JPH0831259B2 - Magnetic stripe demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a magnetic stripe demodulation system for reading and demodulating a magnetic stripe in which a code “1” and a code “0” are recorded on two sets of tracks, the present invention is based on two sets of tracks. First data, which is obtained by arranging the read binary information in the reading order and arranged, and second data, which is arranged by delaying the timing of reading the binary information of either one of the tracks by a predetermined amount, are generated. And a magnetic stripe demodulation circuit for verifying the legitimacy of the second data and demodulating the magnetic stripe signal.
A first data generation circuit for taking in and arranging binary information of a set of tracks at a predetermined timing position of the binary information and generating first data, and from the binary information of one track, from the predetermined timing position. A delay circuit for generating binary information of a predetermined time width, a detecting means for detecting the presence or absence of the generated binary information at the timing of fetching the binary information of the other track of the first data, and the binary value. When the information is detected, it is configured to include a data conversion unit that exchanges the binary information at the detection timing of the first data and the immediately preceding binary information to generate the second data.

[Industrial applications]

The present invention relates to a demodulation circuit of a magnetic stripe recorded by the NRZI method, and more particularly to improvement of a data generation circuit provided to correct skew between tracks.

In passbooks, etc., data is recorded in two sets of tracks (0 track for writing a code "0" and 1 track for writing a code "1") by the NRZI method, but the skew between tracks that occurs during writing or reading In order to correct the above, the demodulation circuit is provided with a three-phase (hereinafter A-phase, B-phase, C-phase) generation circuit.

The three-phase generation circuit has A-phase data in which two sets of read track signals (binary information) are arranged in the reading order, B-phase data in which one track signal is delayed by a predetermined amount, and 0-phase data.
Since the data generating circuit for respectively generating the C-phase data in which the track signals are delayed by a predetermined amount and the buffer for respectively storing the generated data are provided for each of the three phases, increasing the number of correction phases is not possible. The situation was extremely difficult.

Therefore, there is a demand for a magnetic stripe demodulation circuit equipped with a simple correction data generation circuit.

[Conventional technology]

FIG. 5 is an explanatory diagram of a magnetic stripe of a passbook, FIG. 6 is a block diagram of a conventional demodulation circuit, and FIG. 7 is an explanatory diagram of a method of generating phase data.

As shown in FIG. 5, a magnetic stripe in a passbook or the like has a 0 track (0TR) for recording a code “0” and a code “1”.
NRZI (NON RETE) is composed of two sets of magnetic stripes of 1 track (1TR) for recording
The above code is recorded by the RN TO ZERO INVERTED) method.

This magnetic stripe is scanned by the passbook 80 and read by the read head 1. Binary information is arranged and demodulated in the order of reading, but depending on the read / write head position, etc., 0TR
A phase shift (skew) may occur between 1TR and 1TR. To correct this, the A-phase data directly demodulated from the read signal and 1TR data are demodulated by delaying them by a predetermined amount (for example, 0.7 of the bit interval). Three-phase data of the B-phase data and the C-phase data obtained by delaying the 0TR data by a predetermined amount is generated, the correctness of these data is verified, and the correct data is adopted as the demodulation data.

A conventional demodulation circuit will be described below with reference to FIGS. 6 and 7.

1 is a magnetic stripe read head (read head), 2 is an amplifier for 0 track read head (0TR amplifier), 3 is an amplifier for 1 track read head (1TR amplifier), 4 is a timer (0TRT) for delaying the 0 track signal by a predetermined amount.
M), 5 is a timer (1TRT) that delays one track signal by a predetermined amount.
M), 6 are three-phase generation circuits that generate A-phase data, B-phase data, and C-phase data, and 7,8,9 are buffer RAMs 10, 11, and 12 that store the data generated by the three-phase generation circuit 6, respectively. Address counters that generate addresses to store, 10, 11 and 12 are buffer RAMs that sequentially read data of each phase as they occur, and are read synchronously with a common read signal when reading, 13 is a buffer read The gate is.

FIG. 7 shows the data of each phase generated by the demodulation circuit having the above configuration.

Phase A data is read and shaped 0TR signal and 1TR
A signal "1" or "0" corresponding to the track is written in the buffer RAM 10 by a timing signal (corresponding to the rising edge of the signal in FIG. 7) created from the signal and obtained.

As a result, in the example of FIG. 7, the A phase data is (001100).
Becomes

The B-phase data is obtained by writing "1" with a delay of 0.7T, for example, as a skew amount for correcting the 1TR signal with the bit interval T as a reference.
"1", "0" when approaching within 0.7T to TR signal
Is inverted, and the B-phase data becomes (001010).

The C-phase data is written in the buffer 12 with the 0TR signal delayed by 0.7T. When 0TR is 0.7T closer to the trailing 1TR signal, "0" and "1" are inverted and the C-phase data is ( 010
100).

As described above, the three-phase data obtained by writing the data in the buffer RAMs 10 to 12 in the reading order is verified by the horizontal parity provided for a predetermined bit of a plurality of data, and the correctness of each data is verified. Data is adopted. As a result, the data error due to the skew is corrected and restored.

[Problems to be solved by the invention]

The conventional demodulation circuit described above is provided with a data generation circuit, a buffer, an address counter, etc. independently for each of the three phases, and it is extremely difficult to increase the number of phases in order to improve the correction accuracy because of the circuit scale. There was a problem.

In view of the above problems, it is an object of the present invention to provide a magnetic stripe demodulation circuit including a simple data generation circuit.

[Means for solving problems]

For the above-mentioned purpose, in the magnetic stripe demodulation circuit of the present invention, as shown in FIG. 1 for explaining the principle of the present invention, binary information of each bit constituting data is recorded in corresponding two sets of tracks. The magnetic stripe is scanned and read, and at the same time, the first information in which the binary information read from each of the two sets of tracks is taken in and arranged, and the binary information of either one of the binary information of the two sets of tracks. A magnetic stripe demodulation circuit for generating second data arranged by delaying a timing of fetching information by a predetermined amount, and verifying the legitimacy of the first and second data and demodulating a magnetic stripe signal. , Binary information of two sets of tracks having a reading time width is fetched and arranged at a predetermined timing with reference to a predetermined time position of the binary information, and the first data is generated. A first data generating circuit 30 for generating, a delay circuit 31 for generating binary information of a predetermined time width from the predetermined timing position from the binary information of one track, and the presence or absence of the generated binary information, First
Detecting means 32 for detecting the binary information of the other track of the other data at the timing, and when the generated binary information is detected, the binary information of the first data at the detection timing. And a data conversion unit 17 for generating the second data by exchanging the immediately preceding binary information.

[Action]

The first data generation circuit takes in and arranges the binary information read from the two sets of tracks in the reading order to generate the first data (A-phase data). The timing of loading is, for example, the trailing edge of the binary information having a reading time width.

The delay circuit 31 has a predetermined timing position of binary information read from one track (one track in the case of B-phase data generation), for example, a predetermined width from the trailing edge of the above-mentioned binary information, for example, 0.7T. Binary information (pulses) is generated, and the detection means 32 detects the presence or absence of the binary information at the timing at which the binary information read from the other track (0 track) when the A-phase data is generated is fetched. At this time, if the binary information exists, the data conversion unit 17 exchanges the bit at the detection timing and the immediately preceding bit in the A-phase data to generate B-phase data (second data). The same applies to the case of generating C-phase data. Binary information of a predetermined width is generated by a timer from the binary information read from the 0th track, and the presence or absence of the generated binary information of the binary information read from the 1st track. It is detected at the timing of fetching, and if it is present, it is generated by exchanging the corresponding bits of the A-phase data as described above.

The above bit operation can be performed when the A-phase data stored in the buffer is read, and the number of data generating circuits, buffers and the like for each phase, which are conventionally required, can be significantly reduced.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS.

This embodiment is an example of three-phase correction. FIG. 2 is an explanatory view of a data conversion method, FIG. 3 is a block diagram of a demodulation circuit of the embodiment, and FIG. 4 is a block diagram of the data conversion circuit of the embodiment. Show.

FIG. 2 shows a method of converting A-phase data to generate B-phase and C-phase data. For the B-phase data [FIG. 2 (I)], the code “0” of the A-phase data is written. At the timing (the trailing edge of the read track signal), a signal with a predetermined time width from the trailing edge of the 1TR signal (1TR TM5 output, 1TR
When the TM signal 52) is present, it is obtained by converting the bit information of the A-phase data and the bit information before it.

Moreover, since the above-mentioned existence state occurs when the A-phase data is [10], [01] is set to the corresponding bit in this embodiment.

Similarly, for the C-phase data [Fig. 2 (II)], when there is a signal (0TRTM53 output of 0TRTM4) generated from the trailing edge of the 0TR signal, the corresponding 2 bits of the A-phase data are converted or [10]. Obtained by setting.

From the above, the demodulation circuit is configured as shown in FIGS.

In FIG. 3, 14 is an A-phase data generation circuit (first data generation circuit 30).
Then, 0TR output from 0TR amplifier 2 and 1TR amplifier 3
A timing signal (write signal) 54 is generated from the signal and the 1TR signal and is output together with the code corresponding to the track type.

An address counter 15 counts the timing signal 54 and outputs the address data to the buffer RAM 16, which designates the addresses in the order of occurrence.

16 is bit information of A phase data and 0TRTM at the same address
Presence / absence information of signal 52 and 1TRTM signal 53 (“1”, “0”) 52a,
53a is a buffer RAM that stores the data, and 17 is a data conversion unit that generates the B-phase data and the C-phase data together with the A-phase data when the buffer RAM 16 is read out. Represent

The delay circuit 31 corresponds to 0TRTM (0-track timer) or 1TRTM, and the detection means 32 is formed by the buffer 16 and the timing signal 54.

In the above configuration, the A-phase data is generated from the 0TR signal and the 1TR signal, and the presence / absence information 52a, 53a of the 0TRTM signal 52 and the 1TRTM signal 53 and the corresponding bit information of the A-phase data are stored in the same address of the buffer RAM 16. It

At the time of demodulation, the data stored in the buffer RAM 16 is read in the order of occurrence, and each phase data is simultaneously output bit serially based on the data conversion unit 17 shown in FIG.

The data conversion unit 17 uses the A read from the buffer RAM 16.
A 1-bit delay circuit that delays and outputs phase data by 1 bit for each read clock, a B-phase data conversion unit 19 that generates B-phase data, and a C-phase data conversion unit 20 that generates C-phase data.
It is composed of the following components and operates as follows.

The C-phase converter 20 has no 0TRTM signal 52, that is, the code “0”.
In the case of, the A-phase data is directly output through the 1-bit delay circuit 18 and the OR circuit 22, and in the presence information (code “1”), “1” is set to the bit of the preceding A-phase data to “the next bit”. Set to 0 ".

That is, the 0TRTM signal 52 presence information (code "1") read from the buffer RAM 16 is output through the OR circuit 22, and the bit (bit before the presence information) output from the 1-bit delay circuit is converted to "1". To be done.

FF21 delays the existence information "1" by 1 bit. At the next bit position, the output of FF21 becomes "1" and the inverter 23
And "0" is output through the AND circuit 24 (because the presence information is not continuous, "0") and set to "0".

When there is no information (“0”), since the AND circuit 24 is open, the A-phase data delayed by 1 bit is output as it is.

Similar to B-phase data, the circuit shown in FIG.
When the M signal 53 is present, the bit of the A-phase data delayed by 1 bit is set to "0" and the next bit is set to "1".

As described above, according to the presence / absence information of the delayed track signal, the A-phase data can be converted by a simple circuit to read out the B-phase data and the C-phase data. Can be reduced.

〔The invention's effect〕

The present invention uses the presence / absence information of the delayed track signal to
Since the simple magnetic stripe demodulation circuit for converting the phase data to generate the B phase data and the C phase data is provided, the effect of reducing the circuit is extremely large.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is an explanatory view of a data conversion method of an embodiment, FIG. 3 is a block diagram of a demodulation circuit of the embodiment, and FIG. 4 is a block diagram of a data conversion unit of the embodiment. FIG. 5 is an explanatory diagram of a magnetic stripe of a passbook, FIG. 6 is a block diagram of a conventional demodulation circuit, and FIG. 7 is an explanatory diagram of a data generation method of each phase. In the figure, 1 is a read head, 2 is a 0TR amplifier, 3 is a 1TR amplifier, 4
Is OTRTM, 5 is 1TRTM, 6 is a 3-phase data generation circuit, 7 is an A-phase address counter, 8 is a B-phase address counter, and 9 is C.
Phase address counter, 10 is phase A buffer RAM, 11 is phase B buffer RAM, 12 is phase C buffer RAM, 13 is buffer read gate, 14 is phase A data generation circuit, 15 is address counter, 16 is buffer RAM, 17 Is a data converter, 18 is a 1-bit delay circuit, 19 is a B-phase data converter, 20 is a C-phase data converter, 21 is a 1-bit delay circuit, 22 is an OR circuit, 23 is an inverter, 24 is an AND circuit, 30 Is a first data generation circuit, 31 is a delay circuit, 32 is detection means, 52 is a 0TRTM signal, and 52a is
Is presence / absence information of 0TRTM signal, 53 is 1TRTM signal, 53a is presence / absence information of 1TRTM signal, and 54 is a timing signal.

Claims (1)

[Claims] 1. A magnetic stripe in which binary information of each bit constituting data is recorded on two sets of corresponding tracks, and the binary information read from each of the two sets of tracks is fetched in a reading order. Generating first data arranged and second data arranged by delaying a timing for taking in binary information of one of the two sets of binary information by a predetermined amount.
A magnetic stripe demodulation circuit for verifying the legitimacy of each of the first and second data and demodulating a magnetic stripe signal, wherein binary information of two sets of tracks having a read time width is stored in the magnetic stripe demodulation circuit.
A first data generating circuit for generating first data by taking in and arraying the value information at a predetermined timing based on a predetermined time position, and from the binary information of one track, a predetermined time width from the predetermined timing time. And a detecting circuit for detecting the presence or absence of the generated binary information at the timing of fetching the binary information of the other track of the first data. When the value information is detected, a data conversion unit that exchanges the binary information at the detection timing of the first data and the immediately preceding binary information to generate the second data is provided. And a magnetic stripe demodulator circuit.