JPH0831794B2 - Analog / digital conversion method - Google Patents

Description

TECHNICAL FIELD The present invention relates to an analog / digital conversion system for converting an analog signal into a digital signal.

[Conventional technology]

Figure 9 is from the April 14, 1988 issue of ELECTRONICS LETTERS (Vol. 24, No. 8), page 471.
One of the circuit blocks of the / D converter.

Reference numeral 1 is a current input terminal of the electronic circuit 2. Reference numeral 3 is an N-channel MOS transistor, the drain of which is connected to the current input terminal 1. The N-channel MOS transistor 3 is a so-called diode-connected transistor whose gate and drain are connected. The gate of the N-channel MOS transistor 3 is connected to the gates of the N-channel MOS transistors 5a and 5b, and the N-channel MOS transistors 3, 5a and 5b form a current mirror circuit. The drains of the N-channel MOS transistors 5a and 5b are connected to the drain of a diode-connected P-channel MOS transistor 12. Further, the gate of the P-channel MOS transistor 12 is connected to the gates of the P-channel MOS transistors 13 and 14, and the transistors 12,1
3, 14 form a current mirror circuit. Reference numeral 20 is a reference current source that outputs a constant current (reference value amount), and is connected to a diode-connected N-channel MOS transistor 21. The gate of the N-channel MOS transistor 21 is connected to the gates of the N-channel MOS transistors 10 and 11 via the terminal 9, and the transistors 21, 10 and 11 form a current mirror circuit. The drains of the N-channel MOS transistor 10 and the P-channel MOS transistor 13 are
Input to the current comparator 16. The output of the current comparator 16 is
Its source is the drain of the N-channel MOS transistor 11, and its drain is the P-channel MOS transistor 14.
Is connected to the gate of an N-channel MOS transistor 15 which is connected to the drain of each of the. Also, the current comparator
The output of 16 is connected to the digital output terminal 8 and the drain of the P-channel MOS transistor 14 is connected to the current output terminal 6.

Next, the operation will be described. Assuming that the N-channel MOS transistors 3, 5a, 5b forming the current mirror circuit have the same characteristics, the same current as the current input from the current input terminal 1 and flowing through the drain of the transistor 3 is generated in each of the transistors 5a, 5b. Drain current. That is, in accordance with the current (analog input amount) input from the current input terminal 1, a diode-connected N-channel MOS
Although the gate voltage of the transistor 3 changes, since the gates of the N-channel MOS transistors 5a and 5b are connected to the gate of the N-channel MOS transistor 3, the same amount of current as the current flowing to the drain of the transistor 3 is the same as that of the transistor 5a. It also flows to the drain of 5b. Therefore, a current twice as much as the input current flows through the diode-connected P-channel MOS transistor 12. On the other hand, since the P-channel MOS transistors 13 and 14 also form a current mirror circuit together with the P-channel MOS transistor 12, the same current as the drain current of the transistor 12, that is, a current twice the input current, is applied by the same principle as described above. , Transistor 13
And 14 drains. Also, N-channel MOS transistors 21, 10, 11 forming a current mirror circuit
Similarly, the drain currents of the transistors 10 and 11 have the same value as the output current of the reference current source 20.

The current comparator 16 compares the drain current of the P-channel MOS transistor 13 and the drain current of the N-channel MOS transistor 10 and, according to the comparison result, the N-channel MOS transistor.
Open and close the transistor 15. That is, P channel MO
If the drain current of the S transistor 13 is smaller than that of the N-channel MOS transistor 10, a current comparator
The output of 16 becomes a low potential level (logical value 0) and shuts off the N-channel MOS transistor 15. In the opposite case, the output of the current comparator 16 becomes a high potential level (logical value 1) and the N-channel MOS transistor 15 becomes conductive. Let Accordingly, in the former case, the drain current of the P-channel MOS transistor 14 is directly obtained from the current output terminal 6, and in the latter case, the drain current of the P-channel MOS transistor 14 is changed from the drain current of the N-channel MOS transistor 11. The amount of current drawn can be obtained.

 The above operation is summarized as follows.

B = 0 (when 2Iin <Iref) 1 (when 2Iin ≧ Iref) (1) Iout = 2Iin−B · Iref (2) where Iin is the current inflow amount from the current input terminal 1, Iref
Is the current value of the reference current source 20, B is the output logical value of the digital output terminal 8, and Iout is the current outflow amount of the current output terminal 6.
In addition, the conditional expression enclosed by () in expression (1) is 2Iin and Iref
, Which is equivalent to comparing Iin and Iref / 2. FIG. 10 illustrates the operation represented by the equations (1) and (2). When a linearly increasing current such as a straight line 207 is input to the input terminal 1, the current inflow amount Iin becomes I
Output logical value B is 0 and 2Iin until it becomes equal to ref / 2.
Is output as the output current. Current inflow amount Iin is Iref / 2
The output logical value B becomes 1 and the output current changes from Iref to 0 at the moment when it becomes equal to. Then, the current inflow amount Iin is Ire
When the output current exceeds f / 2 and increases to Iref, the output current becomes (2Iin-Ire
Increase again from 0 to Iref according to f).

As an example of using such a conventional circuit, a conventional A / D
An example of the converter configuration is shown in FIG. In FIG. 9, the portion surrounded by the dotted line corresponds to 2 in FIG. 11, and will be referred to as a bit cell hereinafter. The N circuit blocks are cascade-connected via the current input terminal 1 and the current output terminal 6. The current input terminal 1 of the first bit cell 2 located closest to the input side is connected to the current source 22.

The reference current source 20 is a diode-connected N-channel MOS
The drain of the transistor 21 and the terminal 9 of all bit cells 2 are commonly connected.

 The operation of this A / D converter is described below.

In the following, Ik; input current of k-th bit cell Bk; digital output value of k-th bit cell I; current value of current source 22. Since the terminals 9 of all the bit cells 2 are connected to the gates of the N-channel MOS transistors 21 which are commonly diode-connected, the drain currents of the N-channel MOS transistors 10 and 11 of all the bit cells 2 are output from the current source 20. It becomes equal to the current Iref. The operation considering this is as follows. First, in the first bit cell 2, 2I and Iref are compared.

That is, a comparison equivalent to the comparison between I and Iref / 2 is performed. Here, if I is larger than Iref / 2, B ₁ is 1, and in the opposite case, B ₁ is 0, and the first digit of A / D conversion is determined. At this time, the output current is 2I in the former case and 2I-Iref in the latter case. In the second bit cell, these currents are doubled and 4I or 4I-2Iref is compared to Iref. In other words, a comparison equivalent to the comparison between I and Iref / 4 or 3Iref / 4 is performed to determine the second digit. By sequentially determining Bk from the most significant bit B ₁ by such a procedure,
The A / D conversion result is obtained. The above operation will be described with reference to FIG. It should be noted that I ₁ , I ₂ , I ₃ , I ₄ in the drawing correspond to I ₁ , I ₂ , I ₃ , I ₄ , respectively. It is assumed that the current value I of the current source 22 linearly changes from 0 to Iref as in (207a). First, in the first bit cell 2, when I changes from 0 to Iref / 2, the digital output B ₁ (208a) is 0, the output current of this bit cell 2, that is, the input current of the second bit cell 2.
I ₂ (207b) changes from 0 to Iref. Next I is Iref / 2
Changes from Iref to Iref, digital output B ₁ (208a) is 1,
I ₂ (207b) changes from 0 to Iref again. In the second bit cell 2, I (207a) is 1 from 0 to Iref
Since I ₂ (207b) increases twice from 0 to Iref while increasing twice, B ₂ changes 2 from 0 to 1 like (208b).
Repeated times, I ₃ which is the output of this bit cell 2 is (207
Repeat the linear increase from 0 to Iref four times as in c). In the third bit cell 2, I ₃ (207c) changes from 0 to Ir while I (207a) changes once from 0 to Iref.
As it increases to ef four times, B ₃ becomes 0 like (208c).
The change from 1 to 4 is repeated 4 times, and the output I ₄ of the bit cell 2 is linearly increased from 0 to Iref 8 times as in (207c). Thus, changes from I 0 to Iref, the output Bk of the k-th bit cell, as any integer of j from 0 to ^{(2 k-1 -1),} 2j · (Iref / 2 k) ≦ In the case of I <(2j + 1) · (Iref / 2 ^k ), Bk = 0 (3) (2j + 1) · (Iref / 2 ² ) ≦ I <(2j + 2) · (Iref /
In the case of 2 ^k ), Bk = 1 (4). In this way, a digital binary number [B ₁ B ₂ ... B _N ] proportional to the analog quantity I is obtained.

[Problems to be Solved by the Invention]

Although the conventional A / D converter is configured as described above, the conversion speed of the entire A / D converter is impaired because the response speed of the current mirror circuit is slow. For example, consider a current mirror circuit consisting of N-channel MOS transistors 3, 5a and 5b in FIG. The parasitic capacitance of the gate of this current mirror circuit is C ₁ , and the diode-connected N
When the resistance value between the drain and source of the channel MOS transistor 3 is R ₅ , the response speed of this current mirror circuit becomes slower as the time constant C ₁ · R ₅ becomes larger. On the other hand, I ₅ the drain current of N-channel MOS transistor 3, the drain - if the threshold voltage of the source voltage V _DS5, N-channel MOS transistor and _{V THN, I 5 = (β} 5/2) (V DS5 -V _THN ) ² (5) is widely known. Here, β ₅ is a proportional constant that does not depend on V _DS5 . From equation (5), R ₅ is Becomes Here, the current I ₅ input to the bit cell 2 is 0
Since I takes the value of Iref, R ₅ can be infinite. That is, when the input current of the bit cell 2 changes in the vicinity of 0, the next constant C 1 · R _{5 of the} current mirror circuit
Becomes large and the response speed is significantly impaired. As described above, in the conventional A / D converter, the current flowing through the current mirror circuit may be close to 0.
The conversion speed was significantly impaired.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an analog / digital conversion system capable of improving the analog / digital conversion speed.

[Means for solving the problem]

In the analog-digital conversion method according to the first aspect of the present invention, an offset current amount is supplied to each current mirror circuit, and the analog output amount generation means 102 comprises:
When the analog input current amount compared by the comparison means 101 is equal to or less than half the reference value current amount, the analog input current amount is 2
The result of subtracting the offset current amount for each current mirror circuit from the multiple value is generated as the analog output current amount. On the other hand, when the analog input current amount is larger than half the reference value current amount, the analog input current amount It is characterized in that the reference value current amount is subtracted from the doubled value and the offset current amount for each of the current mirror circuits is further subtracted to generate the analog output current amount.

In the analog-digital conversion method according to the second aspect of the present invention, an offset current amount is supplied to each current mirror circuit, and the analog output amount generation means 502 is
When the analog input current amount compared by the comparing means 501 is equal to or less than half of the reference value current amount, the double value of the analog input current amount is subtracted from the reference value current amount and further offset to each of the current mirror circuits. When the analog input current amount is larger than half the reference value current amount, the result obtained by adding three times the current amount is generated as the analog output current amount.
The analog output current amount is generated by subtracting the double value of the analog input current amount from the double value of the reference value current amount and further adding the triple value of the offset current amount for each current mirror circuit. It is what

[Action]

According to the first aspect of the present invention, an offset current amount is supplied to each current mirror circuit, and when the analog input current amount compared by the comparing means 101 is equal to or less than half the reference value current amount, the analog input current amount is 2 The result of subtracting the offset current amount from the doubled value is generated as the analog output current amount. On the other hand, when the analog input current amount is larger than half the reference value current amount, the doubled value of the analog input current amount is used as the reference value. The analog output current amount is generated by subtracting the current amount and the offset current amount.

This second invention supplies an offset current amount to each current mirror circuit, and when the analog input current amount compared by the comparing means 501 is equal to or less than ½ of the reference value current amount, the reference value current amount is converted to an analog value. The doubled value of the input current amount is subtracted and the tripled value of the offset current amount is added, and the result is generated as the analog output current amount. On the other hand, the analog input current amount is larger than half the reference value current amount. In this case, the result obtained by subtracting the double value of the analog input current amount from the double value of the reference value current amount and further adding the triple value of the offset current amount is generated as the analog output current amount.

Example of Invention

An embodiment of the present invention will be described with reference to FIG. Reference numeral 1 is a current input terminal of the electronic circuit 2. Reference numeral 3 is an N-channel MOS transistor, the drain of which is connected to the current input terminal 1. The gate and drain of the N-channel MOS transistor 3 are connected, and this transistor 3 is a so-called diode-connected transistor. The gate of the N-channel MOS transistor 3 is connected to the gates of the N-channel MOS transistors 5a and 5b, and the N-channel MOS transistors 3, 5a and 5b form a current mirror circuit. The drains of the N-channel MOS transistors 5a and 5b are connected to the drain of a diode-connected P-channel MOS transistor 12. Further, the gate of the P-channel MOS transistor 12 is connected to the gates of the P-channel MOS transistors 13 and 14, and the transistors 12, 13, 14 form a current mirror circuit. Reference numeral 20 is a reference current source that outputs a constant current, and is connected to a diode-connected N-channel MOS transistor 21. The gate of the N-channel MOS transistor 21 is connected to the N-channel MOS transistor 10 via the terminal 9.
, 11 connected to the gates of the transistors 20, 10, 11 form a current mirror circuit. The drains of the N-channel MOS transistor 10 and the P-channel MOS transistor 13 are input to the current comparator 16. The output of the current comparator 16 is such that its source is an N-channel MOS transistor 11
N-channel MO, whose drain is connected to the drain of the P-channel MOS transistor 14, respectively.
It is connected to the gate of the S transistor 15. The output of the current comparator 16 is connected to the digital output terminal 8 and the drain of the P-channel MOS transistor 14 is connected to the current output terminal 6.

Reference numeral 30 denotes an offset current source for generating an offset current amount, which is connected to a diode-connected N-channel MOS transistor 31. The gate of the N-channel MOS transistor 31 is connected to the gates of the N-channel MOS transistors 17a, 17b and the N-channel MOS transistor 18 via the terminal 19, and the transistors 31, 18, 17a, 17b form a current mirror circuit. Also, N-channel MOS
The drains and sources of the transistors 17a and 17b are connected in parallel to the drains and sources of the N-channel MOS transistor 10. The drain of the N-channel MOS transistor 18 is connected to the current output terminal 6 and its source is grounded.

The comparing means 101 for comparing the magnitude relationship between the analog input current amount and one half of the reference value current amount and outputting a digital signal corresponding to the analog input current amount is an N-channel MOS transistor 3, 5a, 5b, 10 , 17a, 17b, 21,31 and P channel MOS
It has transistors 12 and 13 and a current comparator 16. The analog output amount generation means 102 for generating an analog output current amount according to the comparison result of the comparison means 101 is an N channel MOS transistor 11, 15, 18, 31 and a P channel MOS transistor 14.
Have and.

Next, the operation will be described. Assuming that the N-channel MOS transistors 3, 5a, 5b forming the current mirror circuit have the same characteristics, the same current as the current input from the current input terminal 1 and flowing through the drain of the transistor 3 is generated in each of the transistors 5a, 5b. Drain current. That is, although the gate voltage of the diode-connected N-channel MOS transistor 3 changes according to the current input from the current input terminal 1, the N-channel MOS transistor 5
Since the gates of a and 5b are connected to the gate of the transistor 3, the same amount of current that flows in the drain of the transistor 3 also flows in the drains of the transistors 5a and 5b.
Therefore, a current twice as much as the input current flows through the diode-connected P-channel MOS transistor 12. On the other hand, P
Since the channel MOS transistors 13 and 14 also form a current mirror circuit together with the P-channel MOS transistor 12, the same current as the drain current of the transistor 12, that is, a current twice the input current is applied to the transistor 13 by the same principle as described above. And 14 drains. Also,
Similarly for the N channel MOS transistors 21, 10 and 11 forming the current mirror circuit, the transistor 1
The drain currents of 0 and 11 have the same value as the output current of the reference current source 20. Further, the drain current of each of the transistors 18, 17a, 17b becomes the same value as the output current of the offset current source 30 by the N-channel MOS transistors 31, 18, 17a, 17b forming the current mirror circuit.

The current comparator 16 detects the drain current of the P-channel MOS transistor 13 and the N-channel MOS transistors 10, 17a,
Compare the sum of the drain currents of 17b, and according to the comparison result, N
Opens and closes the channel MOS transistor 15. Ie N
When the drain current of the channel MOS transistor 13 is smaller than the sum of the drain currents of the N channel MOS transistors 10, 17a and 17b, the output of the current comparator 16 becomes a low potential level (logic value 0) and the N channel MOS transistor 15 is cut off. In the opposite case, the output of the current comparator 16 becomes a high potential level (logical value 1) and the transistor 15 is turned on.
Accordingly, in the former case, a current amount obtained by subtracting the drain current of the N-channel MOS transistor 18 from the drain current of the P-channel MOS transistor 14 is obtained from the current output terminal 6, and in the latter case, the P-channel MOS transistor 14 is obtained. N-channel MOS transistor from the drain current of 1
The amount of current is obtained by subtracting the drain currents of 1 and 18.

 The above operation is summarized as follows.

B = 0 (when 2Iin ′ <Iref + 2Ioff) 1 (when 2Iin ′ ≧ Iref + 2Ioff) (7) Iout ′ = 2Iin′-Ioff-B · Iref (8) where Iin ′ is the current inflow from the current input terminal 1 Amount, Iref
Is the current value of the reference current source 20, B is the output logical value of the digital output terminal 8, IOUT 'is the current outflow amount of the current output terminal 6, and Ioff
Is the current value of the offset current source 30.

FIG. 3 illustrates the operation represented by the equations 7 and 8. However, here, it is assumed that the input current amount Iin 'of the input terminal 1 is Iin' = Iin + Ioff (9) by adding the offset current value to the true input amount Iin in advance. When Iin changes linearly from 0 to Iref / 2, Iin ′ changes from Ioff to (Iref / 2 + Iof
f) changes. In this range, B = 0 according to the conditional expression of the expression (7), and Iout ′ is therefore calculated from Ioff to (I
It changes up to ref + Ioff).

Next, when Iin changes from Iref / 2 to Iref, Iin ′ changes from (Iref / 2 + Ioff) to (Iref + Ioff). In this range, B = 1 according to the conditional expression (7), and Iout ′
From Ioff (Iref + Iof
Repeat the change in f) once more.

As can be seen from the above description, considering equation (9), equation (7) becomes: B = 0 (when 2Iin + 2Ioff <Iref + 2Ioff) 1 (when 2Iin + 2Ioff ≧ Iref + 2Ioff) (10) The conditional expression enclosed by is Iin and Iref /
It is equivalent to the comparison formula in 2. Further, the formula (8) is Iout ′ = (2Iin−B · Iref) + Ioff (11), but if the true current output amount Iout expressed by the formula (2) is used, Iout ′ = Iout + Ioff (12 ). As described above, by equalizing the offset amount included in the input current and the offset amount included in the output current, the multi-stage connection of bit cells described below becomes possible.

FIG. 2 shows a configuration example of an A / D converter using the circuit of such an embodiment. The N circuit blocks are cascade-connected via the current input terminal 1 and the current output terminal 6.
The current input terminal 1 of the first bit cell 2 located closest to the input side is connected to the input current source 22 and the current source 32 having the output amount Ioff equal to that of the offset current source 30. Reference current source 20 is a diode-connected N channel
Drain of MOS transistor 21 and all bit cells 2
Is commonly connected to the terminal 9. Further, the offset current source 30 is commonly connected to the drain of the diode-connected N-channel MOS transistor 31 and the terminals 19 of all the bit cells 2.

The operation of this A / D converter will be described below. In the following, Ik ′; input current of kth bit cell Bk; digital output value of kth bit cell I; current value of current source 22. The drain currents of the N-channel MOS transistors 10 and 11 and the drain currents of the N-channel MOS transistors 17a, 17b and 18 of all bit cells are the reference current Ir.
Considering that it is equal to ef and the offset current Ioff, and the input current of the first bit cell is the sum of the true input current I and the offset current Ioff, that is, I1 ′ = I + Ioff (13), the operation is as follows. Like First, in the first bit cell, 2 (I + Ioff) and (Iref +
2Ioff) are compared. That is, a comparison equivalent to the comparison between I and Iref / 2 is performed. Here, B ₁ is 1 when I is larger than Iref / 2, and B ₁ is 0 in the opposite case, and the first digit of A / D conversion is determined. At this time, the output current is in the former case (2I + Ioff-Iref) and in the latter case (2I + Ioff).
In the second bit cell, these currents are doubled and 2
(2I + Ioff) or 2 (2I + Ioff-Iref) becomes (Iref + 2Io
ff) is compared. This comparison is based on I and Iref / 4 or 3Ire
It can be seen from a simple operation that it is equivalent to the comparison with f / 4. The second digit is determined by this comparison. Thereafter, the A / D conversion result is obtained by sequentially determining Bk from the most significant bit B ₁ by the same procedure.

The above operation will be described with reference to FIG. In addition,
I ₁ ′, I ₂ ′, I ₃ ′ and I ₄ ′ correspond to I ₁ ′, I ₂ ′, I ₃ ′ and I ₄ ′, respectively. Consider a case where the current value I of the current source 22 changes linearly from 0 to Iref and the input current I ₁ ′ of the _first bit cell 2 changes from Ioff to (Iref + Ioff) as in (201a). First, in the first bit cell 2,
When I ₁ ′ changes from Ioff to (Iref / 2 + Ioff), the digital output B ₁ (202a) is 0, the output current of this bit cell, that is, the input current I ₂ ′ (201b) of the _second bit cell 2 is
It changes from Ioff to (Iref + Ioff). Then I ₁ ′ becomes (Ir
When changing from ef / 2 + Ioff) to (Iref + Ioff), the digital output B ₁ (202a) changes to 1, and I ₂ ′ (201b) changes from Ioff to (Iref + Ioff) again. In the second bit cell 2, while I ₁ ′ (201a) increases once from Ioff to (Iref + Ioff), I ₂ ′ (201b) changes from Ioff to (Iref + Iof).
Since it increases twice to f), B ₂ repeats the change from 0 to 1 twice as in (202b), and from Ioff to (Iref + Ioff) like I ₃ ′ (201c) which is the output of this bit cell 2.
Repeat the linear increase up to 4 times. In the third bit cell 2, I ₁ ′ (201a) changes from Ioff to (Iref + Iof
I ₃ ′ (201c) changes from Ioff to (Ire
Since it increases 4 times up to f + Ioff), B ₃ repeats the change from 0 to 1 4 times as in (202c), and the output I ₄ ′ of this bit cell 2 is from Ioff to (Iref as in (201d).
Repeat linear increase up to + Ioff) 8 times. Thus, when I ₁ ′ changes from Ioff to (Iref + Ioff), k
The output Bk of the th bit cell is 2j · (Iref / 2 ^k ) + Ioff ≦ I ₁ ′ <(2j + 1) · (Iref / 2 ^k , where j is an arbitrary integer from 0 to (2 ^k−1 −1). ) + Ioff, Bk = 0 (1
4) (2j + 1) · (Iref / 2 k) + Ioff ≦ I 1 '<(2j + 2) · ( For ^{Iref / 2 k) + Ioff,} Bk = 1 (1
5) In this way, a digital binary number [B ₁ B ₂ ... B _N ] proportional to the analog quantity I is obtained. Where equation (13)
In consideration of, the equations (14) and (15) are exactly the same as the equations (3) and (4).

That is, the conversion result obtained in the above embodiment is
Although not different from the conventional example, as can be seen from FIG. 4, the input current to the bit cell 2 never becomes zero. Therefore,
A current mirror circuit formed by N-channel MOS transistors 3, 5a, 5b and P-channel MOS transistors 12, 13, 1
The current of the current mirror circuit formed by 4 does not become zero, and high-speed operation can be obtained.

Another embodiment of the present invention will be described with reference to FIG. Reference numeral 1 is a current input terminal of the electronic circuit 2. The current input terminal 1 is connected to the drain of a diode-connected P-channel MOS transistor 12. Further, the gate of the P-channel MOS transistor 12 has P-channel MOS transistors 13a and 13b.
And 14a, 14b and the gates of the transistors 12, 13a,
13b, 14a and 14b form a current mirror circuit. 20
Is a reference current source and is connected to a diode-connected N-channel MOS transistor 21. N channel M
The gate of the OS transistor 21 is connected to the gates of the N-channel MOS transistors 10, 11a and 11b via the terminal 9,
The transistors 21, 10, 11a, 11b form a current mirror circuit. An offset current source 30 is connected to the diode-connected N-channel MOS transistor 31. The gate of the N-channel MOS transistor 31 is connected via the terminal 19 to the N-channel MOS transistors 17a, 17b and
Connected to the gates of 18a, 18b and 18c, transistors 31, 17a,
17b, 18a, 18b and 18c form a current mirror circuit. P-channel MOS transistor 13a and P-channel MO
The drains of the S-transistors 13b are connected, and those drains are further input to the positive input terminal of the current comparator 16. The drains of the N-channel MOS transistors 10, 17a and 17b are connected, and the drains are input to the negative input terminal of the current comparator 16. The output of the current comparator 16 has its source connected to the drain of the N-channel MOS transistor 11a and its drain connected to the P-channel MOS transistor 1a.
It is connected to the gate of an N-channel MOS transistor 15, which is commonly connected to the drains of 4a and 14b. The output of the current comparator 16 is connected to the digital output terminal 8, the drains of the P-channel MOS transistors 14a and 14b are connected to the drains of the N-channel MOS transistors 11b, 18a, 18b and 18c, and further to the current output terminal 6. ing.

The comparing means 501 is an N-channel MOS transistor 10,17.
a, 17b, 21,31 and P channel MOS transistor 12,13a, 13b
And a current comparator 16. Analog output amount generation means 50
2 is an N-channel MOS transistor 11a, 11b, 15, 18a, 18
b, 18c, 31 and P-channel MOS transistors 14a, 14b.

Next, the operation will be described. This circuit differs from the conventional example and the first embodiment in that the direction of the current that can be input to the input terminal 1 is the direction in which the current flows from the bit cell 2 to the outside.
The direction of the current that can be output to the output terminal 6 is the direction in which the current flows from the bit cell 2 to the inside. Therefore, the signs of the input amount and the output amount are positive in the outflow direction and the inflow direction, respectively, contrary to the above. Also, the terms “input” and “output” will be used below in terms of expression.

P-channel MOS forming a current mirror circuit
Assuming that the transistors 12, 13a, 13b, 14a, 14b have the same shape, the same current as the current input from the current input terminal 1 and flowing through the drain of the transistor 12 is the same as the transistors 13a, 13a.
It becomes the drain current of each of b, 14a and 14b. That is, the gate voltage of the diode-connected P-channel MOS transistor 12 changes according to the current input from the current input terminal 1, but the P-channel MOS transistor 1
Since the gates of 3a, 13b, 14a and 14b are connected, each drain has the same amount of current as that flowing through the transistor 12. In addition, N forming a current mirror circuit
Similarly for the channel MOS transistors 21, 10, 11a and 11b, the drain currents of the transistors 10, 11a and 11b have the same value as the output current of the reference current source 20. Similarly, for the N-channel MOS transistors 31, 17a, 17b, 18a, 18b, 18c forming the current mirror circuit, similarly, the drain currents of the transistors 17a, 17b and the transistors 18a, 18b, 18c are offset current sources. It has the same value as the output current of 30.

The current comparator 16 calculates the sum of the drain currents of the P-channel MOS transistor 13a and the P-channel MOS transistor 13b, that is, 2Iin and the sum of the drain currents of the N-channel MOS transistors 10, 17a and 17b, that is, (Iref
+ 2Ioff) is compared, and N channel MOS according to the comparison result.
Open and close the transistor 15. That is, 2Iin is (Iref +
2Ioff), the output of the current comparator 16 becomes a low potential level (logical value 0) and the transistor 15 is cut off.
In the opposite case, the output of the current comparator 16 becomes a high potential level (logical value 1), and the transistor 15 is turned on. Accordingly, in the former case, the N-channel MOS transistors 11b and N
A current value obtained by subtracting the drain currents of the P-channel MOS transistors 14a and 14b from the sum of the drain currents of the channel MOS transistors 18a, 18b, and 18c, that is, (Iref + 3Iof
f-2Iin ′) is the latter, from the sum of the drain currents of the N-channel MOS transistors 11a, 11b, 18a, 18b, 18c,
A current value obtained by subtracting the drain currents of the P-channel MOS transistors 14a and 14b, that is, (2Iref + 3Ioff-2Iin ')
Is obtained from the current output terminal 6.

 The above operation is summarized as follows.

B = 0 (when 2Iin ′ <Iref + 2Ioff) 1 (when 2Iin ′ ≧ Iref + 2Ioff) (16) Iout ′ = Iref + B · Iref + 3Ioff-2Iin ′ (17) where Iin ′ is the amount of current outflow from the current input terminal 1, Ire
f is the current value of the reference current source 20, B is the output logical value of the digital output terminal 8, Iout ′ is the current inflow amount of the current output terminal 6, Io
ff is the current value of the offset current source 30.

FIG. 6 explains the operation represented by the equations (16) and (17). However, again, the input current amount of input terminal 1
For Iin ', it is assumed that the equation (9) is established by previously adding the offset current value to the true input amount Iin. Iin is 0 to I
When increasing linearly to ref / 2, 204 in Fig. 6 (1)
Like Iin ′ changes from Ioff to (Iref / 2 + Ioff). In this range, B = 0 according to the conditional expression (7),
Iout ′ is as 206 according to equation (17) (Iref + Ioff)
To Ioff. Next, when Iin changes from Iref / 2 to Iref, Iin ′ changes from (Iref / 2 + Ioff) to (Iref + Ioff
off). In this range, B = 1 according to the conditional expression of the expression (7), and Iout ′ repeats the decrease of Ioff from (Iref + Ioff) again as 206 according to the expression (17). As shown in Fig. 6 (2), Iin is (Iref + Ioff)
To (Iref / 2 + Ioff), Iout 'is Io
Increase from ff to (Iref + Ioff), B = 1, Iin ′ becomes (I
ref / 2 + Ioff) to Ioff, Iout ′ is I
It increases from off to (Iref + Ioff) again, and B = 0.

As can be seen from the above description, considering equation (9), equation (16) becomes: B = 0 (in the case of 2Iin + 2Ioff <Iref + 2Ioff) 1 (in the case of 2Iin + 2Ioff ≧ Iref + 2Ioff) (18) The conditional expression enclosed by is Iin and Iref /
It is equivalent to the comparison formula in 2. Further, the equation (17) becomes Iout ′ = Iref + B · Iref + Ioff−2Iin (19).

As an example using such a second embodiment of the present invention,
FIG. 7 shows a configuration example of the A / D converter. The N circuit blocks are cascade-connected via the current input terminal 1 and the current output terminal 6. It is also located closest to the input side. The current input terminal 1 of the first bit cell 2 is connected to a current source 32 having an output amount Ioff equal to that of the input current source 22 and the offset current source 30. The reference current source 20 is commonly connected to the drain of the diode-connected N-channel MOS transistor 21 and the terminals 9 of all the bit cells 2. Further, the offset current source 30 is commonly connected to the drain of the diode-connected N-channel MOS transistor 31 and the terminals 19 of all the bit cells 2. Each bit cell 2
Of the even-numbered bit cells 2 of the digital output terminals 8 of
The digital output terminal of is to the terminal 100 through the inverter,
The digital output terminal of odd-numbered bit cell 2 is a direct terminal
Tied to 100. The terminal 100 outputs the final conversion result of the A / D converter as described later.

The operation of this A / D converter will be described below. In the following, Ik ′; input current of the kth bit cell Bk; digital output value appearing at the digital output terminal 8 of the kth bit cell Dk; digital output value appearing at the terminal 100 corresponding to the kth bit cell I; current This is the current value of the source 22. Here, Dk = Bk (when k is an odd number) k (when k is an odd number) (20). N-channel MOS transistors 10, 11a, 11b of all bit cells 2 drain current and N-channel MO
The drain currents of the S transistors 17a, 17b, 18a, 18b, and 18c are equal to the reference current Iref and the offset current Ioff, respectively, and the input current of the first bit cell 2 is the true input current Iref as shown in equation (13). Considering that it is the sum of the offset current Ioff and the offset current Ioff, the operation is as follows. First,
In the first bit cell 2, 2 (I + Ioff) and (Iref + 2I
off) are compared. That is, a comparison equivalent to the comparison between I and Iref / 2 is performed. Here, B ₁ is 1 when I is larger than Iref / 2, and B ₁ is 0 in the opposite case. This value is directly output to the terminal 100 as the first digit D ₁ of the A / D conversion result. The output current at this time, when B ₁ is a 0 (Iref + Ioff-2I) , B 1
Is 1 (2Iref + Ioff-2I). In the second bit cell 2, these currents are doubled and 2 (Iref + Ioff
-2I) or 2 (2Iref + Ioff-2I) is compared with (Iref + 2Ioff). It can be seen from a simple operation that this comparison is equivalent to the comparison of I with Iref / 4 or 3Iref / 4. The logical value of this result is inverted by the inverter 101 and is output to the terminal 100 as the second digit D ₂ of the A / D conversion result. An A / D conversion result is obtained by sequentially determining Dk from the most significant bit D _{1 according} to such a procedure.

The above operation will be described with reference to FIG. The current value I of the current source 22 changes linearly from 0 to Iref, and the input current of the first bit cell 2 changes from Ioff to (Ioff
+ Iref) has changed. First, in the first bit cell 2, when I ₁ ′ changes from Ioff to (Iref / 2 + Ioff), B ₁ is 0 and this is directly output to the terminal 100 as the digital output D ₁ as in (205a). The output current of this bit cell, that is, the input current I ₂ '(204b) of the _second bit cell 2 decreases from (Iref + Ioff) to Ioff. Then I ₁ ′ changes from (Iref / 2 + Ioff) to (Iref + Iof
When changes to f) B ₁ and D ₁ are 1 becomes, I ₂ '(204
b) changes from (Iref + Ioff) to Ioff again. In the second bit cell 2, while I ₁ ′ (204a) increases once from Ioff to (Iref + Ioff), I ₂ (201b) changes to (Ir
Since it decreases twice from ef + Ioff) to Ioff, B ₂ repeats the change from 1 to 0 twice as shown in FIG. 6 (204 ′) each time I ₂ ′ decreases. This becomes a digital output D ₂ via the inverter 101, and _two changes from 0 to 1 appear at the terminal 100 as shown in FIG. 8 (205b). The output I ₃ of the bit cell 2 is 1 of I ₂ ′ as shown in FIG. 6 (206 ′).
Fig. 8 (20) shows a linear increase from Ioff to (Iref + Ioff) twice per decrease and _one increase in I ₁ ′.
Repeat 4 times as in 4c). In the third bit cell 2, I ₁ ′ (204a) changes from Ioff to (Iref + Iof
I ₃ ′ (204c) changes from Ioff to (Ire
Since it increases up to f + Ioff) four times, B ₃ repeats the change from 0 to 1 four times, and the digital output D ₃ also changes the same as (205c). The output I ₄ ′ of the bit cell 2 is linearly decreased from Iref + Ioff to Ioff as shown in (204b) eight times. Thus, I ₁ ′ is Io
When changing from ff to (Iref + Ioff), Dk generated from the output Bk of the k-th bit cell 2 changes j from 0 to (2 ^k-1
As an arbitrary integer up to -1), if 2j · (Iref / 2 ^k ) + Ioff ≦ I ₁ ′ <(2j + 1) · (Iref / 2 ^k ) + Ioff, Dk = 0 (2
1) (2j + 1) · (Iref / 2 k) + Ioff ≦ I <(2j + 2) · ( For ^{Iref / 2 k) + Ioff,} Dk = 1 (2
2) In this way, a digital binary number [D ₁ D ₂ ... _DN ] proportional to the analog quantity I is obtained. Where equation (13)
(21) and (22) are exactly the same as equations (3) and (4). That is, although the change result obtained in this embodiment is completely the same as that of the conventional example, the input current to the bit cell 2 does not become zero as can be seen from FIG. Therefore, P-channel MOS transistor 1
The current of the current mirror circuit formed by 2, 13a, 13b, 14a, 14b does not become zero, and high-speed operation can be obtained.

As described above, the input current value and the output current value of the bit cell are the value obtained by adding the offset current to the true analog current value, and the input offset current value and the output offset current value are equalized, It enables multi-stage cascade connection of bit cells. Moreover, the current value flowing through the current mirror circuit does not become zero regardless of the amount of analog input to the A / D converter.

In the above embodiment, the present invention is applied to the configuration of the A / D converter capable of chaining A / D conversion results from the most significant digit. High accuracy can be achieved even when applied to a type A / D converter.

Further, the current mirror circuit is composed of a diode-connected transistor and a single transistor paired with the diode-connected transistor, but any functional circuit having an equal input current and output current or having a predetermined ratio may be used. For example, a Wilson current mirror circuit or the like may be used.

〔The invention's effect〕

As described above, according to the first aspect of the present invention, when the offset current amount is supplied to each current mirror circuit and the analog input current amount compared by the comparison means is equal to or less than half the reference value current amount, the analog input is performed. The result obtained by subtracting the offset current amount for each current mirror circuit from the double current amount is generated as the analog output current amount. On the other hand, when the analog input current amount is greater than half the reference value current amount, the analog output current amount is increased. Since the reference current amount is subtracted from twice the input current amount and the offset current amount for each current mirror circuit is subtracted, the result is generated as the analog output current amount. The current amount and the offset current amount included in the output current become equal, and the current of the current mirror circuit becomes zero regardless of the analog input current amount. No Rukoto, effect that thereby possible to improve the analog / digital conversion speed.

According to the second aspect of the present invention, when the offset current amount is supplied to each current mirror circuit and the analog input current amount compared by the comparing means is equal to or less than half the reference value current amount, the analog input is performed from the reference value current amount. The value of twice the current amount is subtracted, and the offset current amount for each current mirror circuit is set to 3
Generate the result of adding the doubled value as the analog output current amount,
On the other hand, when the analog input current amount is larger than ½ of the reference value current amount, the double value of the analog input current amount is subtracted from the double value of the reference value current amount, and the offset current for each current mirror circuit is further added. Since it is configured to generate the result of adding the triple value of the amount as the analog output current amount,
The offset current amount included in the input current and the offset current amount included in the output current become equal, and the current of the current mirror circuit does not become zero regardless of the analog input current amount. The effect that it can improve is acquired.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a bit cell according to an embodiment of the present invention, FIG. 2 is an operation explanatory diagram of the bit cell according to the embodiment, FIG. 3 is a configuration diagram of an analog / digital conversion system according to the embodiment, and FIG. FIG. 6 is a diagram for explaining the operation of an analog / digital conversion system according to an embodiment, FIG. 5 is a circuit configuration diagram of a bit cell according to another embodiment of the present invention, FIG. 6 (1),
(2) is an operation explanatory diagram of a bit cell according to another embodiment, FIG. 7 is a configuration diagram of an analog / digital conversion method according to another embodiment, and FIG. 8 is an operation explanation of an analog / digital conversion method according to another embodiment. Fig. 9 is a circuit configuration diagram of a conventional bit cell, Fig. 10 is an operation explanatory diagram of a conventional bit cell,
FIG. 11 is a configuration diagram of a conventional analog / digital conversion A / D converter, and FIG. 12 is an operation explanatory diagram of a conventional analog / digital conversion A / D converter. 101,501 ... Comparison means, 102,502 ... Analog output amount generation means.

Claims (2)

[Claims] 1. An analog input current amount is compared with a reference value current amount, and if the analog input current amount is ½ or less of the reference value current amount based on the comparison result, a logical value 0 is set, Analog input current amount is half of the above reference value current amount
If it is larger, it has a comparison means for outputting a digital signal having a logical value of 1, and an analog output amount generation means for generating an analog output current amount according to the comparison result of this comparison means. In an analog-digital conversion method having each current mirror circuit made of a transistor, an amount of offset current is supplied to each of the current mirror circuits, and the analog output amount generation means comprises:
When the analog input current amount compared by the comparison means is equal to or less than half the reference value current amount, the analog input current amount is 2
The result of subtracting the offset current amount for each current mirror circuit from the multiple value is generated as the analog output current amount. On the other hand, when the analog input current amount is larger than half the reference value current amount, the analog input current amount An analog-digital conversion method characterized in that a reference value current amount is subtracted from a doubled value, and a result obtained by further subtracting an offset current amount for each of the current mirror circuits is generated as an analog output current amount. 2. An analog input current amount is compared with a reference value current amount, and if the analog input current amount is ½ or less of the reference value current amount based on the comparison result, a logical value of 0 is set, Analog input current amount is half of the above reference value current amount
If it is larger, it has a comparison means for outputting a digital signal having a logical value of 1, and an analog output amount generation means for generating an analog output current amount according to the comparison result of this comparison means. In an analog-digital conversion method having each current mirror circuit made of a transistor, an amount of offset current is supplied to each of the current mirror circuits, and the analog output amount generation means comprises:
When the analog input current amount compared by the comparing means is equal to or less than ½ of the reference value current amount, a double value of the analog input current amount is subtracted from the reference value current amount and further offset for each current mirror circuit. When the analog input current amount is larger than half the reference value current amount, the result obtained by adding three times the current amount is generated as the analog output current amount.
The analog output current amount is generated by subtracting the double value of the analog input current amount from the double value of the reference value current amount and further adding the triple value of the offset current amount for each current mirror circuit. The analog / digital conversion method.