JPH0831892B2 - Interface system for high-speed digital leased line - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface system for a high-speed digital leased line for controlling data communication with respect to the accommodated high-speed digital leased line.

[0002]

2. Description of the Related Art When a high-speed digital leased line is accommodated in a data communication control unit, conventionally, a host processor in the data communication control unit directly controls the accommodated high-speed digital leased line.

[0003]

However, if the host processor in the data communication control device is so constructed as to directly control the communication of the high-speed digital leased line as in the prior art, each line interface is selected according to the type of the leased line. Circuit and host processor software required,
This causes a problem of being uneconomical in constructing the device.

Therefore, it is an object of the present invention to economically configure a device by omitting the line interface circuit and software for each type of dedicated line when controlling the communication of the accommodated high-speed digital dedicated line. .

[0005]

In order to solve such a problem, the present invention provides CCITTV. 24. 24 interconnect circuitry to the host processor, and Control for inserting transmission data to the high-speed digital leased line into a predetermined channel and extracting received data from the high-speed digital leased line from the predetermined channel between the interconnection circuit and the high-speed digital leased line. A control unit for performing the control and a pseudo response unit for monitoring the control information to the high-speed digital leased line and the status signal from the high-speed digital leased line and notifying the host processor of the monitoring result are provided. Also, host pro
High-speed digitization of transmission data and control information from the sessa side
The first to convert to the Tal leased line frame format
A frame decoder section and this first frame decoder section
The signal output from the
First level converter to convert to bell and high speed digital
The signal received from the leased line can
Second level converter for converting to adaptive code and high-speed digit
Received data from the frame format of the Tal leased line.
Second frame decoder unit for extracting data and control information
And are provided. Also, the host processor and
Send to the high-speed digital leased line side under the control of the control unit
Receives transmission data to the device side immediately before the first level converter
It has a loopback part that folds back as data.
It

[0006]

Operation: Before the data communication is started, the V. When the control information is output to the high-speed digital leased line side via the 24 interconnection circuit, the pseudo response unit monitors the status signal from the high-speed digital leased line. Then, data communication is started by the host processor based on this monitoring result, and this communication data is inserted and extracted into a predetermined channel by the control unit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a data communication control device, and this data communication control device 1 accommodates a high-speed digital leased line (hereinafter referred to as line) 2 and controls the communication thereof. Here, the digital communication control device 1 is configured as follows. That is, 10 is a host processor, 11
Is a CCITTV., Which transmits and receives data and control information between the host processor 10 side and the line 2 side. 24. Reference numeral 24 is an interconnection circuit, 12 is a frame decoder section for converting the transmission data and control information from the host processor side into the frame format of the line 2, 13 is a level conversion section for converting the compatible code for the line 2 and the electrical level. , 14 are transmission transformers connected to the transmission side line of the line 2.

Further, 15 is a receiving transformer connected to the receiving side line of the line 2, 16 is a level converting unit for converting the received signal from the line 2 into an electric level and an adaptive code inside the apparatus, and 17 is a line. A frame decoder unit for extracting received data and control information from the frame format of No. 2 is a control for inserting transmission data to the line 2 into a predetermined channel and extracting received data from the line 2 from the predetermined channel. A control unit 19 performs a loopback unit that loops back transmission data to the line 2 side as reception data to the device side immediately before the input side of the level conversion unit 13 under the control of the host processor 10 and the control unit 18, and 20 is a host processor. The host processor 10 monitors the control information from 10 and the status signal from the line 2 and edits it.
This is a pseudo response unit for notifying the user as control information.

Next, the operation of the data communication control device 1 configured as described above will be described. When data is transmitted from the data communication control device 1 to a partner device (not shown) via the line 2, the host processor 10 first sends the V.V. 24 A transmission request signal is output as control information via the interconnection circuit 11. When the transmission request signal is output, the pseudo response unit 20 monitors the status signal from the line 2 obtained from the frame decoder unit 17. When it is detected from the above status signal that the line 2 is in the synchronization established state, V. 24 interconnection circuit 11
A transmission permission signal is returned as control information to the host processor 10 via.

Upon reception of this transmission permission signal, the host processor 10 starts transmitting data to the partner device via the line 2. In this case, the transmission data is inserted into the channel defined by the frame format preset by the control unit 18 in the frame decoder unit 12, and sent to the line 2 side via the level conversion unit 13 and the transmission transformer 14. Further, data from the partner device side via the line 2 enters the frame decoder unit 17 via the receiving transformer 15 and the level converting unit 16, and similarly from the corresponding channel in the channels of the frame format preset by the control unit 18. The extracted V. 24 is received by the host processor 10 via the interconnection circuit 11.

As described above, the line 2 accommodated and the host processor 10 in the data communication control device 1 are connected to the V. Since the connection is possible via the 24 interconnection circuit 11, the conventional line interface circuit different for each communication line and the software of the host processor 10 related thereto are unnecessary. In addition, V. Even in other general-purpose devices having the same input / output as the 24 interconnection circuit, data transmission / reception can be performed through the accommodated high-speed digital leased line without the dedicated interface circuit by using the configuration of this embodiment. it can.

In the data communication control device 1, when the line 2 or the data communication control device 1 has a failure, the host processor 10 outputs a test signal as control information in order to isolate these failures. Loopback part 1
In 9, when the test signal is received, the data transmitted from the host processor 10 is returned to the frame decoder 17 side immediately before the level conversion unit 13 and given to the host processor 10 as received data. As a result, it becomes possible to perform an internal loopback test in the data communication control device 1.

[0013]

As described above, according to the present invention, the V. While connecting 24 interconnection circuits,
This V. A pseudo response unit and a control unit are provided between the H.24 interconnection circuit and the high-speed digital leased line, and the V.V. When the control information is output to the high-speed digital leased line side through the 24 interconnection circuit, the pseudo response unit monitors the status signal from the high-speed digital leased line, and the host processor performs data communication based on the monitoring result. When this is started, this communication data is configured so that the control unit inserts and extracts from a predetermined channel, so that the same configuration can be used even if the types of dedicated lines accommodated differ. Therefore, the software of the conventional line interface circuit and host processor for each type of dedicated line can be omitted, so that the device can be economically constructed.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus to which an interface system for a high-speed digital leased line according to the present invention is applied.

[Explanation of symbols]

 1 data communication control device 2 high-speed digital leased line 10 host processor 11 V.V. 24 interconnection circuit 12, 17 frame decoder section 13, 16 level conversion section 18 control section 19 loopback section 20 pseudo response section

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location 9371-5K H04L 13/00 315 Z

Claims (3)

[Claims] 1. A data communication control device for accommodating a high-speed digital leased line and having a host processor for controlling data communication via the high-speed digital leased line, comprising: CCITTV. 24. 24 interconnect circuitry to the host processor, and Two
Control for inserting the transmission data to the high-speed digital leased line into a predetermined channel between the interconnection circuit and the high-speed digital leased line and extracting the reception data from the high-speed digital leased line from the predetermined channel. A high-speed digital-only device, which is provided with a control unit for performing the control, and a pseudo-response unit for monitoring control information to the high-speed digital dedicated line and a status signal from the high-speed digital dedicated line and notifying the host processor of the monitoring result. Line interface method. 2. The method according to claim 1, further comprising: 24 interconnection circuit and high-speed digital circuit
Between the line and the line, send data from the host processor side and
And control information for high-speed digital leased line
A first frame decoder section for converting to matte, and
The signal output from the frame decoder unit of No. 1 inside the line
Adaptive code and first level change to electrical level conversion
A converter and a signal received from a high-speed digital leased line
Second level converting to internal electrical level and adaptive code
Converter and frame for high-speed digital leased line
Retrieving received data and control information from the mat
And a frame decoder section of 2 are provided.
High speed digital leased line interface method. 3. The high-speed disk drive according to claim 2, wherein the host processor and the control unit control the high-speed disk.
First level conversion of transmission data sent to the digital line
Loop loop that returns to the device as received data immediately before the instrument
Dedicated high-speed digital circuit characterized by having a clock section
Line interface method.