JPH0831965B2 - Video signal frame detector - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal frame detection device,
It can be used for video equipment such as switchers.

2. Description of the Related Art In a current television system, when displaying an image on a receiver, a line for horizontal scanning is placed between each other on the first and second sheets (interlaced scanning), and limited transmission is performed. Improves vertical resolution in the band. In order to do this, 2
The number of scanning lines of the screen for one sheet is set to an odd number, and the horizontal synchronizing signal is used for each line and the vertical synchronizing signal is used for each screen.
Therefore, on the first sheet, the beginning of the horizontal synchronizing signal and the beginning of the vertical synchronizing signal coincide with each other, and on the second sheet, the beginning of the vertical synchronizing signal is exactly in the middle of the horizontal synchronizing signal. The video signal is added with a composite sync signal including such a vertical sync signal and a horizontal sync signal. One unit of this screen is called a field, and the two units are collectively called a frame. A field in which the beginnings of the horizontal / vertical sync signals coincide with each other is called an odd field, and the other field is called an even field. That is, one frame is composed of two fields, odd and even. In addition, in the NTSC system, the phase relationship between the vertical synchronizing signal and the color subcarrier makes one cycle in four fields. Therefore, four field numbers of 1st, 2nd, 3rd, and 4th are given to the repetition of odd / even / odd / even fields.

When editing and connecting video signals with studio video equipment such as VTRs and switchers for broadcasting and professional use, in order to maintain the continuity of the sync signal, the video signal frame (field odd / even, In the VTR, operations such as recording and editing are performed so that the relationship between the frames of the control signal and the video signal recorded by the servo is made constant in the VTR. An example of the conventional frame detection method will be described with reference to FIG. 4 and waveforms of respective parts in FIG. In FIGS. 4 and 5, 1 is a vertical sync signal, 2 is a composite sync signal, 3 and 7 are latches, 4 is a horizontal signal generator, 8 is a frame signal (a signal representing odd / even of a field, hereinafter simply It is described as a frame signal). The composite sync signal 2 is applied to the clock input of the latch 3, and the vertical sync signal 1 is applied to the data input. Since the vertical synchronizing signal 1 is separated from the composite synchronizing signal by integration or the like, it is slightly behind the state in the composite synchronizing signal. The vertical signal 5 shown in FIG. 5 is obtained at the output of the latch 3. on the other hand,
The horizontal signal 6 is generated by the horizontal signal generator 4 from the composite synchronizing signal. The horizontal signal generator 4 can be composed of a monostable multivibrator (MM) or the like, and removes the equalization pulse. The signal 5 is input to the clock input of the latch 7, and the horizontal signal 6
To the data input of the latch 7, and the frame signal 8 is obtained at its Q output. The frame signal 8 has a high level in the first and third fields and a low level in the second and fourth fields.

Problems to be Solved by the Invention The configuration of FIG. 4 operates stably for a stable signal without noise or dropout, but when there is dropout or noise in the VTR playback signal, Latching may occur at a position other than the normal sync signal, or the sync signal at the point to be originally latched may be missing, resulting in malfunction. In addition, when recording a reproduction signal from a device that cannot control the frame state of the video signal like a home VTR and does not know in which frame relationship the video signal is recorded, FIG. When the frame of the video signal is detected by the configuration like this and it is used as the servo reference, this signal is continuous 30
There is a problem that the servo is disturbed because it does not become Hz (in the case of NTSC) (disturbed at the point where the video signal frame becomes discontinuous).

Means for Solving the Problems In order to solve the above problems, the present invention relates to a vertical signal which represents a constant delay position from the leading edge of the vertical synchronization signal created from the vertical synchronization signal in the video signal, and The first means for detecting the odd / even of the field of the frame of the video signal and outputting the frame information signal from the horizontal signal having a constant width created from the horizontal synchronizing signal in the video signal, the vertical signal being 1/2 Second means for dividing the frequency into a second means, comparing the frame information signal output from the first means with the frequency-divided output signal from the second means, and creating a signal indicating a match / mismatch between the two signals. 3 means, the output signal of the third means is integrated and then shaped, so that the discrepancy between the frame information signal output from the first means and the divided output signal of the second means is kept for a certain period. Fourth to detect persistence Means, fifth means for switching the second means to means having the same function as the first means when the output signal of the fourth means indicates the continuation of the mismatch, and control from the outside. A signal has a sixth means for interrupting the output of the fourth means from the fifth means and always holding the second means in the frequency dividing function. There is provided a video signal frame detection device characterized in that the output signal of the second means is obtained as a frame signal to be expressed.

By comparing the frame information signal with the frequency-divided output and integrating the output into a mismatch detection signal, no detection signal is generated even if the frame information signal is inverted for a short period due to noise or dropout. The frequency divider maintains the previous frequency division state and outputs continuous 30Hz (NTSC). On the other hand, if this mismatch is maintained, a mismatch detection signal is generated and it is determined that the frequency division output is different from the correct frame signal, and the operation of the frequency divider is switched so that the frequency divider output matches the frame information signal. In this way, the frame signal of the video signal which is not affected by the temporary signal disturbance can be obtained at the output of the frequency divider. Also, when recording a signal with no frame continuity, such as a home VTR playback signal, the output of the frequency divider is disabled by prohibiting the switching operation by the disagreement signal to the frequency divider with an external control signal. It can output stable 30Hz (NTSC), though no frame can be taken.

EXAMPLE The present invention will be described with reference to FIG. 1 showing an example of the present invention and FIG. In FIG. 1, the same numbers as those in FIG. 4 represent the same items and operate in the same manner. 9 is a frame information signal, 10 and 18 are switches, 11 is a frequency divider, 12 is a comparator, 14 is an integrator, 16 is a waveform shaper, 19 is a control signal, 20
Is a frame signal. A frame information signal 9 (corresponding to FIG. 8) is created in the same manner as in FIG. 4 (first means). On the other hand, the vertical signal 5 is guided to the frequency divider 11. When performing normal frame detection, the switch 18 is connected to the upper side by the external control signal 19. Also, switch 10 is a signal
When 17 is at a low level, it is connected to the lower side, and the frequency divider 11 composed of D-type flip-flops simply performs frequency division by two, and Q
The signal 20 is output from the output (second means). The signal 9 and the signal 20 are guided to the comparator 12 which is constituted by an exclusive OR, and the output signal 13 thereof has a low level when both signals match and has a high level when they differ (third means). ). The signal 13 integrated by the integrator 14 and shaped by the waveform shaper 15 (fourth means) controls the switch 10 via the switch 18 (fifth means). When signal 9 and signal 20 are connected and coincident, signal 13 stays low, so signal 17 stays low, switch 10 is connected to the bottom side, and divider 11 is only two halves. It operates as a frequency divider and outputs a frame signal 20 that matches the frame information signal 9 to its Q output. Now, as shown in FIG. 2, from point A to point B
The signal 9 and the signal 20 match up to the point, and if the signal 9 has a reverse polarity due to some influence at the point B and returns to normal again at the point C, the signal 13 becomes as shown in the figure. 1 frame is
In the case of NTSC, since it is 30 Hz, the time from point B to point C in the figure is 1/15 second. The signal 13 is led to the integrator 14. If the time constant of the integrator (here, the time until the signal 15 reaches the threshold level of the waveform shaper 16) is set to 1 second to several seconds, the output of the integrator 14 is 1/15 second. The signal 15 does not reach the threshold level of the waveform shaper 16 as shown, and the output signal of the waveform shaper remains low. Therefore, the switch 10 maintains the state of being connected to the lower side, the signal 20 does not have the opposite polarity, and the frame signal can be stably output. On the other hand, when the power is turned on or the signal is applied, signal 9 and
When the mismatch of 20 continues for more than the time constant of the integrator 20, the signal 15 reaches the threshold point of the waveform shaper 16 and the signal 17 becomes high level at the time E when the time set by the time constant is reached. At this point, the switch 10 is connected to the upper side, the frequency divider 11 operates as a latch, and operates the same as the latch 7,
At point F, signal 20 matches signal 9. Therefore, at this point F, the signal 13 becomes low level again, the signal 15 changes as shown in the figure, the signal 17 returns to low level at the point G, the switch 10 is again connected to the lower side, and the frequency divider is 11 operates as a mere frequency divider and stabilizes. In this way, it is possible to perform stable frame detection that is temporary and is not affected by noise or dropout. This protection period can be set by appropriately selecting the time constant of the integrator 14 in relation to the response speed.

Next, the case where the frame continuity is not fixed like the playback signal of a home VTR will be described. When recording such a signal, it is not possible to perform servo in synchronization with the frame, so continuous 30Hz only from vertical information
It is necessary to make (NTSC). Therefore, in such a case, the switch 18 that can be switched by the external control signal 19
The control signal of the switch 10 is always set to a low level, and the frequency divider 11 is always operated as a simple frequency divider (sixth means) so that the frequency is stable at 30 Hz regardless of the frame of the input video signal.
(NTSC) 20 can be obtained. As described above, according to the present invention, even when the frame servo is not performed, a stable circuit is provided only by adding the switch 18 without providing a separate circuit.
You can create Hz.

FIG. 3 shows and explains another embodiment of the present invention. In FIG. 3, the same numbers as those in FIG. 1 represent the same items and operate in the same manner. 21 is a frequency divider and 22 is a switch. Third
The device shown in the figure operates in principle the same as the device shown in FIG. 1, but differs only in the configurations of the frequency divider 21 and the switch 22. Divider 21
The (second means) is composed of a flip-flop or the like having a reset terminal R, and the switch 22 is connected to the lower side when the output signal of the switch 18 is low level and to the upper side when the output signal is high level ( Fifth means). When switch 22 is connected to the lower side, the reset input of divider 21 is always low,
The frequency divider 21 repeats simple frequency division by two (sixth means). When the switch 22 is connected to the upper side, the frame information signal 9 is applied to the reset input of the frequency divider 21, and the output of the frequency divider 21 is reset and controlled so as to coincide with the signal 9. In this way, in the case of FIG. 3 also, exactly the same operation as in FIG. 1 is performed.

As described above, according to the present invention, stable frame detection can be performed without being affected by noise and dropout, and when a frame detection operation causes inconvenience, only a switch is used. A stable 30Hz (NTSC / PALM, PAL / PAL / PAL /
In case of SECAM, 25Hz) signal can be created.

Further, the circuit of the present invention can be constructed by a digital circuit except for the periphery of the integrator 14, which is advantageous for IC implementation. When performing IC, two pins, an output to the integrator 14 and an input from the integrator 14, are necessary. If the switch 18 is provided immediately after the integrator 14 and the waveform shaper 16 as in the present invention and the output signal of the switch 18 is input to the IC, the operation when frame detection is not performed is added. Not (Switch 18
There is no operation), without increasing the number of pins,
Further, the external circuit can be performed without increasing the number other than the switch 18, and the IC can be effectively formed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram of each part of the figure, FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. 4 is a block diagram of a conventional frame detection device.
FIG. 5 is a waveform chart of each part of FIG. 3,7 ... Latch, 11,21 ... divider, 12 ... comparator, 14 ...
… Integrator, 16 …… Wave shaper, 10,18,22 …… Switch.

Claims (2)

[Claims] 1. A vertical signal representing a constant delay position from the leading edge of the vertical synchronizing signal created from the vertical synchronizing signal in the video signal and a horizontal signal having a constant width created from the horizontal synchronizing signal in the video signal. First detecting odd / even of field of frame of video signal and outputting frame information signal
Means, the second means for dividing the vertical signal in half, and the frame information signal output from the first means and the divided output signal of the second means are compared, and both signals are compared. Third means for creating a signal indicating match / mismatch, the first signal by integrating and shaping the output signal of the third means.
Means for detecting that the disagreement between the frame information signal output from the means and the frequency-divided output signal from the second means continues for a certain period, and the output signal from the fourth means maintains the disagreement. Means for switching the second means to a means having the same function as the first means,
And a sixth means for cutting off the output of the fourth means from the fifth means and keeping the second means in the frequency dividing function by a control signal from the outside. 2. A frame detecting device for a video signal, wherein the output signal of the second means is obtained as a frame signal representing the odd / even. 2. An integrated circuit having first to third means and fifth means built-in, having an output terminal of the third means and a terminal for inputting an output signal of the fourth means, and an external circuit. 4 means, and by the control signal from the outside, the fourth
The video signal frame detection device according to claim 1, characterized in that the output of said means is cut off from said fifth means.