JPH0832004B2 - Video signal digital storage - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a video signal for A / D converting an analog video signal and storing the same, such as an image memory device for storing one screen of the video signal. The present invention relates to a digital storage device.

[Conventional technology]

FIG. 3 shows an image memory device as a conventional digital storage device for video signals used in a VTR [video tape recorder] or a television receiver.

The NTSC video signal is input to the sampling clock generation circuit 21 and the A / D conversion circuit 22. The sampling clock generation circuit 21 generates a sampling clock for one screen (one field or one frame) by the vertical / horizontal synchronizing signals of the input video signal and the reference signal from the memory control circuit 23. This sampling clock is sent to the A / D conversion circuit 22. As a result, the A / D conversion circuit 22 samples the video signal based on this sampling clock, quantizes it by 6 bits, and converts it into a digital signal. This digital signal is 6
The bits are sent in parallel to the image memory device 24.
At this time, the memory control circuit 23 uses the clock from the sampling clock generation circuit 21 to set an address that advances from the start value by one address by the image memory element 24.
Send to Therefore, in the image memory element 24, the A / D conversion circuit 2
The 6-bit digital signal sent from 2 is sequentially stored in this address.

When reading the digital signal for one screen stored in this manner, the memory control circuit 23 sequentially sends to the image memory element 24 the address which advances from the start value by one address at a time. Therefore, the latch circuit 25 sequentially latches the digital signal of each address of the image memory element 24 based on the control signal from the memory control circuit 23, and sends it to the decoder circuit 26. Decoder circuit 26
Decodes the sent 6-bit digital signal to restore an analog video signal. Then, the video signal output from the decoder circuit 26 is the CRT display device 27.
It is sent to and the image is projected.

Such an image memory device is used for still display and image quality improvement in TVs, VTRs and the like.

[Problems to be Solved by the Invention]

Here, the horizontal scanning frequency of the video signal in the NTSC system is 15.734 kHz. However, the mainstream of CRT display video signals in personal computers is 31.5 kHz, which has a horizontal scanning frequency twice as high as this.

Therefore, if an image signal for this personal computer is to be stored using the configuration of the conventional image memory device, all circuit elements including the peripheral circuits including the A / D conversion circuit 22 and the image memory element 24 will be stored. Needs to have a high processing frequency.

Therefore, conventionally, as the frequency of the sampling clock required by the analog signal to be stored becomes higher, it is necessary to use a circuit element having a higher processing frequency corresponding thereto, which causes a problem that the apparatus becomes expensive. Was.

[Means for solving the problem]

A video signal digital storage device according to the present invention, in order to solve the above problems, in a video signal digital storage device for A / D converting an analog video signal and storing the same, horizontal scanning of an input analog video signal. Of the frequencies, either the predetermined first frequency or the second frequency that is twice the first frequency is detected, and when the first frequency is detected, the first determination signal is output, A horizontal scanning frequency detection circuit that outputs a second determination signal when the second frequency is detected, a sampling clock generation circuit that generates a sampling clock having a frequency corresponding to the first frequency, and a sampling clock generation circuit A first A / D conversion circuit for A / D converting an analog video signal based on a rising edge and a first A / D conversion circuit for storing the digital video signal output from the first A / D conversion circuit Storage device, a second A / D conversion circuit for A / D converting the analog video signal based on the falling edge of the sampling clock, and a second video signal storing the digital video signal output from the second A / D conversion circuit. 2 storage devices and the digital video signals stored in the first storage device are read in the order of writing based on the first determination signal from the horizontal scanning frequency detection circuit, and the digital video signals stored in the first storage device are read based on the second determination signal. A read control circuit for alternately reading the digital video signals stored in the first storage device and the second storage device in the order of writing, and an analog image originally input from the digital video signal read by the read control circuit. And a decoder circuit that restores a signal.

[Action]

According to the digital storage device for video signals having the above configuration,
The 1A / D conversion circuit performs conversion based on the rising edge of the sampling clock, and the second A / D conversion circuit performs conversion based on the falling edge of the sampling clock. Is the 1st A / D
It can be performed at a timing substantially in the center of each sampling interval in the conversion circuit.

Further, since the sampling clock has a frequency corresponding to the first frequency, it is possible to sample the video signal having the horizontal scanning frequency of the second frequency which is twice the first frequency. That is, since the first and second A / D conversion circuits can perform sampling at half the frequency of the sampling clock that is originally required, the sampling clock corresponding to the first frequency can double the first frequency. A video signal having a horizontal scanning frequency of 2 can be sampled.

Further, since the sampling clock generated by the sampling clock generation circuit has a frequency corresponding to the first frequency, the video signal having the horizontal scanning frequency of the first frequency should be converted by the first A / D conversion. You can

The read control circuit reads the digital video signals stored in the first storage device in the order of writing based on the first determination signal from the horizontal scanning frequency detection circuit, and based on the second determination signal. Since the digital video signals stored in the first storage device and the second storage device are alternately read in the order of writing, video signals having different horizontal scanning frequencies can be automatically discriminated and read. .

Furthermore, since the first storage device and the second storage device are individually controlled by the control signal of the read control circuit, the write processing can be performed at the same processing frequency as the sampling clock. Then, the read control circuit temporarily latches the digital signals read from the respective storage devices, and alternately fetches the digital signals from the storage devices and connects them, so that the reading processing in the respective storage devices is performed at the same processing frequency as the sampling clock. be able to.

Therefore, the digital storage device of the present invention has a sampling clock of 2 times which is originally necessary for the stored video signal.
Since the processing in each circuit element can be performed based on the frequency of one-half, it is possible to reduce the manufacturing cost by using the circuit element having a low processing frequency.

From the above, the digital storage device of the present invention uses, for example, an inexpensive circuit element having the same low processing frequency as the sampling clock in the NTSC video signal as the video signal having the horizontal scanning frequency of the first frequency. , NT
It is possible to automatically discriminate and store not only the video signal of the SC system but also the storage of the video signal for the personal computer as the video signal having the horizontal scanning frequency of the second frequency which is twice the first frequency. it can. That is, in the digital storage device of the present invention, it is possible to automatically discriminate and store video signals having different horizontal scanning frequencies with an inexpensive device using a circuit element having a low processing frequency.

Note that the second A / D conversion circuit inverts the sampling clock generated by the sampling clock generation circuit and performs sampling based on the sampling clock of the opposite phase, so that the pulse used in the first A / D conversion circuit rises. The same A / D conversion circuit that performs sampling in can be used. That is, the second A / D conversion circuit in this case is
It is composed of a circuit (which may be an inverter circuit) that generates a sampling clock of a reverse phase and an A / D conversion circuit that performs sampling at the rising edge of a pulse. Further, when using two A / D conversion circuits that perform sampling at the trailing edge of the pulse, it suffices to use this anti-phase sampling clock in the first A / D conversion circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

In this embodiment, the horizontal scanning frequency of the NTSC system is 15.734.
As a digital storage device of a video signal capable of storing one screen of a video signal of kHz (first frequency) and a video signal of a horizontal scanning frequency of 31.5 kHz (first frequency) used in a personal computer or the like. The image memory device will be described.

The video signal is the horizontal scanning frequency detection circuit 1 and the first A / D
It is adapted to be sent to the conversion circuit 2 and the second A / D conversion circuit 3. The horizontal scanning frequency detection circuit 1 separates a vertical / horizontal synchronizing signal from the input video signal. Further, the horizontal scanning frequency detection circuit 1 determines whether the horizontal scanning frequency of this video signal is 15.734 kHz or 31.5 kHz. That is, the horizontal scanning frequency detection circuit 1 determines whether the horizontal scanning frequency of the input analog video signal is 15.734 kHz or 31.
If it is 5kHz, it is detected if 15.734kHz is detected.
When the 31.5 kHz is detected, the second determination signal is output. The output terminal of the vertical / horizontal synchronizing signal separated by the horizontal scanning frequency detecting circuit 1 is connected to the sampling clock generating circuit 4. The output terminal of the discrimination signal discriminated by the horizontal scanning frequency detection circuit 1 is connected to the memory control circuit 5. The memory control circuit 5 sends a reference signal to the sampling clock generating circuit 4 based on the input discrimination signal. The sampling clock generating circuit 4 generates a square-wave-shaped positive-phase sampling clock and a negative-phase sampling clock based on the reference signal and the vertical / horizontal synchronization signals. The negative-phase sampling clock is an inversion of the positive-phase sampling clock. The sampling clock generation circuit 4 also supplies a clock signal having the same frequency as these sampling clocks to the memory control circuit 5.
It is supposed to be sent to. Based on this clock signal, the memory control circuit 5 generates an address signal that advances from the start value by one address and control signals for a first latch circuit 8, a second latch circuit 9 and a changeover switch 10 which will be described later. .

The output terminal of the positive phase sampling clock generated by the sampling clock generation circuit 4 is connected to the clock input of the first A / D conversion circuit 2. The output terminal of the sampling clock of the opposite phase is connected to the clock input of the second A / D conversion circuit 3. Each A / D conversion circuit 2/3
Is a circuit that performs A / D conversion by sampling the input video signals and performing 6-bit quantization at the rising timings of the sampling clocks of the positive and negative phases. Therefore, the video signal is substantially sampled at a frequency twice the sampling clock. The 6-bit parallel output terminals of the digital signals A / D converted by these A / D conversion circuits 2 and 3 are connected to the first image memory element 6 and the second image memory element 7, respectively.

The image memory elements 6 and 7 are storage elements each capable of storing a digital signal for one screen of a video signal in the NTSC system. The output terminals of the address signals generated by the memory control circuit 5 are connected to the address inputs of the image memory elements 6 and 7, respectively. Therefore, each of the image memory elements 6 and 7 sequentially writes and stores the input 6-bit digital signal based on the address signal. The 6-bit parallel output terminals of these image memory elements 6 and 7 are connected to the first latch circuit 8 and the second latch circuit 9, respectively.
The input and output of these image memory devices 6 and 7 can be in the bus form.

The latch circuits 8 and 9 are circuits for respectively latching 6-bit digital signals. First latch circuit 8 and second latch circuit 9 generated by the memory control circuit 5
The output terminals of the control signal of are connected to the control terminals of these latch circuits 8 and 9, respectively.
Therefore, each of the latch circuits 8 and 9 has the image memory element 6 and 9 at the rising timing of these control signals.
The digital signal read from 7 is latched. The 6-bit parallel output terminals of these latch circuits 8 and 9 are respectively connected to the two switching inputs of the changeover switch 10.

The change-over switch 10 is a circuit for switching and outputting one of two systems of 6-bit parallel inputs. Then, the changeover switch 10 generated by the memory control circuit 5
The control signal output terminal of is connected to the control terminal of the changeover switch 10. Therefore, based on this control signal, the changeover switch 10 outputs the digital signal latched by the first latch circuit 8 when this control signal is at "H" level, and the second latch circuit when it is at "L" level. The digital signal latched in the circuit 9 will be output. The 6-bit parallel output terminal of the changeover switch 10 is connected to the decoder circuit 11.

Therefore, the memory control circuit 5, the first latch circuit 8, the second latch circuit 9, and the changeover switch
10 and 10 constitute a read control circuit for reading the digital signals stored in the image memory elements 6 and 7 in the order of writing.

The decoder circuit 11 is a circuit that sequentially decodes an input digital signal and restores an analog video signal. The output terminal of the decoder circuit 11 is connected to the CRT display device 12. When the changeover switch 10 outputs a digital signal at "H" level and "L" level in the control signal having the same frequency as the sampling clock, the decoder circuit 11 performs the decoding process at a frequency twice the sampling clock. There is a need to do.

The CRT display device 12 is a device for displaying the video signal of the input analog signal on the screen of the CRT. The CRT display device 12 is also adapted to switch the horizontal scanning frequency according to the input video signal.

The operation of the image memory device having the above configuration will be described with reference to FIG.

If the input video signal is for a personal computer with a horizontal scanning frequency of 31.5 kHz, the horizontal scanning frequency detection circuit 1 determines this and issues a determination signal to that effect to the memory control circuit 5.

The first A / D conversion circuit 2 performs A / D conversion of the video signal based on the rising edge of the positive-phase sampling clock. Therefore, even-numbered digital signals such as 0th, 2nd, 4th, etc. when the video signal is sampled at a frequency twice the sampling clock are stored in the first image memory element 6. In addition, the second A / D conversion circuit 3
Performs A / D conversion of the same video signal based on the rising edge of the sampling clock of the opposite phase. Therefore, odd-numbered digital signals such as the first, third, fifth, ... When this video signal is sampled at a frequency twice the sampling clock are stored in the second image memory element 7. The even-numbered and odd-numbered digital signals are respectively supplied to the image memory elements 6 and 7 based on the address signal from the memory control circuit 5.
It is written in order from the top address of. The address signals sent to the respective image memory elements 6 and 7 may have the same address, but the writing timing is different, so the phase of the one sent to the second image memory element 7 is delayed.

When the digital signals stored in the respective image memory elements 6 and 7 are read out in this way, the memory control circuit 5 again issues an address signal that advances by 1 from the start value, and the first latch circuit 8 and the second latch circuit The control signals of the circuit 9 and the changeover switch 10 are emitted. Second
Delaying the phase of the address signal sent to the image memory element 7 is similar to the case of writing. First latch circuit 8
The control signal of is a square wave having the same frequency as the sampling clock. The control signal of the second latch circuit 9 is an inversion of the control signal of the first latch circuit 8. Each of the latch circuits 8 and 9 performs a latch operation at the rising edge of these control signals. Further, the control signal of the changeover switch 10 has the phase of the control signal of the first latch circuit 8 90
° It was delayed.

Then, first, based on the address signal, the digital signals stored in the respective image memory elements 6 and 7 are alternately read in the order of writing. Then, the read digital signals are alternately latched in the respective latch circuits 8 and 9 based on the control signals of the latch circuits 8 and 9. And
Based on the control signal of the changeover switch 10, the latched digital signals are alternately output from the changeover switch 10 in sequence.

Therefore, for example, if the 0th digital signal is output when the control signal of the changeover switch 10 is at the "H" level, the first digital signal is output at the next "L" level, and the "H" level is further output. Then, the second digital signal is output, and thereafter the digital signals are output in the order of sampling, so the same digital signal as when the original video signal is A / D converted at a frequency twice the sampling clock can be obtained. it can. The processing operation of each circuit up to this point is based on the same processing frequency as the sampling clock.

The horizontal scanning frequency of the input video signal is 15.734kHz N
In the case of the TSC system, the horizontal scanning frequency detection circuit 1 discriminates this and the memory control circuit 5
Then, a discrimination signal to this effect is issued. Then, the memory control circuit 5 always outputs a control signal of "H" level to the changeover switch 10 so that the first latch circuit 8 outputs only the latched digital signal. Further, an address signal having a delayed phase with respect to the second image memory element 7 is unnecessary, and the sampling clock generation circuit 4
Also, the opposite phase sampling clock is not sent to the second A / D conversion circuit 3. Therefore, in this case, the operation is similar to that of the conventional image memory device shown in FIG.

As described above, in the image memory device of the present embodiment, if the input video signal is of the NTSC system with the horizontal scanning frequency of 15.734 kHz, A / D conversion is performed only by the first A / D conversion circuit 2.
It is designed to be stored in the image memory device 6, and
If the input video signal is for a personal computer with a horizontal scanning frequency of 31.5 kHz, it is A / D converted by the first A / D conversion circuit 2 and the second A / D conversion circuit 3, and the image memory element 6 and the image are converted. It is adapted to be stored in the memory element 7. When the horizontal scanning frequency is the NTSC system, the pixels are read from the pixel memory element 6 in the writing order, and when the horizontal scanning frequency is for a personal computer, the pixels are read from the pixel memories 6 and 7 in the writing order alternately. Has become. That is, the input analog video signal is automatically discriminated, stored, and read even if it has different horizontal scanning frequencies.

Therefore, the image memory device of the present embodiment has a decoder circuit.
With the exception of the 11 and CRT display device 12, all circuits are configured with the same low processing frequency as the sampling clock of the NTSC video signal, but the horizontal scanning frequency is doubled as well as the NTSC video signal. It is possible to automatically discriminate and store one screen of the video signal for the personal computer.

〔The invention's effect〕

As described above, the digital storage device for analog signals according to the present invention, in the digital storage device for video signals for A / D converting the analog video signals and storing the same, the horizontal scanning frequency of the input analog video signals Of which, a predetermined first frequency or a second frequency twice the first frequency is used.
A horizontal scanning frequency detection circuit that detects any one of the frequencies and outputs a first determination signal when the first frequency is detected and outputs a second determination signal when the second frequency is detected. A sampling clock generation circuit for generating a sampling clock having a frequency corresponding to the first frequency, a first A / D conversion circuit for A / D converting an analog video signal based on the rising edge of the sampling clock, A first storage device for storing a digital video signal output from the first A / D conversion circuit, and an analog video signal for A / D conversion based on the fall of the sampling clock.
Based on a second A / D conversion circuit for converting, a second storage device for storing the digital video signal output from the second A / D conversion circuit, and a first determination signal from the horizontal scanning frequency detection circuit. The digital video signals stored in the first storage device are read in the writing order, and the digital video signals stored in the first storage device and the second storage device are alternately written in the writing order based on the second determination signal. And a decoder circuit that restores the digital video signal read by the read control circuit to the original input analog video signal.

As a result, video signals having different horizontal scanning frequencies can be automatically discriminated, stored and read out, and the stored video signals are processed on the basis of a half frequency of the sampling clock originally required. Therefore, the circuit element having a low processing frequency can be used.

Therefore, since the digital storage device of the present invention can use the A / D conversion circuit and the storage device having a low processing frequency, the cost of the device can be reduced. Further, even when the video signal needs to be sampled at a high frequency, the operation margin of the circuit is improved, so that the reliability of the device can be improved.

[Brief description of drawings]

1 and 2 show an embodiment of the present invention. FIG. 1 is a block diagram of an image memory device, and FIG. 2 is a time chart showing each signal waveform of the image memory device. FIG. 3 shows a conventional example and is a block diagram of an image memory device. 1 is a horizontal scanning frequency detection circuit, 2 is a first A / D conversion circuit, 3
Is a second A / D conversion circuit, 4 is a sampling clock generation circuit, 5 is a memory control circuit (read control circuit), 6
Is a first image memory element (first storage circuit), 7 is a second image memory element (second storage circuit), 8 is a first latch circuit (read control circuit), and 9 is a second latch circuit (read control circuit). ,
Reference numeral 10 is a changeover switch (readout control circuit), and 11 is a decoder circuit.

Claims (1)

[Claims] 1. A digital storage device for a video signal for A / D converting an analog video signal for storage, wherein a predetermined first frequency or a first frequency among horizontal scanning frequencies of the input analog video signal is used. Any one of the second frequencies, which is twice the frequency, is detected, the first determination signal is output when the first frequency is detected, and the second determination signal is detected when the second frequency is detected. , A horizontal scanning frequency detection circuit, a sampling clock generation circuit for generating a sampling clock having a frequency corresponding to the first frequency, and A / D conversion of an analog video signal based on the rising edge of the sampling clock. A first A / D conversion circuit, a first storage device for storing the digital video signal output from the first A / D conversion circuit, and a first storage device based on the fall of the sampling clock. A second A / D conversion circuit for A / D converting the analog video signal based on the above, a second storage device for storing the digital video signal output from the second A / D conversion circuit, and the horizontal scanning frequency detection circuit The digital video signals stored in the first storage device are read out in the order of writing based on the first determination signal from the memory device and stored in the first storage device and the second storage device based on the second determination signal. A read control circuit for alternately reading the read digital video signal in the order of writing; and a decoder circuit for restoring the digital video signal read by the read control circuit to the original input analog video signal. Characteristic video signal digital storage device.