JPH0832072B2 - Automatic frequency controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an automatic frequency control device (hereinafter referred to as an AFC device) in a video tape recorder, and particularly to a horizontal sync signal separated from a video signal and a fixed ratio. An AFC device can be easily obtained by digital signal processing using a low operating clock that is related.

(Prior Art) Conventional AFC devices are widely used, for example, in home VTRs.

To record a color video signal on a magnetic tape or the like, a method is used in which the luminance signal is FM-modulated and the carrier color signal is frequency-converted to the low frequency side. Then, during reproduction, the luminance signal is demodulated and the carrier color signal is returned to the original frequency.

In UHS home VTRs, the frequency of the carrier color signal frequency converted to the low frequency side (hereinafter referred to as the low frequency conversion carrier color signal) is 40 _% of the frequency f _H of the horizontal synchronizing signal in the case of NTSC signal.
In case of PAL signal, it is 40 times 1/8. In order to obtain a low-frequency conversion carrier color signal of such a frequency and to return to the original frequency, an AFC device and an automatic phase control device (hereinafter referred to as an APC device) have been installed in the conventional AFC device. Then, a signal with a frequency of 40 times the frequency f _H of the horizontal synchronizing signal or 40 1/8 times is obtained, and the burst signal in the carrier color signal to be recorded at the time of recording with the APC device and the variable frequency oscillator. Phase comparison with the signal from, the variable frequency oscillator is controlled with the comparison output, the reproduction burst signal and the reference subcarrier signal are phase compared with each other during reproduction, and the variable frequency oscillator is controlled with the comparison output. The signal from the device and the signal from the variable frequency oscillator of the APC device are supplied to the frequency converter to obtain a signal for frequency conversion during recording and reproduction.

FIG. 5 is a block diagram of a conventional AFC device by analog signal processing in this home VTR. Five
01 is a video signal input terminal, 502 is a sync separation circuit that separates the horizontal sync signal from the video signal, 503 is a phase comparator that generates a voltage corresponding to the phase difference between the two input signals, 50
4 is a voltage controlled oscillator whose oscillation frequency changes according to the control voltage, 505 is the first frequency dividing circuit, 506 is a loop filter, 50
Reference numeral 7 is a second frequency dividing circuit, and 508 is an output terminal of a continuous signal which has a constant frequency relationship with the horizontal synchronizing signal in the input video signal and is phase-synchronized.

The operation of the conventional AFC device configured as described above will be described below. When a video signal is input from the input terminal 501, the sync separation circuit 502 separates the horizontal sync signal from the video signal. The phase comparator 503 compares the phase of the horizontal synchronizing signal and the output signal of the voltage controlled oscillator 504 with the signal divided by the first frequency dividing circuit 505, and outputs a signal corresponding to the phase difference. This phase difference signal is a loop filter
It is input to the voltage controlled oscillator 504 as a voltage via 506,
The oscillation frequency is controlled so that the phase difference becomes smaller. Here, the loop filter 506 has a low-pass characteristic and an appropriate gain, removes high-frequency components generated in the phase comparator 503, and determines the synchronization characteristic and response characteristic of the AFC device. The first frequency dividing circuit 505 determines the ratio between the frequency of the horizontal synchronizing signal (hereinafter, referred to as f _H ) and the oscillation frequency of the voltage controlled oscillator 504, and the frequency dividing ratio of the frequency dividing circuit 505 is determined. Is 1 / a, the oscillation frequency of the voltage controlled oscillator 504 is af _H. In the case of VHS type VTR, AF
The frequency required for the C device output signal is NTS as described above.
40f _H in C method, in PAL method Therefore, in order to make the division ratio an integer in the PAL method, a = 320 in the NTSC method and a = 321 in the PAL method, and the division ratio of the second dividing circuit 507 is 1/8. And it is sufficient.

(Problems to be Solved by the Invention) However, the above-described configuration has the following problems when it is replaced with digital signal processing as it is.

For example, in VHS / VTR, when the head crosses between adjacent tracks on the tape during high-speed playback or reverse high-speed playback of the tape recorded in the NTSC 4-hour mode or PAL 6-hour mode, A skew corresponding to a half period of the horizontal synchronization cycle (hereinafter referred to as 0.5H) is generated. In the conventional AFC device, the phase comparator compares the phase of the horizontal sync signal with the output signal of the voltage controlled oscillator that oscillates at the horizontal sync frequency. 1/2 of cycle
There is a problem that the AFC operation is greatly disturbed by detecting an error phase of a magnitude corresponding to. In a special case, the same problem may occur when a signal without the equalization pulse in the vertical synchronizing period removed as the horizontal synchronizing signal enters the AFC device. In order to solve this problem, phase comparison in the phase comparator is performed by using a horizontal sync signal and a signal having a cycle of 1/2 the horizontal sync cycle (frequency 2f _{H which is} twice the horizontal sync frequency). Good. However, in the configuration of the conventional AFC device described above, for example, the PAL in the VTR is
In order to use a signal with a frequency of 2f _H as the comparison signal with the horizontal synchronizing signal in the phase comparator in the system, the dividing frequency of the first frequency dividing circuit is set to 321 and the oscillation frequency of the voltage controlled oscillator is horizontally synchronized. It must be 642 times the frequency (642f _H ). At this time, the output signal frequency of the voltage controlled oscillator is about 10 MHz. Therefore, when the above configuration is replaced with digital signal processing, the operation clock needs to have a high frequency of 20 MHz or more, which is twice that of the operation clock. there were. Here, the case of VHS / VTR is taken as an example, but in other applications, a higher clock frequency may be required.

In view of the above problems, it is an object of the present invention to easily provide an AFC device by digital signal processing without requiring a particularly high operating clock frequency. Further, the present invention detects that the AFC operation is not disturbed even when the horizontal sync signal causes a skew jump of 0.5H during special playback of a VTR, and further that the 0.5H skew occurs. And the signal to correct this
It is also an object of the present invention to provide an AFC device that also has a 0.5H skew detection function of sending to a 0.5H skew correction circuit.

Furthermore, the present invention is applicable to the case where the tape recorded in the NTSC system or the PAL system is reproduced at high speed or reverse high speed, or when the equalization pulse in the vertical synchronization period is not removed as a horizontal synchronization signal and enters the AFC device. In either case, it is an object to provide an AFC device that does not significantly disturb the operation of the AFC.

(Means for Solving the Problems) In order to solve the above problems, the automatic frequency control device of the present invention includes a sync separation means for separating a horizontal sync signal from an input video signal, and a reference for generating a reference angular frequency signal. Angular frequency signal generating means, integrating means for integrating the difference between the reference angular frequency signal and the error angular frequency signal to obtain a phase signal, and detecting the value of the phase signal at the time corresponding to the horizontal synchronizing signal. An error phase detection means for obtaining an error phase signal, a phase / angular frequency conversion means for applying a constant attenuation characteristic and a low-pass characteristic to the error phase signal to convert the error phase frequency signal into the error angular frequency signal, and the integration means. Adding means for adding a predetermined number to the obtained phase signal, means for correcting skew from the phase signal obtained by the integrating means, and the phase signal obtained by the adding means for the amplitude signal. It is provided with a phase / amplitude converting means for converting.

(Operation) According to the present invention, the integration means output signal (which corresponds to the voltage controlled oscillator output signal described in the configuration of the conventional AFC device) requires a phase signal corresponding to a particularly high frequency. No. (typically the horizontal synchronizing frequency or twice the frequency thereof), so that an AFC device by digital signal processing can be configured without using a particularly high operating clock.

Further, according to the present invention, the phase comparison in the error phase detection means is performed by the horizontal synchronization signal and the phase signal having a half cycle of the horizontal synchronization signal, so that the horizontal synchronization signal generated at the time of special reproduction of the VTR or the like. It is possible to realize an AFC device in which the AFC operation is not disturbed even for a 0.5H skew jump.

Further, according to the present invention, by using a bit signal having a horizontal synchronizing frequency f _H and a bit signal having a frequency 2 f _H which is twice the horizontal synchronizing frequency among the digital signals output from the integrating means, the VTR special A 0.5H skew detection circuit for detecting a 0.5H skew occurrence of a video signal generated at the time of reproduction and sending the detected signal to the 0.5H skew correction circuit can be easily configured in the AFC device.

(Embodiment) FIG. 1 shows a block diagram of an AFC device by digital signal processing in an embodiment of the present invention. In FIG. 1, 101 is a video signal input terminal, 102 is a sync separation circuit for separating a horizontal sync signal from the video signal, 103 is a reference angular frequency signal generator, and 104 is an error angular frequency signal subtracted from the reference angular frequency signal. Subtractor, 105 an integrating circuit for converting an angular frequency signal into a phase signal, 106 an error phase detecting circuit for obtaining an error phase signal from a horizontal synchronizing signal and a phase signal, 107
Is a phase / angular frequency converter that gives the error phase signal a constant attenuation characteristic and a low-pass characteristic, 108 is a multiplier that multiplies the input signal by a constant multiplier b, and 109 is an output of the multiplier 108 for another phase. Reference numeral 110 is an adder for adding signals, 110 is a phase / amplitude converter for converting a phase signal into an amplitude signal, 111 is an output terminal for the amplitude signal, 112 is a 0.5H skew detection circuit, and 113 is a 0.5H skew correction circuit.

The operation of the AFC device of this embodiment configured as described above will be described below. Note that the sampling cycle in digital signal processing is T and an arbitrary time is nT.

When video signal is input to input terminal 101, sync separation circuit 1
02 separates the horizontal synchronizing signal from the video signal. The reference angular frequency signal generator 103 gives a reference value proportional to the frequency f _HO of the standard horizontal synchronizing signal, and this is referred to as the reference angular frequency signal W _HO . The subtractor 104 subtracts the error angular frequency signal ΔW (nT) from the reference angular frequency signal W _HO to obtain the angular frequency signal W _HO.
Output (nT). The integrating circuit 105 outputs the angular frequency signal W (n
T) is integrated and converted into a phase signal Φ (nT). The error phase detection circuit 106 compares the phase of the horizontal sync signal (frequency f _H ) from the sync separation circuit 102 with the phase of the output signal of the integration circuit 105, detects the phase difference, and detects this as T _H (= 1 / f _H ), and this output signal is the error phase signal ΔΦ (mT _H ). Phase and the angular frequency converter 107, error phase signal ΔΦ (mT _H) of the error angle frequency signal [Delta] W (m
And converts the T _H), with a suitable low-pass characteristics as needed and a predetermined gain. Here, the subtractor 104, the integration circuit 105, the error phase detection circuit 106, the phase / angular frequency converter 107
It constitutes the AFC loop, when the AFC loop is fully phase synchronized, the output signal ΔΦ (mT _H) of the error phase detecting circuit 106 becomes zero or constant value. The output signal of the integration circuit 105 is a signal that represents the phase of a continuous signal of frequency f _H that is synchronized with the horizontal synchronization signal, and the output signal of the error phase detection circuit 106 is an amount that indicates a deviation from the synchronization state. The gain of the phase / angular frequency converter 107 determines the response speed of the AFC device, and the closer the gain is to T / T _H , the faster the AFC response. By the way, in the AFC device, when a VTR skew occurs, for example, when the head of a VTR having a plurality of heads is switched, high-speed reproduction, reverse high-speed reproduction, etc. However, it is desirable to respond instantaneously, but there is a conflicting requirement that no response should be made to the disturbance that the horizontal synchronizing signal receives regardless of the color signal. However, if the gain of the phase / angular frequency converter 107 is set to a constant value, these contradictory requirements cannot be satisfied at the same time. In order to satisfy these requirements at the same time, the signal level of the error phase signal may be detected and the gain of the phase / angular frequency converter 107 may be switched according to the level. That is, when the signal level of the error phase signal is high, such as when a skew occurs, set the gain to a value close to T / T _H to slow the response of the AFC, and when the signal level of the error phase signal is low due to the influence of disturbance, etc. , The gain should be set to a value much smaller than T / T _H to slow down the AFC response.

The multiplier 108 multiplies the phase signal of the output signal of the integration circuit 105 by a constant multiplier b, and the output signal of the multiplier 108 is
The signal represents the phase of a continuous signal having a frequency of bf _H. VH
In S / VTR, NTSC system b = 40, PAL system Is.

FIG. 2 shows a concrete circuit configuration example of the multiplier 108 in the VHS / VTR. In the figure, 201 is a signal input terminal, 202, 203 and 204 are multipliers having multiplicands of 32, 8 and 1/8 respectively, 205 and 206 are adders, and 207 is a control signal input terminal for switching the PAL method to the NTSC method. , 208 are respective bits of the output signal of the multiplier 204 and a control signal input terminal 207.
AND circuit that takes the logical product with the PAL / NTSC switching signal from 209
Is a signal output terminal. Here, the multiplier 202, the multiplier 203
And the multiplier 204 can be realized as a simple adder by simply bit-shifting the digital signal. In the case of PAL system, a high signal is output to the control signal input terminal 207 as NTSC.
In the case of the system, a low signal is input. As a result, when a signal representing the phase of a signal having a frequency of f _{H is} input to the signal input terminal 201, the signal output terminal 209 is 40 f _{H in the} NTSC system and in the PAL system. A signal representing the phase of the signal having the frequency of is output.

The adder 109 adds another phase signal Φ _P (nT) to the output phase signal of the multiplier 108, where Φ _P (nT) is AP
In the signal from the device C and the VHS / VTR, the phase of the color signal is shifted by 90 degrees for each horizontal scanning period. This is the 90 degree shift signal. The phase / amplitude converter 110 converts a phase signal into an amplitude signal, for example, a sine wave signal, and can be easily realized by using a ROM in digital signal processing.

In the above, the integrating circuit 105 is expressed so as to convert the angular frequency signal into the phase signal by the integrating operation. Is expressed as Therefore, Φ (nT) = Φ (nT−T) + W (nT−T) · T, and the integration circuit output at time nT is the integration circuit output at time (nT−T) and the angular frequency signal W. (NT-T) and sampling period T
Can be thought of as the product of Therefore, in the reference angular frequency signal generator 103, if the constant T is multiplied in advance, the integrating circuit can be configured simply by an adder and a delay circuit that delays the signal by the time T. In the present invention, the expression "angular frequency signal" includes a signal obtained by multiplying an arbitrary constant including the period T.

By the way, the output phase signal of the integrator circuit 105 has a different cycle depending on how many lower bits of the digital signal represent the phase signal. Now, assuming that the phase signal of the horizontal synchronization cycle is represented by l bits, the 1 + bit signal obtained by adding 1 bit to the upper part thereof represents the phase signal having a cycle twice as long as the horizontal synchronization cycle, and conversely the upper 1 bit is represented. The scraped l-1 bit signal represents a phase signal having a period of 1/2 of the horizontal synchronization period.

The value of the error phase detected by the error phase detection circuit 106 varies depending on how many bits of the output signal of the integration circuit 105 are used to detect the error phase. When the horizontal synchronizing signal always comes in every horizontal synchronizing period, the error phase detection may be performed using the phase signal of the horizontal synchronizing period.
However, when the horizontal sync signal may come in at an interval of 1/2 of the horizontal sync cycle, for example, NTSC in VHS / VTR.
When the head crosses between adjacent tracks on the tape during high-speed playback or reverse high-speed playback of the tape recorded in the system 4-hour mode or the PAL system 6-hour mode, the equalization pulse in the vertical synchronization period is generated. If error phase detection is performed using the phase signal of the horizontal sync cycle when a horizontal sync signal that has not been removed comes in, the detected error phase will be a phase value equivalent to 1/2 of the horizontal sync cycle. , AFC operation will be greatly disturbed. To deal with this problem, error phase detection is 1 / of the horizontal sync period.
It may be performed using a phase signal having a period of 2, that is, a signal obtained by removing the upper 1 bit of the phase signal having a horizontal synchronization period.
This way, the AFC operation will not be disturbed even in the above cases. Also, depending on the case, the switching means selectively switches whether to perform the error phase detection using the phase signal of the horizontal synchronization cycle or the phase signal of the half of the horizontal synchronization cycle. Good.

The 0.5H skew detection circuit 112 detects the horizontal synchronization signal when it is shifted by 1/2 cycle (0.5H) of the horizontal synchronization signal, and the 0.5H skew correction circuit 113 detects the 0.5H skew signal 0.5 based on this detection signal. It corrects the skew of H. As described above, 0.5H skew may occur in the reproduced signal during VTR special reproduction. 0.5H skew detection circuit 112
Detects the occurrence of skew of 0.5H at such time simply by using the phase signal obtained from the integrating circuit 105.

FIG. 3 shows a configuration example of the 0.5H skew detection circuit 112 and the 0.5H skew correction circuit 113. In the figure, 3
01 is a video signal input terminal, 302 is a 0.5H signal delay device that delays the video signal by 0.5H, and 303 is a signal switching circuit that inputs two signals and selectively outputs one of them according to a control signal. 304 is an output terminal of a video signal in which a skew of 0.5H is corrected, 305 and 306 are input terminals of a signal of a specific bit of a phase signal obtained from the integrating circuit 105, 307
Reference numerals 308 and 308 are D flip-flops, and 309 is an input terminal for a horizontal synchronizing signal.

The operation of the 0.5H skew detection circuit 112 and the 0.5H skew correction circuit 113 configured as described above will be described with reference to FIG. FIG. 4 shows a signal waveform in each part of the 0.5H skew detection circuit 112 and the 0.5H skew correction circuit 113 shown in FIG.

When a video signal, for example, a video signal during VTR playback, is input to the signal input terminal 301, the 0.5H signal delay unit 302 delays this signal by 0.5
Output after delaying for H period. The signal switching circuit 303 uses the detection signal obtained from the 0.5H skew detection circuit 112 to output a signal to be input to the input terminal 301 when there is no skew, and a 0.5H signal delay device which delays this signal for 0.5H period when there is skew. Selectively output the 302 output signal.

To the input terminal 305, a bit signal (a signal shown in FIG. 402 of FIG. 4) that changes in the same cycle as the horizontal synchronizing cycle among the output digital phase signals of the integrating circuit 105 is input, and the input terminal 306
Of the output digital phase signal of the integrator circuit 105 is a bit signal that changes at a half cycle of the horizontal synchronizing signal (fourth
The signal shown in FIG. 403) is input. The horizontal synchronizing signal (the signal shown in FIG. 4 401) is input to the input terminal 309. Input terminal 3
When the above signals are input to 05, 306 and 309, the output signal of the D flip-flop 307 and the output signal of the D flip-flop 308 become signals as shown in 404 and 405 of FIG. 4, respectively. The output signal of the D flip-flop 308 (the signal shown in FIG. 405 in FIG. 4) changes to a high level or a low bell when the horizontal synchronizing signal is deviated by a half period thereof 0.5H.
The skew detection signal, which is used for signal switching circuit 303
By controlling the signal, a skew-corrected signal of 0.5H can be obtained at the output terminal 304.

As described above, according to the present embodiment, the sync separation circuit, the reference angular frequency signal generator, the integration circuit that integrates the difference between the reference angular frequency signal and the error angular frequency signal to obtain the phase signal, and the integration circuit output. An error phase detection circuit that obtains an error phase signal by sampling the phase signal corresponding to the horizontal synchronization signal, and a phase that obtains an error angular frequency signal by giving a predetermined gain and, if necessary, low-pass characteristics to the error phase signal. An angular frequency converter,
A multiplier that multiplies the integration circuit output phase signal by a predetermined multiplier,
By configuring an AFC device in a VTR with an adder that adds another phase signal to the multiplier output phase signal and a phase / amplitude converter that converts the adder output phase signal to an amplitude signal, The device can be easily realized, and the operation of the AFC can be prevented from being disturbed by a 0.5H skew jump of the horizontal sync signal during VTR special playback. Furthermore, by using the signal generated in the AFC circuit section, it is possible to easily configure a 0.5H skew detection circuit that detects a 0.5H skew jump of the video signal during the VTR special reproduction, etc. 0.5H in addition to the original AFC operation for AFC equipment
It can also have a skew detection function.

(Effects of the Invention) The present invention can easily configure an automatic frequency control device by digital signal processing even if the horizontal synchronizing frequency is about twice that frequency as a clock.

Further, according to the present invention, since the signal level of the error phase signal is detected and the gain of the phase / angular frequency converter is switched according to the level, the horizontal level which occurs at the time of head switching, high speed reproduction, and reverse high speed reproduction. It is possible to configure an automatic frequency control device capable of responding to a sudden phase change of a sync signal and not responding to a disturbance received by a horizontal sync signal regardless of a color signal.

Furthermore, the present invention not only does not disturb the AFC operation even with respect to a skew jump of 0.5H of a signal that occurs during VTR special playback, but also has a function of simultaneously detecting and correcting this skew occurrence. An automatic frequency control device can be constructed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an AFC device according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of a multiplier in the embodiment of the present invention, and FIG. 3 is a skew detection circuit in the embodiment of the present invention. FIG. 4 is a signal waveform diagram for explaining FIG. 3, and FIG. 5 is a block diagram showing a configuration of a conventional AFC device. 101: video signal input terminal, 102: sync separation circuit, 10
3 ... Reference angular frequency signal generator, 104 ... Subtractor, 105 ...
… Integrator circuit, 106 …… Error phase detection circuit, 107 …… Phase ・
Angular frequency converter, 108 ... Multiplier, 109 ... Adder, 110
...... Phase / amplitude converter, 111 …… Amplitude signal output terminal, 1
12 …… 0.5H skew detection circuit, 113 …… 0.5H skew correction circuit.

Claims (9)

[Claims] 1. A sync separation means for separating a horizontal sync signal from an input video signal, a reference angular frequency signal generation means for generating a reference angular frequency signal, and a difference between the reference angular frequency signal and an error angular frequency signal. Integrating means for obtaining a phase signal by
Error phase detecting means for obtaining an error phase signal by detecting the value of the phase signal at the time corresponding to the horizontal synchronizing signal, and the error by applying a constant attenuation characteristic and low pass characteristic to the error phase signal. A phase / angular frequency converting means for converting into an angular frequency signal; an adding means for adding a predetermined number to the phase signal obtained by the integrating means; a means for correcting skew from the phase signal obtained by the integrating means; An automatic frequency control device comprising: a phase / amplitude converting means for converting a phase signal obtained by the adding means into an amplitude signal. 2. The automatic frequency control device according to claim 1, wherein the integrator comprises an adder and a delay circuit. 3. The error phase detecting means obtains the error phase signal by setting the cycle of the phase signal obtained by the integrating means to one half of the horizontal synchronizing cycle. The described automatic frequency control device. 4. The error phase detecting means sets the error phase signal corresponding to when the cycle of the phase signal obtained by the integrating means is half the horizontal synchronizing cycle and the cycle of the phase signal obtained by the integrating means. The automatic frequency control device according to claim (1), further comprising switch means for selectively switching and outputting a corresponding error phase signal when the horizontal synchronizing period is made equal. 5. A plurality of said phase / angular frequency conversion means are provided in accordance with the signal level detection means for detecting the signal level of the error phase signal obtained from the error phase detection means and the detection signal obtained from said signal level detection means. 10. An automatic frequency control device according to claim 1, further comprising: an attenuation characteristic switching means for selectively switching the attenuation characteristic of. 6. The phase / angular frequency conversion means, when the error phase signal level is large, an attenuation characteristic set to a value close to T / T _H (T is a sampling period, T _H is a hold period) and an error. When the phase signal level is low, the attenuation characteristic is set to a value much smaller than T / T _H , and means for selectively switching these is provided. The automatic frequency control device according to the paragraph. 7. The adder means comprises a multiplier for multiplying a predetermined multiplier and an adder for adding another phase signal to the output phase signal of the multiplier. The automatic frequency control device according to item (1). 8. The adding means comprises a multiplier that multiplies a constant number, and an adder that adds a 90-degree shift signal to the output phase signal of the multiplier. The automatic frequency control device according to the item (1). 9. A skew detecting means for detecting that the horizontal synchronizing signal has generated a skew corresponding to a half cycle period of the horizontal synchronizing cycle by using a phase signal obtained by the integrating means. The detection circuit, and a skew correction circuit that corrects a skew corresponding to the size of a half cycle period of the horizontal synchronization cycle by the detection signal. The described automatic frequency control device.