JPH0832172B2 - Power supply failure determination circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a failure determination circuit for a power supply device having a plurality of inverters.

Power supply devices that stabilize the output voltage by pulse width control are used in various fields, and when increasing the output capacity, it is common to use a parallel operation configuration of a plurality of inverters. In the power supply device having such a configuration, the failure of the inverter can be detected by detecting the oscillation stop of the inverter. However, at a light load, some of the plurality of inverters may be in the oscillation stopped state, so it is necessary to detect this state and the failure separately.

[Conventional technology]

FIG. 4 shows a fault detection circuit of a power supply device including a plurality of inverters of a conventional example, and shows a case where two inverters are operated in parallel. The DC voltage input from the input terminal IN is
It is applied to the primary winding of the transformers T1 and T2 via the transistors Q1 and Q2 which are on / off controlled by the drivers DV1 and DV2. The voltage of the secondary winding of the transformers T1 and T2 is rectified by the diodes D11, D12, D21 and D22 that form the main rectifier, smoothed by the smoothing circuit of the inductances L1 and L2 and the capacitors C11 and C21, and the output terminal It is supplied from OUT to a load (not shown).

The DC output voltage from the output terminal OUT is divided by the resistors R5 and R6 and compared with the reference voltage in the switching control unit 10 so that the output voltage becomes constant.
1, DV2 is controlled to control the on-time width of the transistors Q1, Q2.

The voltage of the secondary winding of the transformers T1 and T2 is rectified by the diodes D13, D14, D23 and D24 which form the sub rectifier, and smoothed by the capacitors C12 and C22 and the resistors R11 and R21, and the time constant is, for example, , The peak rectification is performed when the on-time widths of the transistors Q1 and Q2 are equal to or more than a certain value, and the average-value rectification can be considered when the on-time width is less than the certain value. The rectified output voltage from the sub rectifier is compared with the reference voltage in the comparators 11 and 12, and when it is lower than the reference voltage, the output signal becomes "1". That is, in the oscillating state in which the transistors Q1 and Q2 are repeatedly turned on and off, the induced voltage in the secondary windings of the transformers T1 and T2 becomes a certain value or more. In the continuous oscillation stopped state, the induced voltage drops or becomes zero,
The output signals of the comparators 11 and 12 are "1".

When the output signals of the comparators 11 and 12 both become "1", the output signal of the NAND circuit G becomes "0", and a current flows through the resistor R4 to the light emitting diode LD constituting the photocoupler to emit light. An alarm signal is output via the transistor PQ. That is, when two inverters fail at the same time,
An alarm signal is output. In this case, the NAND circuit G can be configured as an AND circuit.

Also, instead of the NAND circuit G, a NOR circuit is used, and comparators 11 and 1
An alarm signal may be output when either one of the two output signals becomes "1". In this case, an alarm signal will be output even if one of the inverters fails.

[Problems to be solved by the invention]

If the configuration is such that an alarm signal is output when the output signals of the comparators 11 and 12 are both "1", that is, if the configuration is such that an alarm signal is output only when both of the two inverters have failed, Even if the inverter fails, the alarm signal will not be output when the load current of 50% or less is supplied, and when the load current of 50% or more is supplied, the normal inverter will be overloaded. As a result, the alarm signal is output according to the drooping characteristic of the output voltage. In this case, there is a drawback that it is not possible to determine whether the load is abnormal or the power is abnormal.

In the case where the alarm signal is output when either or both of the output signals of the comparators 11 and 12 are "1",
Even if one of the inverters fails, an alarm signal will be output, but it is actually difficult to make the characteristics of the inverter exactly the same, and the internal impedance and switching of the transistors Q1 and Q2 as switching elements Due to the difference in speed and the like, there may be a state where the ON time width of one of the transistors Q1 and Q2 is zero, that is, an oscillation stopped state, under no load and under light load.

In such an oscillation stopped state, there is a drawback that an alarm signal is output even though the inverter is not in failure.

In order to improve such a defect, the inverter always oscillates even under no load and light load.
It is possible to provide a dummy load. However, there is a drawback that the efficiency is lowered due to the power consumed by the dummy load.

It is an object of the present invention to determine, during parallel operation of a plurality of inverters, whether it is in an oscillation stopped state due to a light load or the like, or in an oscillation stopped state due to a failure.

[Means for solving the problem]

The failure determination circuit of the power supply device according to the present invention can reliably detect a failure in any one inverter when a plurality of inverters are operated in parallel, and will be described with reference to FIG.

An oscillation pause detection unit 2 that detects the oscillation pauses of the plurality of inverters 1-1 to 1-n, and a control unit that temporarily forcibly stops the oscillation of the inverters other than the oscillation pause inverter detected by the oscillation pause detector 2. 3 and a failure detection section 4 that outputs an alarm signal when an oscillation-stop inverter other than the one whose oscillation is temporarily stopped by the control section 3 does not resume oscillation.

[Action]

If the oscillation suspension of the inverters 1-1 to 1-n occurs at a light load, the oscillation of the inverters other than the oscillation suspension inverter is forcibly stopped to start the oscillation of the oscillation suspension inverter to output the output voltage. Since it is necessary to keep the oscillation constant, the oscillation suspension state is released. Further, in the case of a failure, even if the oscillation of the inverters other than the oscillation-stop inverter is forcibly stopped, the oscillation-stop inverter does not operate, so it can be determined as a failure.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram of an embodiment of the present invention, showing a case where two inverters are operated in parallel. In the figure, T
1, T2 is a transformer, Q1, Q2 are transistors as switching elements, DV1, DV2 are drivers, D11, D12, D22, D23 are diodes as main rectifiers, D13, D14, D23, D24 are diodes as sub-rectifiers, L1, L2 and C11, C21 are inductances and capacitors that form a smoothing circuit, IN is a DC voltage input terminal, OUT is a DC voltage output terminal, C12, C22, R11, R
21 is a capacitor and a resistor that form a smoothing circuit, R1 to R3 are voltage dividing resistors for forming reference voltages Vr1 and Vr2, R4 is a resistor, L
D and PQ are light-emitting diodes and phototransistors forming a photocoupler, 10 is a switching control circuit, 11 to 14 are comparators, G1 and G2 are AND circuits, G3 and G4 are NAND circuits, and G5 and G6 are inverters (inversion circuits). , G7 is a NOR circuit.

The oscillation pause detector 2 is composed of the comparators 13 and 14, and the switching control circuit 10 and the gate circuits G1 to G of the AND circuit and the like.
The control unit 3 is composed of 6 or the like, and the comparators 11 and 12 and the NOR circuit G
7, the light emitting diode LD, the phototransistor PQ, and the like constitute the failure detection unit 4.

The operation of making the DC output voltage of the output terminal OUT constant by controlling the on-time width of the transistors Q1 and Q2 is the same as the operation in the configuration of the conventional example, and the duplicated description will be omitted. In this embodiment, the reference voltage Vr1 of the comparators 13 and 14 is
In contrast, the reference voltage Vr2 of the comparators 11 and 12 is set low, and the comparators 11 and 12 detect the failure due to the oscillation stop, and the comparator 1
3, 14 detects the oscillation stop state.

When the inverter is operating normally, the rectified output voltage V due to the diodes D13, D14, D23, D24 that compose the sub rectifier
1, V2 is higher than the reference voltage Vr1, Vr2, the comparator 11,12
The output signal of is 0, therefore the output signal of the NOR circuit G7 is 1 and no current flows through the light emitting diode LD, so that no alarm signal is output. Further, since the output signals of the comparators 13 and 14 are "1" and the output signals of the NAND circuits G3 and G4 are "1", the control signal from the switching control circuit 10 is the driver through the AND circuits G1 and G2. In addition to DV1 and DV2, on / off control of the transistors Q1 and Q2 is performed.

At no load or at light load, either one of the inverters may be in the oscillation stop state. For example, when the transistor Q2 as the switching element of the other inverter is in the oscillation continuation state in which it is on / off controlled, and the on / off control of the transistor Q1 as the switching element of the one inverter is stopped to enter the oscillation suspension state, The induced voltage in the secondary winding of the transformer T1 decreases, and the charge in the capacitor C12 is discharged through the resistor R11, and the voltage
V1 decreases.

When this voltage V1 drops below the reference voltage Vr1, the comparator 13
, The output signal of the NAND circuit G4 becomes "0", and the AND circuit G2 is closed. Therefore, the control signal from the switching control circuit 10 is not added to the driver DV2. That is, the oscillation stop state of one inverter forces the other inverter to stop oscillating.

When one of the inverters is not in failure, the output voltage drops due to the oscillation stop of the other inverter, so the control signal from the switching control circuit 10 is applied to the driver DV1 via the AND circuit G1 to turn on / off the transistor Q1. The control is started, the induced voltage of the secondary winding of the transformer T1 rises accordingly, the rectified output voltage V1 by the sub rectifier rises, becomes the reference voltage Vr1 or more, and the output signal of the comparator 13 becomes “1”. Therefore, the output signal of the NAND circuit G4 becomes "1". Therefore, the control signal from the switching control circuit 10 is applied to the driver DV2 via the AND circuit G2, and the operation of the other inverter whose oscillation is forcibly stopped is restarted.

At this time, if one of the inverters fails, even if the other inverter is forcibly stopped oscillating, the oscillation of one inverter does not start, so the terminal voltage V1 of the capacitor C12 further decreases, and the reference voltage Vr2 or less. When it comes to comparator 1
The output signal of 1 becomes "1", a current flows through the light emitting diode LD to emit light, and an alarm signal is output.
That is, the failure of the inverter can be detected by distinguishing between the oscillation stop state under no load or light load and the oscillation stop state due to the failure.

FIG. 3 is a block diagram of a main part of another embodiment of the present invention, showing a case of a power supply device in which three inverters 21-1 to 21-3 are operated in parallel, 22 to 27 are comparators, and 28 is a comparator. Switching control circuits, G21 to G26 are AND circuits, G27 to G32 are NAND circuits, and G33 to G38 are inverters (inversion circuits).

The comparators 22 to 27 are connected to the reference voltage Vr1 and each inverter 21-1.
21-21 are used to compare the rectified output voltage (corresponding to V1 in FIG. 2) by the sub rectifier of the inverter 21-
When 1 to 21-3 are normal, the output signals of the comparators 22 to 27 are "1" and the output signals of the NAND circuits G27 to G32 are "1". Therefore, the output signals of the AND circuits G24 to G26 become "1", and the control signal from the switching control circuit 28 is applied to the inverters 21-1 to 21-3 via the AND circuits G21 to G23 to obtain the DC output voltage. Stabilization control is performed.

For example, if the rectified output voltage of the sub rectifier of the inverter 21-3 is lower than the reference voltage Vr1, the comparators 25, 26
The output signal of the NAND circuit becomes "0", which causes the NAND circuit G3
The output signal of 0 and G31 becomes "0". Therefore, AND circuit G26
Since the output signal of the AND circuit is "0" and the output signals of the AND circuits G24 and G25 are "1", the AND circuits G21 and G22 are closed and only the AND circuit G23 is opened.
Is forced to stop oscillating.

In this case, the inverter 21
-3 becomes the oscillation stop state, the other inverter 21-
Since the oscillation of 1,21-2 is forcibly stopped, the oscillation of the inverter 21-3 is started due to the decrease of the DC output voltage, which increases the rectified output voltage of the sub rectifier and returns to the original state. It will be.

However, if the inverter 21-3 fails, even if the oscillation of the other inverters 21-1 to 21-2 is forcibly stopped,
Since the oscillation of the inverter 21-3 is not restarted, the failure detection unit operates and outputs the alarm signal. Therefore, it is possible to separately detect the oscillation suspension state and the oscillation suspension state due to a failure.

The present invention is not limited to the above-described embodiments, and for example, the control unit may have another logic circuit configuration, and the judgment and control functions of a microprocessor or the like may be used. Is.

〔The invention's effect〕

As described above, the failure determination circuit of the power supply device according to the present invention includes the oscillation pause detection section 2, the control section 3, and the failure detection section 4.
By forcibly stopping the oscillation of the inverters other than the oscillation pause inverter, it is determined whether or not the oscillation pause inverter is restarting the oscillation and whether or not there is a failure. Multiple inverters 1-
It is possible to distinguish the 1 to 1-n no-load or light-load oscillation suspension state and the oscillation stop state due to a failure. Therefore, there is an advantage that the failure of the inverter can be surely detected.

Further, since it is not necessary to connect a dummy load to each of the plurality of inverters 1-1 to 1-n, the efficiency of the power supply is not reduced, and there is some variation in characteristics among the plurality of inverters 1-1 to 1-n. However, there is an advantage that it is possible to discriminate between the oscillation stop state under no load or light load and the oscillation stop state due to a failure.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIG. 3 is a block diagram of essential parts of another embodiment of the present invention, and FIG. 4 is a circuit of a conventional example. It is a figure. 1-1 to 1-n are inverters, 2 is an oscillation pause detector, 3
Is a control unit, and 4 is a failure detection unit.

Claims (1)

[Claims] 1. A failure determination circuit for a power supply device, wherein a plurality of inverters (1-1 to 1-n) are operated in parallel, and a constant voltage is applied to a load by pulse width control. 1 to 1-n), an oscillation stoppage detection unit (2) for detecting the oscillation stoppage, and a control unit for temporarily forcibly stopping the oscillation of inverters other than the oscillation stoppage inverter detected by the oscillation stoppage unit (2) ( 3) and a failure detection unit (4) that outputs an alarm signal when the oscillation halt inverter other than the inverter whose oscillation is temporarily forcibly stopped by the control unit (3) does not resume oscillation. Characteristic power supply device failure determination circuit.