JPH08330174A - Chip type electronic component and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Purpose] An object is to provide a chip-type electronic component in which the Manhattan phenomenon does not occur. [Structure] The exposed end surfaces of the internal electrode 42 of the element body 43, the side surfaces continuing from these end surfaces, and a part of the upper and lower surfaces, a total of 5 surfaces,
g was applied and baked to form an Ag electrode 44. Next, Ni plating and Sn plating were performed in this order on the Ag electrode 44 to form an intermediate layer 45 and an outermost layer 46. Then, it was placed in a heat-resistant container of a dryer and heat-treated. By performing this heat treatment, Ni of the intermediate layer 45 is diffused into a portion where the Sn plating thickness is thin, and S which is inferior in solderability to Sn is Sn.
An n-Ni intermetallic compound 47 can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type electronic component having terminal electrodes on both end faces of an element and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, electronic parts having one terminal external electrode having five faces, represented by a multilayer ceramic capacitor (hereinafter referred to as a chip capacitor), have become lighter, thinner and smaller.
As its dimensions, length L 1.0 mm, width W and height T 0.5
The 1005 mm type has been produced and sold, and is compatible with high-density mounting. The terminal external electrode (hereinafter referred to as an external electrode) has a structure and a manufacturing method of an electronic component having end surfaces, side surfaces, and upper and lower 15 surfaces. FIG. 16 is a perspective view of a conventional chip capacitor. In FIG. 16, 1 is the upper surface of the ceramic body and 2 is the side surface of the ceramic body, and there is almost no apparent distinction between 1 and 2. 3 is a top surface of the external electrode, 4 is a side surface of the external electrode, and there is almost no apparent distinction between 3 and 4. Reference numeral 5 is an external electrode end surface. FIG. 17 is a sectional view of a conventional chip capacitor. Reference numeral 6 is an internal electrode, 7 is a terminal plating base electrode (hereinafter referred to as a plating base electrode), and 8 is an intermediate electrode made of Ni or Cu. The intermediate electrode 8 may have two layers. Reference numeral 9 is an outermost layer electrode formed of Sn or Sn alloy. The chip capacitor is manufactured by the process shown in the flowchart of FIG.
First, the plating base electrode 7 is formed on the ceramic body by coating and baking (21) and (22), and the intermediate electrode 8 and the outermost layer electrode 9 are formed by electrolytic barrel plating or electroless plating (23) and (24). ), The characteristics and appearance are selected and packaged (25), (26), (27) and shipped (therefore,
There is almost no distinction between the upper surface 1 and the side surface 2 of the ceramic body and the upper surface 3 and the side surface 4 of the external electrode).

A reflow soldering method will be briefly described among the mounting methods for the chip capacitor configured as described above. FIG. 19 is a model diagram of a mounting substrate. Cream solder 12 is applied to lands 11 of a substrate 10 formed of alumina or resin and chip capacitors 14 are arranged to melt the cream solder 12 by heat from the outside, and the solder is as shown in FIG. It was mounted by the reflow soldering method, in which the solder is soldered by getting wet on the top.

[0004]

According to this structure, when mounting the chip capacitor on the substrate 10, all the steps shown in FIG.
As shown in FIG. 2, the substantially symmetrical fillets 13 are formed at both ends of the chip capacitor 14 and are not soldered, and various conditions at the time of mounting (heat on the lower surface depends on the heat capacity of the substrate 10 or the substrate 10 or other components). (Effect of radiant heat, etc.)
As shown in FIG. 21, there is a problem that a Manhattan phenomenon occurs in which the chip capacitor 14 rises to one side due to a tradeoff between the chip capacitor 14 and the dimensions of the chip capacitor 14.

This phenomenon is caused by a difference in the left and right balance of the tension of the solder with respect to the chip capacitor 12 when the solder gets wet from the end face to the upper face, and the gravity of the chip capacitor 12 is exceeded.

Therefore, an object of the present invention is to provide a chip-type electronic component that suppresses the wetting of solder from the end face to the upper part and does not cause the Manhattan phenomenon.

[0007]

In order to achieve this object, a chip-type electronic component of the present invention comprises an element and an electrode composed of at least three layers provided on at least an end face of the element. A part of the outer layer and a part of the intermediate layer which is in contact with the outermost layer are made of a metal having a solderability lower than that of the metal forming the outermost layer, and the rest of the outermost layer is Sn or Sn. It is composed of an alloy with a metal not used in the intermediate layer, and the balance of the intermediate layer forms an alloy with the metal of the outermost layer, and this alloy is inferior in solderability to the metal of the outermost layer. It is a metal.

[0008]

According to this structure, the electrode surface has a part that is poorly wetted by the solder and a part that is well-wetted by the solder. Therefore, when mounting the chip type electronic component on the substrate, the difference between the left and right forces due to the wetted solder is reduced. As a result, the Manhattan phenomenon can be prevented from occurring.

[0009]

【Example】

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with a chip capacitor as an example with reference to the drawings.

FIG. 1 is a perspective view of a chip capacitor according to this embodiment, FIG. 2 is a sectional view thereof, and FIG. 3 is a manufacturing process drawing of the chip capacitor according to this embodiment.

First, an element body 43 in which dielectric layers 41 and internal electrodes 42 are alternately laminated is prepared (21), and this element body 43 is formed.
The Ag is applied (22) to the exposed both end surfaces of the internal electrode 42, the side surfaces following the both end surfaces, and a part of the upper and lower surfaces, a total of five surfaces (22),
After baking (23), an Ag electrode 44 was formed. Next, on this Ag electrode 44, Ni plating (24) and Sn plating (2
5) was performed in this order to form the intermediate layer 45 and the outermost layer 46. At this time, the Sn plating (25) does not use a chemical (brightening agent) for uniform plating in order to partially form an alloy portion of Ni and Sn on the surface of the external electrode, so that the uniformity is poor. It was performed using a plating solution based on methanesulfonic acid. Then, characteristics and appearance selection (26), (2
After 7), put it in a heat-resistant container of the dryer and heat-treat (2
8) was performed.

By performing this heat treatment (28), S
Ni of the intermediate layer 45 is diffused to the thin portion of the n-plating, and the Sn-Ni intermetallic compound 47, which is inferior to Sn in solderability, can be formed.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. 4 is a perspective view of the chip capacitor in this embodiment, FIG. 5 is a sectional view thereof,
FIG. 6 is a manufacturing process diagram of this chip capacitor.

An element body 43 was prepared in the same manner as in Example 1 (21), and Ag was applied (22) to both end surfaces and side surfaces following these end surfaces and a part of the upper and lower surfaces, a total of 5 surfaces. Baking (23)
Thus forming the Ag electrode 44. Next, Ni plating (24) and Sn plating (25) were performed in this order on the Ag electrode 44 to form an intermediate layer 45 and an outermost layer 46. At this time S
The n-plating (25) is one of the heights of the chip capacitor with respect to the surface in contact with the substrate on which the chip capacitor is mounted.
In order to partially form an alloy portion of Ni and Sn in a portion higher than / 3, a brightener was added to a liquid based on alkanol sulfonic acid so that plating with good uniformity could be obtained.

Next, characteristics and appearance selection (26),
After (27), it is placed on the alignment jig 48 of the packaging machine as shown in FIG. 7 and heat-treated (29) from the upper surface of the chip capacitor with the iron 49, so that the intermediate layer of the heated portion. Ni of 45 diffused to the Sn side of the outermost layer 46 to form an Sn-Ni intermetallic compound 47 having a solderability lower than that of Sn.

When this chip capacitor is mounted on a substrate, the solder wettability of the upper part is deteriorated, so that the tension at the time of forming the fillet is minimized, and the reliability due to the peeling of the external electrode and the fillet due to the temperature cycle after the mounting. Can maintain sex.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings. FIG. 8 is a perspective view of the chip capacitor in this embodiment, FIG. 9 is a sectional view thereof,
FIG. 10 is a manufacturing process diagram of this chip capacitor.

An element body 43 was prepared in the same manner as in Example 2 (21), and Ag was applied (22) to a total of 5 surfaces on both end surfaces and side surfaces continuing from the end surfaces and upper and lower surfaces. Baking (23)
Thus forming the Ag electrode 44. Next, Ni plating (24) and Sn plating (25) were performed in this order on the Ag electrode 44 to form an intermediate layer 45 and an outermost layer 46. At this time S
The n-plating (25) is one of the heights of the chip capacitor with respect to the surface in contact with the substrate on which the chip capacitor is mounted.
In order to partially form an alloy portion of Ni and Sn in a portion higher than / 3, a brightener was added to a liquid based on alkanol sulfonic acid so that plating with good uniformity could be obtained.

Then, characteristics and appearance selection (26),
After (27), as shown in FIG. 11, a chip capacitor 53, which is marked with UV curing resin 50 on the upper surface, is arranged on the alignment jig 51 of the marking machine, and heat is applied from the upper surface of the chip capacitor 53 with the heat source 52 including the UV light source. did. By partially applying heat, the N of the intermediate layer 45 of the heated part is
i diffused to the Sn side of the outermost layer 46 to form an Sn-Ni intermetallic compound 47 having a solderability lower than that of Sn, and marking for distinguishing the upper and lower surfaces of the chip capacitor 53 was performed. .

By carrying out this marking, it is easy to set the surface having poor solder wettability on the top during mounting, and the mounting is successful.

The UV curing resin used here is 165
A material that cures at ℃ must be used.

(Embodiment 4) A fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 12 is a perspective view of the chip capacitor in this embodiment, FIG. 13 is a sectional view thereof, and FIG. 14 is a manufacturing process diagram of this chip capacitor.

An element body 43 was produced in the same manner as in Example 2 (21), and Ag was applied (22) to both end faces and side faces following these end faces and a part of the upper and lower faces, a total of 5 faces (22), and baked. (23)
Thus forming the Ag electrode 44. Next, Ni plating (24) and Sn plating (25) were performed in this order on the Ag electrode 44 to form an intermediate layer 45 and an outermost layer 46. At this time S
In the n-plating (25), in order to partially form an alloy portion of Ni and Sn, a brightening agent was added to a liquid based on alkanol sulfonic acid so that the plating had good uniformity.

Next, characteristics and appearance selection (26),
After (27), it is placed on the aligning jig 48 of the packaging machine as shown in FIG. 15, and heat treatment (29) is performed from both end surfaces of the chip capacitor with the iron 54, so that the middle of the heated portion is reached. Ni of the layer 45 was diffused to the Sn side of the outermost layer 46 to form an Sn-Ni intermetallic compound 47 having a solderability lower than that of Sn.

Since this chip capacitor has a surface with poor solder wettability on the end face, it is possible to generate not a lateral force but a lateral rotation force about the central axis of the chip capacitor.

(Embodiment 5) Similar to Embodiment 4, both end faces of the chip capacitor which has been subjected to the heat treatment step (29) and before are polished with sandpaper so that the thickness of the Sn plating of the outermost layer 46 is reduced to 0.5 μm. After scraping off, heat treatment (29) was performed in the same manner as in Example 4.

(Embodiment 6) As in Embodiment 4, the both end surfaces of the chip capacitor, which has been subjected to the heat treatment step (29) and before, are treated with a non-boiling liquid composed of an oxidizing expansion agent and sodium hydroxide at 80 ° C. After immersion for 10 seconds, the thickness of the Sn plating adjusted to 0.5 μm was heat treated (29) in the same manner as in Example 4.

For comparison, as a comparative example 7, a normal plating is used, and as a comparative example 8, an intermediate layer 45 having a Ni plating thickness of 0.5 μm and an outermost layer having a Sn plating thickness of 0.5 μm is used. In the same manner as in Example 4, heat treatment (2
9) The prepared one was prepared.

In the heat treatment (29) of the chip capacitors of Examples 1 to 8, the surface temperature of the heated portion was 16
The temperature was controlled to 5 ° C.

Table 1 shows the mounting tests (solderability, Manhattan defect occurrence rate) of the chip capacitors of Examples 1 to 6 and Comparative Examples 7 and 8.

[0031]

[Table 1]

The test conditions are shown below. Product 1005 type (length 1.0 mm * width 0.5 mm *
Height 0.5 mm) Reflow soldering No residual heat TOP temperature 240 ° C. 230 ° C. or higher for 5 seconds (Table 1) As is apparent from Table 1, the chip capacitors of Examples 1 to 6 have excellent mountability.

As described above, according to the embodiment, at least a part of the surface of the external electrode, which is higher than 1/3 of the height of the chip capacitor, is heat-treated on the basis of the surface in contact with the substrate on which the chip capacitor is mounted. By forming the Ni—Sn intermetallic compound 47 on the substrate, the Manhattan defect can be prevented.

In the examples, the intermediate layer 45 and the outermost layer 46 were each formed to have a thickness of 1 μm or more.

In the embodiment, the intermediate layer 45 is made of Ni.
However, the metal used for the intermediate layer 45 may be a metal (for example, Cu) that forms a compound by heat treatment with Sn and has a soldering property inferior to that of Sn (for example, Cu).

Further, the heat treatment is preferably applied all at once because the heat treatment is applied only to the portion where the intermetallic compound 47 is desired to be formed. At that temperature, the effect can be obtained as long as Sn of the outermost layer 46 is oxidized. By setting the temperature to 165 ° C. or higher, the Ni of the intermediate layer 45 becomes the outermost layer 4 in a short time.
It is possible to diffuse to the Sn side of 6 to form an alloy.

Although the chip capacitor is shown as an example in the embodiment, the same effect can be obtained in other chip type ceramic electronic components having electrodes on the end faces and chip resistors having electrodes on only three faces.

[0038]

As described above, according to the present invention, the electrode surface has a portion which is poorly wetted by the solder and a portion which is not wetted by the solder.
When mounting the chip-type electronic component on the substrate, it is possible to reduce the difference between the left and right forces due to the wetting of the solder, and as a result, it is possible to prevent the Manhattan phenomenon from occurring.

[Brief description of drawings]

FIG. 1 is a perspective view of a chip capacitor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a chip capacitor according to a first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the chip capacitor according to the first embodiment of the present invention.

FIG. 4 is a perspective view of a chip capacitor according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a chip capacitor according to a second embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of a chip capacitor according to a second embodiment of the present invention.

FIG. 7 is a perspective view illustrating a heat treatment process in the second embodiment of the present invention.

FIG. 8 is a perspective view of a chip capacitor according to a third embodiment of the present invention.

FIG. 9 is a sectional view of a chip capacitor according to a third embodiment of the present invention.

FIG. 10 is a manufacturing process diagram of a chip capacitor according to a third embodiment of the invention.

FIG. 11 is a perspective view illustrating a heat treatment process in the third embodiment of the present invention.

FIG. 12 is a perspective view of a chip capacitor according to a fourth embodiment of the present invention.

FIG. 13 is a sectional view of a chip capacitor according to a fourth embodiment of the present invention.

FIG. 14 is a manufacturing process diagram of a chip capacitor according to a fifth embodiment of the present invention.

FIG. 15 is a perspective view illustrating a heat treatment process in a fifth embodiment of the present invention.

FIG. 16 is a perspective view of a conventional chip capacitor.

FIG. 17 is a sectional view of a conventional chip capacitor.

FIG. 18 is a manufacturing process diagram of a conventional chip capacitor.

FIG. 19 is a perspective view of a mounting board.

FIG. 20 is a side view of the chip capacitor after soldering.

FIG. 21 is a side view of a chip capacitor that has failed Manhattan.

[Explanation of symbols]

 43 Element body 44 Ag electrode 45 Intermediate layer 46 Outermost layer 47 Intermetallic compound 50 Marking

Claims (9)

[Claims] 1. An element, and an electrode composed of at least three layers provided on at least an end face of the element, wherein a part of an outermost layer of the electrode and a part of an intermediate layer in contact with a part of the outermost layer are formed as described above. The intermediate layer is composed of a metal having a solderability lower than that of the metal forming the outermost layer, and the balance of the outermost layer is Sn or an alloy of Sn and a metal not used in the intermediate layer. The remaining part of the above forms an alloy with the metal of the outermost layer, and the alloy is a metal whose solderability is inferior to the metal of the outermost layer. 2. The chip-type electronic component according to claim 1, wherein the intermediate layer is made of Ni or Cu. 3. A metal having a solderability lower than that of a metal forming an outermost layer provided in a part of an outermost layer and an intermediate layer in contact with the outermost layer is based on a surface in contact with a substrate on which a chip-type electronic component is mounted. The chip-type electronic component according to claim 1, wherein the chip-type electronic component is present in a portion higher than 1/3 of the height of the chip-type electronic component. 4. The chip-type electronic component according to claim 1, wherein a marking is provided on the upper surface of the element. 5. The intermediate layer and the outermost layer each have a thickness of 1 μm.
The thickness of the outermost layer and a part of the intermediate layer in contact with the outermost layer and the alloy portion of the metal of the outermost layer are the sum of the thickness of the intermediate layer and the outermost layer. Alternatively, the chip-type electronic component described in 3 above. 6. The intermediate layer and the outermost layer each have a thickness of 1 μm.
The thickness of the alloy portion of the metal of the outermost layer and the outermost layer provided in a part of the intermediate layer in contact with the outermost layer is thicker than the thickness of the intermediate layer by less than 1 mm. The chip-type electronic component described in. 7. A plating base electrode is formed on at least an end surface of the device, and then Ni or Cu is formed on the plating base electrode.
And forming Sn on the intermediate layer.
Alternatively, a chip type in which an outermost layer made of an alloy of Sn and an unused metal in the intermediate layer is formed to form a terminal plating electrode, and then at least a part of the terminal plating electrode is heat-treated at a temperature of 165 ° C. or higher. Electronic component manufacturing method. 8. After removing at least a portion of the outermost layer,
The method for manufacturing a chip-type electronic component according to claim 7, wherein the removed portion is heat-treated. 9. The method for manufacturing a chip-type electronic component according to claim 8, wherein at least a part of the outermost layer is removed by physical polishing or immersion in an acid or alkali solution.