JPH0833379B2 - Ultrasonic flaw detector - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital ultrasonic flaw detector for performing flaw detection inside an object.

[Conventional technology]

The ultrasonic flaw detector is well known as an apparatus for inspecting the presence or the size of a flaw inside an object without destroying the object. Conventionally, as such an ultrasonic flaw detector, an analog type has been used in which an ultrasonic reflected wave reflected from an object is displayed on an oscilloscope. On the other hand, the applicant of the present application has proposed, in Japanese Patent Application No. 61-240191, a digital-type ultrasonic flaw detector capable of processing an ultrasonic reflected wave so as to be more convenient for flaw detection.
The outline of this digital ultrasonic flaw detector will be described with reference to the drawings.

FIG. 4 is a block diagram of a digital ultrasonic flaw detector. In the figure, reference numeral 1 denotes an object to be inspected, and 1f denotes a defect existing in the object to be inspected 1. Reference numeral 2 denotes an ultrasonic probe that radiates ultrasonic waves into the inspection object 1 and outputs an electric signal proportional to the reflected ultrasonic waves. Reference numeral 4 is a timing circuit for generating a pulse that gives time regulation to the operation of the ultrasonic flaw detector, and 5 is an ultrasonic probe 2 according to a signal from the timing circuit 4.
It is a transmitter that outputs a pulse for ultrasonic wave generation.
Reference numeral 6 denotes a receiving unit that receives a signal from the ultrasonic probe 2 and is composed of an attenuation circuit 6a and an amplification circuit 6b.

7 is an A / which converts the output signal of the receiving unit 6 into a digital value.
A D conversion unit, 8 is a waveform memory that stores the values converted by the A / D conversion unit 7, and 9 is an address counter that sequentially specifies each address of the waveform memory 8. The A / D converter 7 and the address counter 9 are each given a start signal from the timing circuit 4. A crystal oscillator is used for oscillation of the timing circuit 4.

10 is a CPU (central processing unit) that performs the required calculation and control, 1
1 is R for temporarily storing parameters and data for calculation
AM (random access memory), 12 is a ROM (read only memory) that stores the processing procedure of the CPU 10. 13 is a measuring range setting unit for inputting a desired measuring range, 14
Is a sound velocity input unit for inputting a velocity (sound velocity) at which an ultrasonic wave propagates in the inspected object 1. Reference numeral 15 is a display unit, and 16 is a display unit controller that controls the display of the display unit 15 based on the data obtained as a result of the calculation and control of the CPU 10.

Next, the outline of the operation of the ultrasonic flaw detector will be described with reference to the waveform diagram of the reflected wave signal shown in FIG. 5 and the block diagram of the waveform memory 8 shown in FIG. First, a desired measurement range l _R (this value is shown in the inspected object 1 shown in FIG. 4) is set in the measurement range setting unit 13. The sound velocity v _S determined by the material of the object 1 to be inspected is also input to the sound velocity input unit 14. In this state, the timing circuit 4 to the transmitter 5
When a trigger signal is output to the ultrasonic probe 2, the transmitting unit 5 outputs a pulse to the ultrasonic probe 2, and the ultrasonic probe 2 outputs the pulse to the object 1 to be inspected.
Ultrasonic waves are emitted inside. The reflected wave of this ultrasonic wave is converted into an electric signal by the ultrasonic probe 2, and this signal is received by the receiving unit 6. The receiving unit 6 outputs the received reflected wave signal as a value suitable for the subsequent processing. The output reflected wave signal is output from the A / D converter 7 at a predetermined sampling cycle.
At, the digital value is converted into a digital value, and the converted value is sequentially stored in the waveform memory 8. This storage is performed by the address counter 9 sequentially designating the addresses of the waveform memory 8. The sampling of the reflected wave signal and the address designation of the waveform memory 8 are executed by the start signal output from the timing circuit 4. Sampling of such a reflected wave signal and accommodation of the digital value in the waveform memory 8 will be described with reference to FIGS. 5 and 6.

FIG. 5 is a waveform diagram of the reflected wave signal. In the figure, the horizontal axis represents time, and the vertical axis represents the magnitude (voltage) of the reflected wave signal. T represents a reflected wave signal from the surface of the inspected object 1, and F represents a reflected wave signal from the defect 1f. Incidentally, in FIG. 5, only the horizontal axis is drawn in an extremely enlarged manner. Next, FIG. 6 is a block diagram of the waveform memory 8. Each block shown in a row means a data storage section in the waveform memory 8 and is described in each storage section D ₍₀₎ , D ₍₁₎ , ... D ₍ i _-1) , D ₍ i ₎ , D ₍
i _{+ 1)} ... is the data of the reflected wave signal converted into a digital value by the A / D converter 7. As a general form of these data
Denote by D ₍ i ₎ . In addition, the code A on the left side of each accommodation unit
_{M (0)} , A _{M (1)} , ... A _{M (} i _-1) , A _{M (} i ₎ A _{M (} i _+1), ... _Represent the address of the corresponding accommodation unit. These addresses are represented in the general form by A _{M (} i ₎ .

Now, at time t ₀ shown in FIG. 5, the timing circuit 4
When the activation signal is output from the A / D converter 7 to the address counter 9, the A / D converter 7 A / D converts the voltage of the reflected wave signal T at that time to obtain data D ₍₀₎ . . Further, the address counter 9 designates the address A _{M (0)} of the waveform memory 8. As a result, data D ₍₀₎ is the address of waveform memory 8.
It is housed in A _{M (0)} . Next, time t ₁ after the time τ _{S has} elapsed
At the same time, when the timing circuit 4 outputs the activation signal to the A / D converter 7 and the address counter 9 again, the voltage of the reflected wave signal T at that time is also converted by the A / D converter 7 and the data D _{( 1)} is obtained and the address counter 9 designates the next address A _{M (1)} , so that the data D ₍₁₎ is stored in the address A _{M (1)} of the waveform memory 8. In this case, the time τ
_S is the sampling time (for example, 50 ns). Thereafter, similarly, the data of the reflected wave signal is stored in the waveform memory 8. The sampling time τ _S is shown extremely large in comparison with the reflected wave signal.

In this way, the necessary data of the reflected wave signal data Di stored in the waveform memory 8 is extracted and displayed on the display unit 15
Is displayed in. For example, when displaying a waveform within a distance l _R from the surface of the inspected object 1 as shown in FIG. 4, the distance l _R is set in the measurement range setting unit 13, and the distance l _R and the sound velocity input unit are set. Data in the range of the distance l _R is selectively fetched from the waveform memory 8 and displayed on the display unit 15 at numerical intervals calculated based on V _S input to 14. The operation for displaying these is controlled by the CPU 10.

The above-mentioned digital ultrasonic flaw detector has various types of display such as the whole display of the reflected wave of the object to be inspected 1, the display of the reflected wave in an arbitrary range, the enlarged display of an arbitrary portion of the reflected wave, the transition display of the reflected wave in the time axis direction. The function can be executed, and it is extremely effective for flaw detection of the object to be inspected.

[Problems to be solved by the invention]

In the above ultrasonic flaw detector, it is natural that high flaw detection accuracy, that is, high precision flaw detection at the defect position (the distance from the surface of the object to be inspected to the defect) is required. For that purpose, it is necessary to reduce the sampling time τ _S , and for this purpose, a high-speed A / D conversion circuit is used as the A / D converter 7, for example, an A / D conversion circuit using an ECL (Emitter Coupled Logic) circuit. Should be used. However, such a high-speed A /
When the D conversion circuit is used, it is necessary to use, for example, the ECL circuit described above for all the elements related to the high speed conversion operation. This will be described with reference to FIG.

FIG. 7 is a circuit diagram when an ECL circuit is used for the A / D conversion circuit. In the figure, the same parts as those in FIG. 4 are designated by the same reference numerals. The A / D converter 7 in FIG. 4 is composed of an A / D conversion circuit 7a and a latch circuit 7b that holds the output of the A / D conversion circuit 7a for a certain period. It is composed of a multiplexer 8b for switching. Reference numerals 16 and 17 denote translators that convert the voltage level between the ECL circuit and the TTL circuit.

If the ECL circuit is used for the A / D conversion circuit 7a in the above circuit, the timing circuit 4 and the address counter 9 must also use the ECL circuit, and the latch circuit 7
It is obvious that the b, the memory 8a and the multiplexer 8b also need to use the ECL circuit.

By the way, the ECL circuit consumes more power than a normal TTL circuit, and accordingly generates a large amount of heat and is expensive. On the other hand, since the memory composed of the ECL circuit has a small capacity, it is necessary to use a large number of memories in order to obtain the memory having the same capacity as the memory using the normal TTL circuit.
Therefore, when the ECL circuit is used for the memory 8a as shown in FIG. 7, the number of the memories 8a becomes large, so that the power consumption and the heat generation amount become extremely large, and a large power source and a cooling device are required, As a result, the problem of increasing the cost of the ultrasonic flaw detector arises in combination with the use of many expensive memories.

The object of the present invention is to solve the above-mentioned problems and to achieve high-speed A / D.
It is to provide an ultrasonic flaw detector that can use a slow memory to perform the conversion.

[Means for solving problems]

In order to achieve the above object, the present invention is an ultrasonic flaw detector that receives an ultrasonic reflected wave from a flaw-detected object and performs flaw detection on the flaw-detected object by analyzing the received signal. High-speed A / D that converts signals to digital values
A converter, a shift register that sequentially shifts a predetermined frequency signal, a plurality of latch circuits that sequentially hold the output data of the high-speed A / D converter by each signal that is shifted by the shift register, and a latch circuit that is held by these latch circuits. A plurality of low-speed memories for storing output data are provided.

[Action]

Ultrasonic reflected waves from the object to be inspected are transmitted through the amplification circuit and at high speed.
It is input to the A / D converter and converted to digital values sequentially in a short sampling period. On the other hand, each latch circuit is input with a latch signal of a predetermined cycle shifted by the sampling period, and can hold the input data. Therefore, when the digital value data output from the high speed A / D converter is simultaneously input to the plurality of latch circuits, the data is sequentially latched by each latch circuit. The data thus latched is stored in the low speed memory corresponding to each latch circuit.

[Examples] Hereinafter, the present invention will be described based on illustrated examples.

FIG. 1 is a block diagram of a part of an ultrasonic flaw detector according to an embodiment of the present invention. In the figure, the same parts as those shown in FIG. A timing circuit 4 outputs a high-speed signal (high-frequency signal) and a low-speed signal (lower-frequency signal than the high-speed signal). The timing circuit 4 is configured by using, for example, an ECL circuit, and the high speed signal is output to an A / D conversion circuit 7a described later and the like.
In addition, the low-speed signal divides the high-speed signal, and divides this divided signal from the signal level of the ECL circuit to the low-speed operation circuit (for example, T
It is obtained by converting the signal level of the TL circuit) and is output to the address counter 9 and the like. 7a is a high-speed A / D conversion circuit, and 7b is a latch circuit that latches the output data of the A / D conversion circuit 7a. Reference numeral 20 is a frequency dividing circuit for dividing the output pulse of the timing circuit 4, and 21 is a shift register for sequentially shifting and outputting the output pulse output from the frequency dividing circuit 20. Timing circuit 4, A / D conversion circuit 7a, latch circuit 7
b, the frequency dividing circuit 20 and the shift register 21 are configured by using a circuit capable of high speed operation, for example, the ECL circuit. Reference numerals 22 and 23 denote the output signal level of the high-speed operation of the shift register 21 and the latch circuit 7b (the operation level of the ECL circuit) which is suitable for the low-speed operation (for example, a normal TT).
It is a translator that converts to L circuit operation level).

L ₁ ~L ₆ is a latch circuit, a shift register, respectively
Each signal shifted by 21 is individually input as a latch signal, and the data converted by the A / D conversion circuit 7a is simultaneously input. L ₁₀ ~L ₅₀ each respectively latch L ₁
A latch circuit which latches the latched data to ~L _5, the same latch signal and latch signal inputted to the latch circuit L ₆ is input. M ₁ ~M ₆ is latch L ₁₀ ~L _50, L ₆
It is a memory for storing the data latched in, and operates in synchronization with the output signal (low speed signal) of the timing circuit 4.

24 is a multiplexer for switching and designating the addresses of the memories M _{1 to} M ₆ by the command of the address counter 9 or the CPU 10, 2
A decoder 5 selects any one of the memories M _{1 to} M ₆ based on a command from the CPU 10. Each latch circuit L ₁ ~
Each of L ₆ , L _{10 to} L ₅₀ , memories M _{1 to} M ₆ , address counter 9, multiplexer 24, and decoder 25 is composed of a circuit that operates at a low speed, for example, a TTL circuit.

Next, the operation of this embodiment will be described with reference to the waveform chart shown in FIG. 2 and the time charts shown in FIGS. FIG. 2 is a waveform diagram of the same reflected wave signal T as that shown in FIG. A pulse shown in FIG. 3 (a) is output from the timing circuit 4, and the A / D conversion circuit 7a converts the reflected wave signal T into a digital value corresponding to this every one cycle. Therefore, one cycle of the output pulse of the timing circuit 4 becomes the sampling time τ _S ′. The reflected wave signal T shown in FIG. 2 is sampled at time t ₀₁ and further at time t ₀₂ after time τ _S ′. In this way, sampling is sequentially performed at each time τ _S ′. In this embodiment, the sampling time τ _S ′ is 1 / the sampling time τ _S of the apparatus shown in FIG.
6, and the A / D conversion circuit 7a performs high-speed A / D conversion corresponding to this. Output data D ₁ , D ₂ , ... Of the A / D conversion circuit 7a is shown in FIG. 3 (i). These output data are one cycle latch of the output pulse of the timing circuit 4 by latch 7b, and output is converted by the translator 23 to a predetermined level in the latch circuit L ₁ ~L _6.

On the other hand, the output pulse of the timing circuit 4 is divided into 1/6 by the frequency dividing circuit 20 as shown in FIG. 3B, and this frequency divided signal is output to the shift register 21. Shift register 21
Outputs the input frequency-divided signals as six signals which are shifted by one cycle τ _S ′ of the output pulse of the timing circuit 4 as shown in FIGS. 3 (c) to (h). After these signals are converted into signals of a predetermined level by the translator 22, the output signal (1) of shift 0 is input to the latch circuit L ₁ , the output signal (2) of shift τ _S ′ is input to the latch circuit L ₂ , ... The output signal (6) of shift 5 · τ _S ′ is input to the latch circuit L ₆ .

Now, when the data D ₁ is output after being converted into digital values translator 23 by the A / D converter circuit 7a, when an output signal to the latch circuits L ₁ (1) is input, the data D ₁ is latch L Output signal (2) latched to ₁ only
The other latch circuits L _{2 to} L ₆ to which (6) is not input cannot latch the data D ₁ . Latch data D ₁ by latch L ₁ is executed one cycle of the output signal as shown in FIG. 3 (j) (1). After time τ _S ′, A / D
When the data D ₂ is output from the conversion circuit 7a, this data D ₂
Is latched only in the latch circuit L ₂ to which the output signal (2) is input as shown in FIG.
Latch L ₁ and the output signal is latched to D ₁ (3)
The latch circuits L _{3 to} L ₆ having no inputs of (6) to (6) are not latched. By the same operation, the data D _{3 to} D ₆ are transferred to the latch circuit L ₃
~ L ₆ will be sequentially latched.

On the other hand, the output signal (6) shown in FIG. 3 (h) which is output to the latch circuit L ₆ is also given to the latch circuits L _{10 to} L ₅₀ of the next stage. Therefore, when the output signal (6) is output, the data latched in each latch circuit L _{1 to} L ₅ correspond at the same time as shown by the dotted lines in FIGS. 3 (j) to (n). The latch circuit is switched to L _{10 to} L ₅₀ . This latch period is one cycle of the output signal (6).

While the operating state of the memory M ₁ ~M ₆ is output low-speed signal from the timing circuit 4 during one cycle of the output signal (6), the address counter 9 designates an address of the memory M ₁ ~M ₆ An address signal is output, and this address signal is input to the memories M _{1 to} M ₆ via the multiplexer 24 to specify those addresses. In this state, the data D ₁ -Latch latched by the latch circuits L ₁₀ -L ₅₀ until then.
D ₅ and data D latched in latch circuit L _6
As shown in FIGS. 3 (j) to 3 (o), ₆ is stored at a designated address of the corresponding memories M _{1 to} M _{6 at} the same time, for example, at an address A _{M (0)} of each of the memories M _{1 to} M _6. To be done.

Here, regarding the latch circuit L ₁ , the data D ₁ latched here disappears when one cycle of the output signal (1) elapses. However, the data D ₁ has already been latched in the latch circuit L ₁₀ at this time. On the other hand, at the same time when the next cycle of the output signal (1) rises, the latch circuit L ₁ latches the data being output at that time. This data is
Data as apparent from Figure (c) and Figure 3 (i)
₇ Just as the data _{D 8, D 9, ......,} D 12 are sequentially latched in the latch circuit _{L 1 ~L 6, L 10 ~L} 50 respectively, it is stored in the memory M ₁ ~M _6.

An example of the relationship between the data stored in each of the memories M _{1 to} M ₆ and the addresses as described above is shown in the following table.

Next, the operation of out taking the data stored in the memory M ₁ ~M _6. In order to meet various conditions such as the set measurement range, when the data to be extracted is determined, the CPU 10 outputs a signal designating the memory in which the data is stored to the decoder 25, The decoder 25 decodes this signal and outputs the signal to the designated memory. At the same time, a signal designating the address of the memory in which the data is stored is output from the CPU 10 to the multiplexer 24, and the multiplexer 24 switches the address accordingly and designates the address by the signal. As a result, the required data is fetched from the address of the memory to the CPU 10 and processed.

As described above, in this embodiment, a plurality of latch circuits and a plurality of memories are used for one A / D converter, and the plurality of latch circuits are driven by the shift signal obtained by shifting the divided signal. Therefore, even if the A / D converter performs high-speed conversion, it is not necessary to configure the memory with a circuit that operates at high speed, and as a result, it is possible to suppress power consumption and heat generation, and The price of the ultrasonic flaw detector can be reduced.

In the above description of the embodiment, the latch circuit and the memory are operated at a cycle of 1/6 of the conversion cycle of the A / D converter, but the invention is not limited to this, and the function of the memory is not limited to this. The period can be arbitrarily determined according to

〔The invention's effect〕

As described above, in the present invention, a plurality of latch circuits and a plurality of memories are used for a high-speed A / D converter, and the plurality of latch circuits are driven by a shift signal obtained by shifting a divided signal. As a result, the memory can be configured with a circuit that operates at a low speed, which can suppress power consumption and heat generation of the ultrasonic flaw detector.
Moreover, the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a part of an ultrasonic flaw detector according to an embodiment of the present invention, FIG. 2 is a waveform diagram of a reflected wave signal, and FIG. 3 (a).
(O) is a time chart showing the operation of the configuration shown in FIG. 1, FIG. 4 is a block diagram of the ultrasonic flaw detector, FIG. 5 is a waveform diagram of the reflected wave signal, and FIG. 6 is a block diagram of the waveform memory. , FIG. 7 is a block diagram of a part of an ultrasonic flaw detector that can be considered when a high-speed A / D conversion circuit is used. 4 '... Timing circuit, 7a ... A / D conversion circuit, 20 ...
Frequency divider, 21 ...... shift register, 24 ...... _{multiplexer, L 1 ~L 6, L 10} ~L 50 ...... latch, M ₁ ~M ₆ ...... memory.

Claims (1)

[Claims] 1. An ultrasonic reflected wave from an object to be inspected is received,
In an ultrasonic flaw detector that performs flaw detection on the flaw detection object by analyzing the received signal, a high-speed A / D converter that converts the received signal of the ultrasonic reflected wave into a digital value, and a shift that sequentially shifts a predetermined frequency signal Register and the high speed A /
A plurality of latch circuits for sequentially holding the output data of the D converter by each signal shifted by the shift register, and a plurality of low-speed memories for storing the output data held by these latch circuits are provided. Ultrasonic flaw detector.