JPH0833868B2 - Data transfer device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device, and more particularly to a data transfer device using a memory request method.

[Conventional technology]

Conventionally, in this type of data transfer device, the system control device performs bank busy management and priority determination for managing whether or not a plurality of banks of the main storage device are in use. When the channel device in the transfer device makes a memory request, the memory replies are returned in the order in which the memory request was made.
Memory requests that were not selected in the main memory bank busy check or priority judgment in the system controller
During that time, since the system control device is kept waiting, even if the request from the same data transfer device to be transferred is a request to an address that is not bank busy, it is also kept waiting.

[Problems to be Solved by the Invention]

As described above, the conventional data transfer device has a structure in which one memory request is waited at the same time as bank busy overlaps in the system control device, so that there is a drawback that subsequent memory requests are also waited together. is there.

[Means for solving the problem]

A data transfer device of the present invention includes a system control device and a channel device which are connected between a main memory device and a peripheral device input / output device, and requests the main memory device to read and write data from the channel device. In a data transfer device that makes a memory request and supplies reply data to the peripheral device input / output device, a request generation unit that generates the memory request information, and a carry-over number that updates a number each time the memory request is sent A turn-around number generating means, a first turn-around number adding means for adding the turn-around number to the memory request, and a temporary holding of the turn-around number added to the memory request by the system controller. Memory reply for data read / write request from storage device Second rounding number adding means for sending the rounding number to the channel device and sending it to the channel device, a memory reply storage buffer having an address set for each rounding number in the channel device, and the memory Memory reply storing means for storing a memory reply sent from the system control device in a reply storage buffer at a predetermined address designated by a carry number of the memory reply; and the memory reply in the order of generating the carry number. And a memory reply extracting means for extracting the memory reply from the storage buffer, and the channel device is configured by rearranging the memory replies in the order of sending the memory requests.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is an explanatory diagram showing the relationship between the carry-over number of the data transfer device shown in FIG. 1 and the number of request transmissions, and FIG. FIG. 4 is an explanatory view showing the relationship between the address of the reply storage buffer of the data transfer device shown in FIG. 1 and the circulating number of FIG. 2, and FIG. 4 shows the data flow for each configuration of the data transfer device of FIG. FIG. 5 is a block diagram showing an example of a system equipped with the data transfer device constructed according to FIG. 1, and FIG. 6 is a block diagram showing the configuration of a second embodiment of the present invention.

First, a first embodiment in which the number of carry-over numbers is 4 will be described.

In FIG. 1, 100 is a main memory, 200 is a system controller, 300 is a channel controller, 400 is a channel device,
401 is a request generation circuit, 402 is a turn around number generation circuit, 406 is a difference counter, 405 is a turn around processing circuit, 404
Is a reply valid flag, 203 is a bank busy check and priority determination circuit, and 204 and 205 are selectors.

Referring to FIGS. 1 and 5, the channel controller 300
Is a device that gives a transfer instruction 1 to the channel device 400 connected to the peripheral control device 600 to transfer data and controls the transfer. The request generation circuit 401 is
It is a circuit that generates memory request information consisting of a request code and a memory address based on the transfer instruction 1 given from the channel control device 300, and suppresses the generation of a request when the request suppression signal 7 comes.

Further, at the same time when the request is generated, the carry-over number generating circuit 402 is composed of a 2-bit counter which is incremented by 1 according to the number of memory request occurrences as shown in FIG. The count is updated by the trigger 2, and the value of the counter is carried around as the request number 4 and the request transmission register 40
Send to 3. At the same time, a turn around number sending trigger 5
Send The request transmission register 403 is a register for sending the memory request 3 from the request generation circuit 401 and the circulation number 4 from the circulation number generation circuit 402 to the system control device 200 at the same time.

The reply reception system 407 is a register for receiving the memory reply 24 for the memory request 3,
The reply storage address 8 and reply data 9 are output from the carry-back number that has been brought back. The reply storing buffer 408 stores the reply data 9 from the reply receiving register 407 at the address designated by the reply storing address 8. The reply valid display flag 404 is prepared corresponding to the address of the reply storing buffer 408, and corresponds to the address indicated by the reply storing address 8 at the same timing as the reply data 9 is stored in the reply storing buffer 408. Flag is set.

When reply data is output from the reply storage buffer 408 to the data output register 409, the flag of the address designated by the reply output address 10 is reset. The carry-over number processing circuit 405 includes a 2-bit counter, updates the count from the same value as the counter of the carry-over number generating circuit 402, and when the count value and the address indicated by the flag of the reply valid display flag 404 match, The value of the counter is generated as the reply output address 10. At the same time, the reply processing trigger 6 is transmitted.
The data output register 409 is a register for transmitting the reply data 11 output from the reply storage buffer 408 to the peripheral control device connected under the channel device 400. The difference counter 406 is a difference counter that counts up with the turn-around number sending trigger 5 from the turn-around number generating circuit 402 and counts down with a reply processing trigger 6 from the turn-around number processing circuit 405, and monitors the sending amount of the memory request. Therefore, when the difference counter value becomes 4, the request inhibition signal 7 is transmitted to the request generation circuit 401.

The IOP buffer 201 is a buffer that temporarily stores the memory request 21 from the channel device 400. The bank busy check priority determination circuit 203 is a circuit that determines the bank busy check and priority order of the main storage device 100 for a memory request request from each device, and generates a selection condition for the selectors 205 and 204. The IOP request stack buffer 202 is a first-in first-out method (hereinafter FIFO) in which the memory request 21 from the channel device 400 not selected by the bank busy check priority determination circuit 203 is temporarily stacked.
Called) buffer.

The memory request register 206 is a resist for sending the memory request selected by the bank busy check priority determination circuit 203 to the main storage device 100. The carry-on number stack 207 is stored in the main storage device 100 and the channel device 40.
This is a FIFO stack buffer that stacks the circulating numbers of the memory request when sending the memory request from 0. Memory reply register 208
Is a register for receiving the memory reply 23 from the main memory 100, and the received memory reply is the channel device 40.
In case of memory reply to 0, carry number stack 207
The carry-over number stacked in is added to the channel device 400.

First, the request generation circuit 401 is the channel control device 300.
When the transfer instruction 301 is received from the mobile terminal, the request information is generated, and at the same time, the personalized number generating circuit 402 carries the personalized number 4
Is generated and written in the request transmission register 403. The request transmission register 403 transmits the memory request 21 to the system control device 200. System controller 200
Captures the memory request 21 from the channel device 400 into the IOP buffer 201 and interrupts the bank busy check priority determination circuit 203.

The bank busy check priority determination circuit 203 determines the priority order according to the bank busy state of the main storage device 100 and the interrupt state from another device, and if the priority order is the highest, the request is transferred to the memory request register 206. If the priority is lower than other memory requests, the memory request 21 from the channel device 400 is stacked in the IOP request stack buffer 202. Next, when the memory request 21 comes from the channel device 400, if the highest priority is determined by the bank busy check and the priority determination circuit 203, the memory request is transferred to the memory request register 206, and the IOP request stack buffer. The last memory request that was stuck in 202 is overtaken.

As soon as the memory request from the channel device 400 is stored in the memory request register 206, the main memory device
When the memory request 23 is sent to the memory reply register 208 when the memory reply 23 returned from the main storage device 100 is stored in the memory reply number stack 207, the memory reply 23 is stored in the memory reply register 208. The carry-over number that has been stacked in the stack 207 is added, and the result is transferred to the channel device 400. The reply reception register 407 is stored in a predetermined address of the reply storage address according to the carry-back number that has been brought back. At the same time, the reply valid display flag 404 is set to inform the carry-over number processing circuit 405 that the memory reply is stored. When the memory reply to be transmitted next is returned from the value of the reply valid display flag 404 and the value of the difference counter 406, the carry-on number processing circuit 405 specifies the read address of the reply storage buffer 408. The reply data 11 is taken out to the data output register 409.

In this way, by controlling the carry-over number, even if the order of memory requests from the channel device 400 is switched in the system control device 200, the request can be rearranged in the channel device 400.

Next, the data transfer device shown in FIG. 1 will be described with reference to FIGS. FIG. 2 shows the relationship between the value of the circulating number counter inside the circulating number generating circuit 402 and the circulating number processing circuit 405, and the number of request transmissions.

FIG. 3 shows a data storage area of the reply storage buffer 408 and an address. Reply storage buffer
408 has a storage area for an address corresponding to the carry-over number shown in FIG.

FIG. 4 is a diagram simply showing a data flow in each device.

The memory request 21 sent by the channel device 400 is
The order is changed in the system controller 200, and the memory reply 24 is returned to the channel device 400 at random and is written in the reply storage buffer 408. However, when reading from the reply storage buffer 408, the memory reply 24 can be taken out to the data output register 409 in the order in which the memory request 21 is sent because it is the order of updating the carry-over number.

In FIG. 5, the channel device 400 and the system controller 2
The data transfer device shown in FIG. 1 is mounted on 00.

The main storage device 100 is for storing programs and processing data. The system control device 200 includes a main storage device 100 including an arithmetic processing device 500 and an input / output processing device 300.
Is a device for controlling the access path of the. Processor 50
0 is for executing the program stored in the main storage device 100 and issuing an input / output instruction to the input / output processing device 300 in accordance with an instruction from the program. The input / output processing device 300 is a device that executes data transfer between the main storage device 100 and the peripheral control device 600 and the peripheral device 700 according to an input / output instruction issued from the arithmetic processing device 500.

 Here, the second embodiment will be described.

Referring to FIG. 6, in the second embodiment compared with the first embodiment, the memory reply judging means 421 is provided in the channel device 400.
Is added, and all other parts except this are the same as in the first embodiment. Therefore, only the differences will be described here.

The memory reply judging means 421 is a reply judging circuit 410.
And the error display flag 411.
Whether 10 is the carry-over number 4 corresponding to the memory request 3 when the reply receiving register 407 receives the memory reply 24 by remembering the carry-over number 4 from the carry-over number generating circuit 402 when the memory request 3 is transmitted. In the circuit for checking (1), if the memory request from the channel device 400 is not a memory reply, an error is detected and the error display flag 411 is set.
When set, the error display flag 411 immediately stops the transfer and reports an error to the host device.

〔The invention's effect〕

As described above, according to the present invention, a means for generating a memory request in the channel device, a means for generating a carry-over number for updating the number each time the memory request is sent, and a carry-over number for adding to the memory request. A means for temporarily holding the carry-over number added to the memory request by the system control device, adding the held carry-over number to the memory reply from the main storage device, and sending it to the data transfer device; A means for writing a reply storage buffer having an address set for each turn-around number in the channel device and a means for writing a memory reply to the reply storage buffer for an address indicated by the turn-around number, and a means for taking out from the memory reply storage buffer in the order in which the turn-around number is generated. By providing the system control device, the main memory bank busy or Since the memory requests from the later of the same data transfer device to the memory request, even if the memory request is not selected in the previous determination has occurred is processed it is no wait, there is an effect that it shortens the memory access time.

Also, since the amount of prefetched data can be adjusted by changing the capacity of the reply storage buffer on the channel device side, the capacity of the IOP buffer in the system controller can be changed even when connecting a combination of high-speed transfer channels and low-speed transfer channels. It is possible to transfer data without any need, and since the buffer is prepared in the channel device and the amount of memory requests is managed, there is an effect that the capacity of the IOP buffer in the system control device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is an explanatory diagram showing the relationship between the carry-over number of the data transfer device shown in FIG. 1 and the number of request transmissions, and FIG. FIG. 4 is an explanatory view showing the relationship between the address of the reply storage buffer of the data transfer device shown in FIG. 1 and the circulating number of FIG. 2, and FIG. 4 shows the data flow for each configuration of the data transfer device of FIG. Explanatory diagram, FIG. 5 is a block diagram showing an example of a system equipped with the data transfer device constructed according to FIG. 1, and FIG. 6 is a block diagram showing a configuration of a second embodiment of the present invention. 100 ... Main storage device, 200 ... System control device, 300 ... Channel control device, 400 ... Channel device, 500 ... Arithmetic processing device, 600 ... Peripheral control device, 700 ... Peripheral device input / output device.

Claims (2)

[Claims] 1. A memory request including a system controller and a channel device, which is connected between a main memory device and a peripheral device input / output device, and which requests a data read / write from the channel device to the main memory device. In a data transfer device for supplying reply data to the peripheral device input / output device, a request generation means for generating the memory request information, and a rotation circuit for generating a rotation number for updating the number each time the memory request is transmitted. Number generating means, first circulating number adding means for adding the circulating number to the memory request, and a temporary storage for the circulating number added to the memory request in the system control device, from the main storage device. The memory reply to the data read / write request of Second turn around number adding means for adding a number to the channel device, sending to the channel device, a memory reply storing buffer having an address set for each turn around number in the channel device, and the memory reply storing buffer Memory reply storing means for storing the memory reply sent from the system control device at a predetermined address designated by the turn around number of the memory reply, and the memory reply storage buffer to the memory in the order of generation of the turn around number. A data transfer device, comprising: a memory reply extracting means for extracting a reply, wherein the memory replies are rearranged in the channel device in the order of the memory request transmission. 2. The data transfer device according to claim 1, further comprising a memory reply judging means for judging whether the memory reply has returned normally from the system control device.