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JPH0834280B2 - Semiconductor device - Google Patents
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JPH0834280B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0834280B2
JPH0834280B2 JP1051157A JP5115789A JPH0834280B2 JP H0834280 B2 JPH0834280 B2 JP H0834280B2 JP 1051157 A JP1051157 A JP 1051157A JP 5115789 A JP5115789 A JP 5115789A JP H0834280 B2 JPH0834280 B2 JP H0834280B2
Authority
JP
Japan
Prior art keywords
substrate
board
terminal
chip
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1051157A
Other languages
Japanese (ja)
Other versions
JPH02230762A (en
Inventor
周幸 加藤
次郎 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1051157A priority Critical patent/JPH0834280B2/en
Publication of JPH02230762A publication Critical patent/JPH02230762A/en
Publication of JPH0834280B2 publication Critical patent/JPH0834280B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に基板端子とピンと
の配線を行う半導体装置用パッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device package in which wiring between a substrate terminal and a pin is performed.

〔従来の技術〕[Conventional technology]

従来、半導体装置用パッケージの配線は、基板端子と
同一面に配線回路を設けていたため、チドリ状に基板端
子を設けた場合、外側の基板端子はそのまま配線回路に
配線することができたが、内側の基板端子は外側の基板
端子の間を通して配線回路に配線していた。
Conventionally, the wiring of the semiconductor device package has been provided with the wiring circuit on the same surface as the substrate terminal, so when the substrate terminal is provided in a puddle shape, the outer substrate terminal can be directly wired to the wiring circuit. The inner board terminals were wired in the wiring circuit through the outer board terminals.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

上述した従来のチドリ状にした基板端子の配線は、内
側の基板端子を外側の基板端子の間を通して配線回路に
配線していたので、内側の基板端子より外側の基板端子
が細くなってしまう。そのため、ボンディング時に基板
端子からワイヤが落ちてしまうスイッチ落ち不良や、ボ
ンディングワイヤがカールし隣りのワイヤとショートし
てしまう不良等が発生し、ボンディング歩留りが低いと
いう欠点があり、またボンディングワイヤ引張強度にお
いても通常より弱くなるため、温度サイクル等の試験を
行った場合その信頼性が低いという欠点がある。
In the above-described conventional wiring of the board terminals in the form of a puddle, since the inner board terminals are arranged in the wiring circuit through the outer board terminals, the outer board terminals are thinner than the inner board terminals. As a result, there are drawbacks such as a low switch yield, in which the wire drops from the substrate terminal during bonding, and a defect in which the bonding wire curls and short-circuits with the adjacent wire, and the bonding yield is low. Since it is weaker than usual, there is a drawback that the reliability is low when a test such as a temperature cycle is conducted.

本発明の目的は、これらの欠点を除き、接続の信頼性
を高めた半導体装置を提供することにある。
An object of the present invention is to eliminate the above drawbacks and to provide a semiconductor device having improved connection reliability.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の構成は、ICチップと、このICチップを中央部
にマウントした絶縁性基板と、この基板上で前記ICチッ
プのマウント面周辺に多数植設された外部接続用ピンと
を備え、前記基板には、この基板の一方の面に設けられ
た配線部分からなり前記ICチップの各端子とワイヤによ
りそれぞれ結線される基板端子と、前記基板面で前記各
基板端子と前記各外部接続用ピンとの間にそれぞれ配設
された配線回路とを有する半導体装置において、前記配
線回路が前記基板の両面で均数に配設されるように、そ
の配線回路の半数が前記基板の一方の面で前記基板端子
と前記外部接続用ピンとの間で直接配線され、その配線
回路の他の半数が前記基板の他方の面で前記外部接続用
ピンに配線されて前記ICチップのマウント面近傍でかつ
前記各基板端子よりそのマウント面の内側に設けたスル
ーホールまたは半スルーホールを介して前記基板端子と
接続したことを特徴とする。
The configuration of the present invention comprises an IC chip, an insulating substrate having the IC chip mounted in the central portion, and a large number of external connection pins implanted around the mounting surface of the IC chip on the substrate. Is a board terminal which is composed of a wiring portion provided on one surface of this board and is connected to each terminal of the IC chip by a wire, respectively, and each board terminal and each external connection pin on the board surface. In a semiconductor device having wiring circuits respectively disposed between them, half of the wiring circuits are provided on one surface of the substrate so that the wiring circuits are evenly arranged on both surfaces of the substrate. Directly wired between the terminal and the external connection pin, and the other half of the wiring circuit is wired to the external connection pin on the other surface of the substrate, in the vicinity of the mounting surface of the IC chip and on each of the substrates. That from the terminal It is characterized in that it is connected to the substrate terminal through a through hole or a half through hole provided inside the mount surface.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図(a),(b)は本発明の一実施例の平面図お
よびその縦断面図である。この実施例は、ガラスエポキ
シ等の電気絶縁性基板1の平面上に基板端子をチドリ状
に設け、外側の基板端子16は平面上に布設した配線回路
4によりピン挿入用スルーホール3まで配線し、ピン7
と電気的に導通させる。
1 (a) and 1 (b) are a plan view and a longitudinal sectional view of one embodiment of the present invention. In this embodiment, board terminals are provided in a puddle shape on the plane of an electrically insulating board 1 made of glass epoxy or the like, and the board terminals 16 on the outside are wired to the through holes 3 for pin insertion by a wiring circuit 4 laid on the plane. , Pin 7
To electrically connect with.

また、内側の基板端子2はその基板端子とマウント面
11の間に設けたφ0.1〜φ0.4mmのバイパス用スルーホー
ル5の通って裏面上に布設した配線回路4に結びそれか
らピン挿入用スルーホール3まで配線し、ピン7と電気
的に導通させている。この場合、基板端子の幅は外側,
内側とも0.25mm、間隔は0.15mmで0.4mmピッチとし、バ
イパスのためのスルーホール5は半田等のスルーホール
止め12により封じ込めている。
In addition, the inner board terminal 2 is mounted on the board terminal and the mounting surface.
Connect to the wiring circuit 4 laid on the back surface through the through hole 5 for bypass of φ0.1 to φ0.4 mm provided between 11 and then connect to the through hole 3 for pin insertion to electrically connect to the pin 7. I am letting you. In this case, the width of the board terminal is outside,
The inner side is 0.25 mm, the interval is 0.15 mm and 0.4 mm pitch, and the through hole 5 for bypass is enclosed by a through hole stopper 12 such as solder.

第2図(a),(b)は本発明の第2の実施例の裏面
図およびその縦断面図である。この実施例では、裏面上
に基板端子を設け、外側の基板端子16は裏面上に布設し
た配線回路4によりピン挿入用スルーホール3と配線
し、ピン7と電気的に接続される。また、内側の基板端
子2はこの端子2とマウント面11との間に設けた直径0.
1〜0.5mmのバイパス用半スルーホール15と接続される。
この半スルーホール15はマウント面11を貫通させ半スル
ーホールとしており、ここを通って平面上に設けた配線
回路4によりピン挿入用スルーホール3まで配線し、ピ
ン7と電気的に接続される。この基板端子2のピッチ
は、内,外とも0.4mmにしている。基板1を打抜いた部
分には、ヒートシンク型ベース13を絶縁性樹脂14にて取
付けて、半スルーホール15を封込めるとともにマウント
面11を形成する。
2 (a) and 2 (b) are a rear view and a longitudinal sectional view of the second embodiment of the present invention. In this embodiment, a board terminal is provided on the back surface, and the board terminal 16 on the outside is wired to the through hole 3 for pin insertion by the wiring circuit 4 laid on the back surface and electrically connected to the pin 7. In addition, the board terminal 2 on the inner side has a diameter of 0.1 mm provided between the terminal 2 and the mounting surface 11.
It is connected to a 1-0.5 mm bypass half through hole 15.
The half through hole 15 penetrates the mount surface 11 to form a half through hole, and the wiring circuit 4 provided on the plane passes through the half surface to reach the pin insertion through hole 3 and is electrically connected to the pin 7. . The pitch of the board terminals 2 is 0.4 mm both inside and outside. A heat sink type base 13 is attached to the punched portion of the substrate 1 with an insulating resin 14 to seal the half through hole 15 and form a mount surface 11.

本実施例では、熱抵抗を1/2以下にすることができる
し、半スルーホールにすることによりボンディングワイ
ヤ8の長さを短く出来、ボンディングスピード及び歩留
を向上させることができる。
In this embodiment, the thermal resistance can be reduced to 1/2 or less, and the length of the bonding wire 8 can be shortened by using a half through hole, and the bonding speed and the yield can be improved.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、基板端子とマウント面
の間にバイパス用スルーホール又は半スルーホールを設
け、外側の基板端子と内側の基板端子を表面上と裏面
上,又は裏面上と表面上に分けて配線回路を設けること
により、基板端子が直行型で同一間隔にした場合での基
板端子の幅は外側と内側とも等しく、放射型で同一間隔
にした場合での基板端子の幅は外側の方が内側より広く
なりボンディング性(接合性)が向上する。また、配線
回路を平面上と裏面上に2分するため同一配線幅及び間
隔にした場合、2倍の配線数にすることができ多ピン化
及び多端子化が容易になる。さらに、同一ピン及び端子
の場合、2倍の配線幅及び間隔にするとができるので電
気的特性が向上する。
As described above, according to the present invention, a bypass through hole or a half through hole is provided between the board terminal and the mount surface, and the outer board terminal and the inner board terminal are on the front surface and the back surface, or on the back surface and the front surface. By providing the wiring circuit separately, the width of the board terminals is the same when the board terminals are of the orthogonal type and are arranged at the same interval, and the width of the board terminals is the same when the board terminals are arranged at the same distance of the radiation type. Is wider than the inner side, and the bondability (bondability) is improved. Also, since the wiring circuit is divided into two on the plane and on the back surface, if the wiring width and spacing are the same, the number of wirings can be doubled, and the number of pins and the number of terminals can be increased easily. Furthermore, in the case of the same pin and terminal, the wiring width and spacing can be doubled, so that the electrical characteristics are improved.

【図面の簡単な説明】[Brief description of drawings]

第1図(a),(b)は本発明の第1の実施例の平面図
およびその縦断面図、第2図(a),(b)は本発明の
第2の実施例の裏面図およびその縦断面図である。 1……電気絶縁性基板、2……内側の基板端子、3……
ピン挿入用スルーホール、4……配線回路、5……バイ
パス用スルーホール、6……ICチップ、7……ピン、8
……ワイヤ、9……ICチップの端子、10……マウント部
材、11……マウント面、12……スルーホール止め、13…
…ヒートシンク型ベース、14……取付け樹脂、15……バ
イパス用半スルーホール、16……外側の基板。
1 (a) and 1 (b) are a plan view and a longitudinal sectional view of the first embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are rear views of the second embodiment of the present invention. FIG. 3 is a vertical sectional view thereof. 1 ... Electrically insulating substrate, 2 ... Inner substrate terminal, 3 ...
Through hole for pin insertion, 4 ... Wiring circuit, 5 ... Through hole for bypass, 6 ... IC chip, 7 ... Pin, 8
...... Wire, 9 ...... IC chip terminal, 10 ...... Mounting member, 11 ...... Mounting surface, 12 ...... Through hole stopper, 13 ...
… Heat sink type base, 14… Mounting resin, 15… By-pass half through hole, 16… Outside board.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】ICチップと、このICチップを中央部にマウ
ントした絶縁性基板と、この基板上で前記ICチップのマ
ウント面周辺に多数植設された外部接続用ピンとを備
え、前記基板には、この基板の一方の面に設けられた配
線部分からなり前記ICチップの各端子とワイヤによりそ
れぞれ結線される基板端子と、前記基板面で前記各基板
端子と前記各外部接続用ピンとの間にそれぞれ配設され
た配線回路とを有する半導体装置において、前記配線回
路が前記基板の両面で均数に配設されるように、その配
線回路の半数が前記基板の一方の面で前記基板端子と前
記外部接続用ピンとの間で直接配線され、その配線回路
の他の半数が前記基板の他方の面で前記外部接続用ピン
に配線されて前記ICチップのマウント面近傍でかつ前記
各基板端子よりそのマウント面の内側に設けたスルーホ
ールまたは半スルーホールを介して前記基板端子と接続
したことを特徴とする半導体装置。
1. An IC chip, an insulating substrate having the IC chip mounted in a central portion, and a large number of external connection pins implanted around the mounting surface of the IC chip on the substrate. Is a board terminal formed of a wiring portion provided on one surface of the board and connected to each terminal of the IC chip by a wire, and between the board terminal and the external connection pin on the board surface. In a semiconductor device having wiring circuits respectively arranged on the substrate terminals, half of the wiring circuits are arranged on one surface of the substrate so that the wiring circuits are evenly arranged on both surfaces of the substrate. And the external connection pins are directly wired, and the other half of the wiring circuit is wired to the external connection pins on the other surface of the substrate, near the mounting surface of the IC chip, and the substrate terminals. More that mau A semiconductor device, wherein the semiconductor device is connected to the substrate terminal through a through hole or a half through hole provided inside a semiconductor surface.
JP1051157A 1989-03-02 1989-03-02 Semiconductor device Expired - Lifetime JPH0834280B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1051157A JPH0834280B2 (en) 1989-03-02 1989-03-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1051157A JPH0834280B2 (en) 1989-03-02 1989-03-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH02230762A JPH02230762A (en) 1990-09-13
JPH0834280B2 true JPH0834280B2 (en) 1996-03-29

Family

ID=12878994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1051157A Expired - Lifetime JPH0834280B2 (en) 1989-03-02 1989-03-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0834280B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6122358U (en) * 1984-07-12 1986-02-08 株式会社東芝 Pin grid array package

Also Published As

Publication number Publication date
JPH02230762A (en) 1990-09-13

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