JPH0834281B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0834281B2 JPH0834281B2 JP62226856A JP22685687A JPH0834281B2 JP H0834281 B2 JPH0834281 B2 JP H0834281B2 JP 62226856 A JP62226856 A JP 62226856A JP 22685687 A JP22685687 A JP 22685687A JP H0834281 B2 JPH0834281 B2 JP H0834281B2
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- lead
- semiconductor
- semiconductor device
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、樹脂型半導体パッケージに半導体チップが
搭載された半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a resin type semiconductor package.
従来の技術 従来の樹脂封止型半導体パッケージに用いられるリー
ドフレームは、ほぼ中央に半導体素子を固着するため
に、幅，長さともに半導体素子より0.3mm以上大きい固
着台（以下、ダイパッドと呼ぶ）があり、このダイパッ
ドはパッケージ内での定められた位置に固定される。ダ
イパッドの固定は、２本以上の吊りリードで周囲のフレ
ームの一部に継がれる。そして、ダイパッド表面には、
１μｍ以上の厚さの金や銀のメッキ層が施され、その上
に共晶（金／シリコン）や導電性粉末入りペーストで半
導体素子が固着される。2. Description of the Related Art A lead frame used in a conventional resin-encapsulated semiconductor package has a width and length of 0.3 mm or more larger than a semiconductor element in order to fix a semiconductor element to the center (hereinafter referred to as a die pad). And the die pad is fixed in place within the package. The die pad is fixed to a part of the surrounding frame by two or more suspension leads. And on the surface of the die pad,
A gold or silver plating layer having a thickness of 1 μm or more is applied, and a semiconductor element is fixed thereon by a eutectic (gold / silicon) or paste containing conductive powder.
ダイパッドの周囲には、半導体素子表面上の端子と電
気的接続を形成するために、リード（以降インナーリー
ドと呼ぶ）が配置されている。そして、ダイパッド面は
周囲のインナーリードの面より0.15〜0.3mm下げるため
に、吊りリード部で折り曲げ（ディプレス加工）られて
いる。配置されるインナーリードの本数は、パッケージ
外部に突き出ているリード（以降アウターリードと呼
ぶ）の数と同等である。Leads (hereinafter referred to as inner leads) are arranged around the die pad to form electrical connections with terminals on the surface of the semiconductor element. The die pad surface is bent (depressed) at the suspension lead portion in order to lower the die pad surface by 0.15 to 0.3 mm from the surrounding inner lead surface. The number of inner leads arranged is equal to the number of leads (hereinafter referred to as outer leads) protruding outside the package.
このような構造のリードフレームは、ダイパッド部に
半導体素子を載置し、インナーリード部と所望の結線を
なしたものを熱硬化性の樹脂で覆い、必要とするパッケ
ージの外形にする。In the lead frame having such a structure, the semiconductor element is mounted on the die pad portion, and the inner lead portion and the desired connection are covered with a thermosetting resin to obtain the required package outline.
発明が解決しようとする問題点 産業用，民生用の両分野で、半導体装置の機能と外形
とに関し、製造業者間での互換性が必須条件となってい
る。とりわけ半導体大容量メモリー等ではこの種の互換
性を抜きにしては、市場での競争力が著しく下がる。そ
こで搭載する半導体素子寸法の大小が、この互換性を保
つためのパッケージ設計の難易度や品質の良否を支配す
る。従来のパッケージ設計では、半導体素子寸法が大き
くなればアウターリード幅を一定寸法に保ち、樹脂部の
幅を可能な限り広げて、半導体素子の搭載に当たってき
たが、目標とする品質水準に対する低下の原因となるア
ウターリード成形技術、とりわけパッケージ樹脂中に埋
め込まれるリードの深さ等に問題が残っていた。Problems to be Solved by the Invention In both the industrial and consumer fields, compatibility between manufacturers is essential for the function and external shape of semiconductor devices. Especially in the case of semiconductor large-capacity memory and the like, without this type of compatibility, the competitiveness in the market will drop significantly. Therefore, the size of the semiconductor element to be mounted controls the difficulty and quality of the package design for maintaining this compatibility. In the conventional package design, the outer lead width was kept constant as the semiconductor element size increased, and the width of the resin part was widened as much as possible to mount the semiconductor element. However, there remains a problem with the outer lead molding technology, especially the depth of the leads embedded in the package resin.
問題点を解決するための手段 本発明では、上述した問題を解決するために、ダイパ
ッド、インナーリードが一体化形成されたリードフレー
ムと、前記ダイパッドに設けられた切り取り部と、前記
切り取り部にインナーリードの一部が入り込み、かつ、
前記ダイパッドの底面が少なくとも前記インナーリード
の上面より上に位置し、前記切り取り部を覆うように前
記ダイパッドに半導体チップが搭載された半導体装置で
ある。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a lead frame in which a die pad and an inner lead are integrally formed, a cutout portion provided in the die pad, and an inner cutout portion. Part of the lead has entered, and
In the semiconductor device, a bottom surface of the die pad is located at least above an upper surface of the inner lead, and a semiconductor chip is mounted on the die pad so as to cover the cutout portion.
作用 本発明の半導体装置は、リードフレームのダイパッド
の一部までインナーリードのリードパターンを設けてい
るので、インナーリードが樹脂中に深く埋設される。従
って、リードの引き抜き強度の改善と、水の進入経路の
延長による長寿命化が図れる。さらに、ダイパッドに切
り取り部を設けたので半導体素子と樹脂との接触する面
積が増えるためにこれら両者間の密着性が高まる。ま
た、大きな半導体チップにも対応できる。Action In the semiconductor device of the present invention, since the lead pattern of the inner leads is provided up to a part of the die pad of the lead frame, the inner leads are deeply embedded in the resin. Therefore, it is possible to improve the pull-out strength of the lead and extend the life by extending the water entry path. Further, since the cutout portion is provided on the die pad, the area of contact between the semiconductor element and the resin is increased, so that the adhesion between them is improved. It can also be applied to large semiconductor chips.
実施例 本発明の半導体装置に適用されるインナーリードの斜
視図を第１図に、本発明の半導体装置を第２図に示す。
以下、これらを参照して説明する。EXAMPLE FIG. 1 shows a perspective view of an inner lead applied to a semiconductor device of the present invention, and FIG. 2 shows a semiconductor device of the present invention.
Hereinafter, description will be made with reference to these.
先ず、第１図で示すように、リードフレーム１の半導
体チップ２が搭載されるダイパッド３の一部を、インナ
ーリード４の形状に合わせて切り取る。その切り取り部
５にインナーリード４を構成するリードの一部６が入る
ように配置する。First, as shown in FIG. 1, a part of the die pad 3 on which the semiconductor chip 2 of the lead frame 1 is mounted is cut out according to the shape of the inner lead 4. The cutout portion 5 is arranged so that a part 6 of the lead forming the inner lead 4 is inserted.
次にダイパッド３を吊っている吊りリード７はディプ
レス折り曲げ部８の加工を施す。組立ての際、半導体チ
ップとインナーリード４との接触を防ぐために曲げの方
向はダイパッド３の底面がインナーリード４より高くな
る構造にする。このリードフレーム１のダイパッド3,イ
ンナーリード４の各々の先端部に１〜５μｍの金又は銀
のメッキを施したメッキ領域９を設ける。第２図は本発
明の半導体装置を示す。半導体チップ２はヒートブロッ
クを有する半導体チップ固着装置に載せられたダイパッ
ド３上に、還元雰囲気中で450〜490℃の温度範囲で、金
−シリコン共晶によって固着する。このとき半導体チッ
プ２はダイパッド３に設けた切り取り部（凹部）５を覆
うように固着される。こうした構成によって、半導体チ
ップ２とダイパッド３との接触面積が減るために、ダイ
パッドを介しての水の侵入を少なくすることができる。
また、半導体チップ２とプラスチック12との接触面積が
増えるために、耐湿性や強度が向上する。さらに、本願
発明では、半導体チップがインナーリード４の位置に制
約を受けないために、半導体チップ２の大型化に対応で
きる。そして、半導体チップ２の端子11とインナーリー
ド４の先端部はワイヤー10によって接続する。Next, the suspension leads 7 suspending the die pad 3 are processed into the depress bending portion 8. At the time of assembly, in order to prevent contact between the semiconductor chip and the inner leads 4, the bending direction is such that the bottom surface of the die pad 3 is higher than the inner leads 4. The die pad 3 and the inner lead 4 of the lead frame 1 are provided with a plated region 9 plated with gold or silver having a thickness of 1 to 5 μm on the respective tips. FIG. 2 shows a semiconductor device of the present invention. The semiconductor chip 2 is fixed on the die pad 3 mounted on the semiconductor chip fixing device having a heat block by a gold-silicon eutectic in a temperature range of 450 to 490 ° C. in a reducing atmosphere. At this time, the semiconductor chip 2 is fixed so as to cover the cutout portion (recess) 5 provided on the die pad 3. With such a configuration, the contact area between the semiconductor chip 2 and the die pad 3 is reduced, so that water intrusion through the die pad can be reduced.
Further, since the contact area between the semiconductor chip 2 and the plastic 12 is increased, the moisture resistance and the strength are improved. Further, according to the present invention, since the semiconductor chip is not restricted by the position of the inner lead 4, the semiconductor chip 2 can be upsized. The terminal 11 of the semiconductor chip 2 and the tip of the inner lead 4 are connected by the wire 10.
これを機械的破壊，電気的絶縁，周囲環境からの保護
を目的として、プラスチック12でパッケージ形状に成形
して本願発明の半導体装置は完成する。For the purpose of mechanical destruction, electrical insulation, and protection from the surrounding environment, this is molded into a package shape with plastic 12 to complete the semiconductor device of the present invention.
発明の効果 本発明の半導体装置によれば、半導体大容量メモリー
に見られるような埋設深さが浅く、しかも細いインナー
リードで発生する耐湿性やリードの引抜き強度の低下を
ダイパッドの一部に配置して延長したインナーリード形
状で改善することができる。EFFECTS OF THE INVENTION According to the semiconductor device of the present invention, a decrease in burying depth as seen in a semiconductor large-capacity memory and a decrease in moisture resistance and lead extraction strength generated by a thin inner lead are arranged in a part of a die pad It can be improved by the extended inner lead shape.
第１図は本発明の半導体装置が適用されるリードフレー
ムの斜視図、第２図は本願発明の半導体装置の断面図で
ある。 １……リードフレーム、２……半導体チップ、３……ダ
イパッド、４……インナーリード、５……切り取り部、
６……リードの一部、７……吊りリード、８……ディプ
レス折り曲げ部、９……メッキ領域、10……ワイヤ、11
……端子、12……プラスチック、13……アウターリー
ド。FIG. 1 is a perspective view of a lead frame to which the semiconductor device of the present invention is applied, and FIG. 2 is a sectional view of the semiconductor device of the present invention. 1 ... Lead frame, 2 ... Semiconductor chip, 3 ... Die pad, 4 ... Inner lead, 5 ... Cut-off part,
6 ... Part of lead, 7 ... suspension lead, 8 ... depressed bent portion, 9 ... plated area, 10 ... wire, 11
…… Terminal, 12 …… Plastic, 13 …… Outer lead.
Claims (1)
されたリードフレームと、前記ダイパッドに設けられた
切り取り部と、前記切り取り部にインナーリードの一部
が入り込み、かつ、前記ダイパッドの底面が少なくとも
前記インナーリードの上面より上に位置し、前記切り取
り部を覆うように前記ダイパッドに半導体チップが搭載
されたことを特徴とする半導体装置。1. A lead frame in which a die pad and an inner lead are integrally formed, a cutout portion provided in the die pad, a part of the inner lead enters the cutout portion, and a bottom surface of the die pad is at least the above. A semiconductor device, wherein a semiconductor chip is mounted on the die pad so as to be located above the upper surface of the inner lead and cover the cutout portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62226856A JPH0834281B2 (en) | 1987-09-10 | 1987-09-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62226856A JPH0834281B2 (en) | 1987-09-10 | 1987-09-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6469041A JPS6469041A (en) | 1989-03-15 |
| JPH0834281B2 true JPH0834281B2 (en) | 1996-03-29 |
Family
ID=16851641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62226856A Expired - Lifetime JPH0834281B2 (en) | 1987-09-10 | 1987-09-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0834281B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2522524B2 (en) * | 1988-08-06 | 1996-08-07 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JP3088193B2 (en) * | 1992-06-05 | 2000-09-18 | 三菱電機株式会社 | Method for manufacturing semiconductor device having LOC structure and lead frame used therein |
| DE4345303C2 (en) * | 1992-06-05 | 2003-12-04 | Mitsubishi Electric Corp | Lead wire frames for use in manufacturing a LOC structure semiconductor device and method for manufacturing a LOC structure semiconductor device |
| US5519576A (en) * | 1994-07-19 | 1996-05-21 | Analog Devices, Inc. | Thermally enhanced leadframe |
| JP5562780B2 (en) * | 2010-09-21 | 2014-07-30 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62154764A (en) * | 1985-12-27 | 1987-07-09 | Hitachi Ltd | Resin sealed semiconductor device |
-
1987
- 1987-09-10 JP JP62226856A patent/JPH0834281B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6469041A (en) | 1989-03-15 |
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