JPH0834288B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a MIM using a polycrystalline silicon film as a lower electrode.
The present invention relates to a method for manufacturing a semiconductor device having a layer into which an impurity has been introduced and etched, which is applied to a method for manufacturing a (Metal-Insulator-Metal) capacitor and the like.

[Conventional technology]

FIG. 3 is a process sectional view showing a method of manufacturing a conventional MIM capacitor having a structure of polycrystalline silicon film-insulating film-polycrystalline silicon film. As shown in FIG. 3 (a), first, on the main surface of the silicon substrate 1, a thickness of about 100 n is formed by, for example, a thermal oxidation method.
A silicon oxide film 2 of m is formed. Next, on the surface of the silicon oxide film 2, for example, low pressure CVD (Chemical Vapor Deposi
and a polycrystalline silicon film 3 having a thickness of about 200 nm is formed by the ionization method. Next, as shown in FIG. 3B, arsenic ions 5, for example, are implanted into the polycrystalline silicon film 3 at an implantation energy of 50 Kev and a dose of 2 × 10 ¹⁵ / cm ² . Polycrystalline silicon film 3
Since the projection range R _p of the arsenic ions 5 in the inside is about 30 nm and the dispersion ΔR _p of the distribution is about 10 nm, the distribution of the arsenic ions in the polycrystalline silicon film 3 is the surface of the polycrystalline silicon film 3. Has a mean value at a depth of about 30 nm and the dispersion is approximated by a Gaussian distribution of about 10 nm.

Next, as shown in FIG. 3C, after the pattern of the resist 6 is formed by using the existing photolithography method, the resist 6 is used as a mask by, for example, the reactive ion etching method for increasing the capacitor area. The polycrystalline silicon film 3 is etched. At this time, the side surface 7 of the polycrystalline silicon film 3 is also etched and recedes. Since the etching rate is higher as the arsenic concentration in the polycrystalline silicon film 3 is higher, the side surface 7 reflects the distribution of the implanted arsenic ions 5, and the portion of the polycrystalline silicon film 3 that is approximately 30 nm from the surface is most etched. As a result, a shape having a corner 11 is formed.

Then, as shown in FIG. 3D, the resist 6 is removed, and the silicon oxide film 2 is formed by using, for example, a low pressure CVD method.
Then, a silicon oxide film 8 having a thickness of about 10 nm is formed on the polycrystalline silicon film 3. Further, for example, a phosphorus-doped polycrystalline silicon film 9 is grown on the formed silicon oxide film 8 and patterned so as to serve as an upper electrode. Thereafter, for example, heat treatment is performed in a nitrogen atmosphere at 900 ° C. to activate phosphorus in the polycrystalline silicon film 9 and arsenic in the polycrystalline silicon film 3 to form a capacitor using the respective electrodes as electrodes as shown in the figure. .

For example, + 5V is applied to the polycrystalline silicon film 9 doped with phosphorus.
Is applied to keep the polycrystalline silicon film 3 at the ground potential 0 V,
A charge Q is stored in this capacitor. The potential difference is 5V,
Since the thickness of the silicon oxide film 8 as an insulating film is 10 nm,
The magnitude of the electric field E ₈ applied to the silicon oxide film 8 on the flat surface portion of the polycrystalline silicon film 3 is E ₈ = 5 MV / cm. Since the shape of the corner 11 is an acute angle, the electric field due to the charge Q is concentrated and becomes stronger. As a result, the electric field E ₁₁ (MV / cm) higher than E ₈ = 5MV / cm
Is applied to the corner 11 of the silicon oxide film 8, so that dielectric breakdown is likely to occur. That is, when the corner 11 is present, the dielectric breakdown voltage of the silicon oxide film 8 is significantly reduced.

FIGS. 4 (a) and 4 (b) are histograms showing the relationship between the voltage and the frequency at which dielectric breakdown occurs in a planar MIM capacitor having no corners and a conventional MIM capacitor having corners 11, respectively. The sample shown in Fig. 4 (a) is a planar MIM capacitor with a total area of 1.0mm ² facing the electrode plate and no corners, and the sample of Fig. 4 (b) has a total area of 1.0mm ² facing the electrode plate with a square shape. This is a MIM capacitor in which the total length of the sides forming the part is 173 mm. The sample of FIG. 4 (b) has a more complicated structure than the planar sample of FIG. 4 (a) because the total facing area is increased within a limited chip area.

The horizontal axis of the histogram is the positive voltage applied to the polycrystalline silicon film 9 when the polycrystalline silicon film 3 is grounded,
The breakdown voltage is shown in increments of 5V. The vertical axis is MI
It is the number of times the dielectric breakdown of M capacitors is converted into a percentage.

The mode of the dielectric breakdown voltage is 8. in Fig. 4 (a).
It is at a level of 5 to 9.0 V, and in Fig. 4 (b) it is 5.5 to
It is at the level of 6.0V. In FIG. 4 (b), the breakdown voltage is largely reduced due to the corner 11.

[Problems to be Solved by the Invention]

Since the conventional method of manufacturing a semiconductor device is configured as described above, it is not possible to control the impurity distribution in the polycrystalline silicon film 3 which will be the lower electrode of the MIM capacitor, for example. Therefore, when impurities are injected into the polycrystalline silicon film 3 and anisotropic etching is performed to increase the capacitor area, an acute angle 11 is formed and the dielectric breakdown voltage of the capacitor is significantly reduced.

The present invention has been made to solve the above problems, for example, it is possible to control the impurity concentration in a semiconductor layer such as a polycrystalline silicon film to be a lower electrode of an MIM capacitor to have a desired distribution. An object of the present invention is to obtain a method for manufacturing a semiconductor device in which the shape after etching is rounded so that the characteristics of the semiconductor device having the semiconductor layer are improved, such as increasing the breakdown voltage of the MIM capacitor.

[Means for solving the problem]

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor layer, a step of forming a buffer layer on the semiconductor layer, and a distribution in which an impurity concentration in the semiconductor layer monotonically decreases along a depth direction. And a step of removing the buffer layer, and a step of anisotropically dry etching the semiconductor layer according to a predetermined pattern.

[Action]

In the present invention, since the impurity concentration in the semiconductor layer can be controlled by the buffer layer to have a distribution that monotonically decreases along the depth direction, the shape of the semiconductor layer after etching becomes a desired shape.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a process sectional view showing a method of manufacturing an MIM capacitor according to an embodiment of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 2 having a thickness of about 100 nm is formed on the main surface of a silicon substrate 1 by, for example, a thermal oxidation method. Then, a polycrystalline silicon film 3 having a thickness of about 200 nm is formed on the surface of the silicon oxide film 2 by, for example, a low pressure CVD method. Further thereon, a silicon oxide film 4 having a thickness of about 50 nm is formed as a buffer layer by a low pressure CVD method. Then, in FIG. 1B, arsenic ions 5 are ion-implanted into the polycrystalline silicon film 3 through the silicon oxide film 4 serving as the buffer layer, for example, with an implantation energy of 100 Kev and an implantation amount of 4 × 10 ¹⁵ / cm ² . Projection range of arsenic ions in the silicon oxide film 4
Since R _p is about 48 nm and the dispersion ΔR _p of the distribution is about 15 nm, the distribution peak occurs in the silicon oxide film 4 which is the buffer layer. Therefore, the distribution of arsenic ions in the polycrystalline silicon film 3 has the highest concentration at the boundary with the silicon oxide film 4, which is the buffer layer, and monotonically decreases along the depth direction.

Then, as shown in FIG. 1C, after removing the silicon oxide film 4 as the buffer layer with, for example, a hydrofluoric acid solution,
The pattern of the resist 6 is formed by using the existing photolithography method. Then, as shown in FIG. 1 (d),
For example, using the reactive ion etching method, the resist 6
The polycrystalline silicon film 3 is etched by using the as a mask.
At this time, the side surface 7 of the polycrystalline silicon film 3 is etched back in a region having a high arsenic concentration, but the arsenic ions in the polycrystalline silicon film 3 monotonically decrease along the depth direction. Since it has a concentration distribution, it has a shape with rounded corners 10 as shown in the figure.

Then, as shown in FIG. 1E, the resist 6 is removed, and a silicon oxide film 8 having a thickness of about 10 nm is formed on the silicon oxide film 2 and the polycrystalline silicon film 3 by using, for example, a low pressure CVD method. Further, the formed silicon oxide film 8
A polycrystalline silicon film 9 doped with phosphorus, for example, is grown on it and patterned so as to be an upper electrode.
Thereafter, for example, heat treatment is performed in a nitrogen atmosphere at 900 ° C. to activate phosphorus in the polycrystalline silicon film 9 and arsenic in the polycrystalline silicon film 3 to form a capacitor using the respective electrodes as electrodes as shown in the figure. .

For example, + 5V is applied to the polycrystalline silicon film 9 doped with phosphorus.
Is applied to keep the polycrystalline silicon film 3 at the ground potential 0 V,
A charge Q is stored in this capacitor. The potential difference is 5V,
Since the thickness of the silicon oxide film 8 as an insulating film is 10 nm,
The magnitude of the electric field E ₈ applied to the silicon oxide film 8 on the flat surface portion of the polycrystalline silicon film 3 is E ₈ = 5 MV / cm.

In this embodiment, since the shape of the corner 10 is rounded, the concentration of the electric field due to the charge Q is reduced. Therefore, the electric field E ₁₀ (MV / cm) smaller than the electric field E ₁₁ (MV / cm) and larger than 5 MV / cm described above in the conventional manufacturing method is applied to the corner 10 portion of the silicon oxide film 8. Since E ₁₀ <E ₁₁ , the structure of corner 10 is less likely to cause dielectric breakdown than corner 11.

FIG. 2 shows a rounded corner according to an embodiment of the present invention.
6 is a histogram showing the relationship between the voltage and the frequency of dielectric breakdown of a MIM capacitor having 10. The sample is a MIM capacitor having a total area of 1.0 mm ² facing the electrode plate and a total length of sides forming a corner portion of 173 mm.

The horizontal axis of the histogram is the positive voltage applied to the polycrystalline silicon film 8 when the polycrystalline silicon film 3 is grounded,
The breakdown voltage is shown in increments of 5V. The vertical axis is MI
It is the number of times the dielectric breakdown of M capacitors is converted into a percentage. Mode of dielectric breakdown voltage is 7.0 to 7.5
At the V level, the corner 11 shown in FIG. 4 (b) is shown.
The breakdown voltage is higher than that of a MIM capacitor having a.

It should be noted that in the above embodiment, the phosphorus-doped polycrystalline silicon film 9 is used as the upper electrode of the MIM capacitor, but the same effect can be obtained by using other electrode materials. Further, although the case of implanting arsenic ions into the polycrystalline silicon film 3 has been shown in the formation of the lower electrode, other impurities that can make the polycrystalline silicon film 3 an n-type or p-type semiconductor, for example, boron, phosphorus, antimony, etc. The same effect is obtained when implanting the ions. Further, although the case where the silicon oxide film by the low pressure CVD method is used as the insulating film is shown, the same applies to the case where another insulating film such as a silicon nitride film and its composite film and another insulating film forming method are used. Produce an effect.

Although the MIM capacitor has been described in the above embodiment, it is needless to say that the present invention can be applied to other uses.

〔The invention's effect〕

As described above, according to the present invention, the method for manufacturing a semiconductor device can be controlled by the buffer layer so that the concentration of impurities in the semiconductor layer has a monotonically decreasing distribution along the depth direction. Since the shape of the semiconductor layer after etching can be formed into a desired shape, for example,
By controlling the impurity concentration in the semiconductor layer, such as the polycrystalline silicon film that will be the lower electrode of the MIM capacitor, so that it monotonically decreases along the depth direction, for example, the shape after anisotropic dry etching is rounded. With the
It increases the breakdown voltage of the MIM capacitor, etc.
It is possible to obtain a method for manufacturing a semiconductor device having improved characteristics of the semiconductor device having the semiconductor layer.

[Brief description of drawings]

1 (a) to 1 (e) are process sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a distribution of dielectric breakdown voltage of an MIM capacitor formed according to the embodiment of the present invention. 3 (a) to 3 (d) are process cross-sectional views showing a conventional method for manufacturing a semiconductor device, and FIGS. 4 (a) and 4 (b) are distributions of the breakdown voltage of a conventional MIM capacitor. It is a histogram shown. In the figure, 3 is a polycrystalline silicon film, 4 is a silicon oxide film, 5 is arsenic ions, 7 is a side wall, and 10 is a corner. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having a layer doped with impurities and subjected to anisotropic dry etching, wherein the step of forming the layer includes the step of forming a semiconductor layer, and the step of forming the semiconductor layer. Forming a buffer layer thereover; introducing impurities through the buffer layer so that the impurity concentration in the semiconductor layer has a monotonically decreasing distribution along the depth direction; and removing the buffer layer And a step of anisotropically dry-etching the semiconductor layer according to a predetermined pattern.