JPH0834390B2 - Operational amplifier circuit - Google Patents

Description

The present invention relates to an operational amplifier circuit, and more particularly to an operational amplifier circuit suitable for an integrated circuit.

[Conventional technology]

Conventionally, various kinds of operational amplifier circuits of this type have been proposed. Among them, a folded cascode type operational amplifier circuit as shown in FIG. 2 is known.

This circuit comprises P-type transistors Q ₃₀ -Q ₃₂
And a differential pair circuit 1 _A which receives the first and _second input signals IN ₁ and IN ₂ and outputs the first and second differential signals, and N-type transistors Q ₃₃ and Q ₃₄ . Input the differential signal of
First cascode stage circuit 2 _G that outputs the cascode signal of
And a second N-type transistor Q ₃₇ , Q ₃₈ for inputting the second differential signal and outputting a second cascode signal.
Cascode stage circuit 2 _H and P-type transistors Q ₃₅ and Q ₃₆
A single-end switching circuit 3 _C which is provided with the first and second cascode signals and outputs a single-end signal
When, N-type transistor Q ₃₉ to be connected to the P-type transistor Q _40, and the output terminal T _O a drain by applying a bias voltage to the gate of connecting a drain receiving said single-ended signal to the gate and the output terminal T _O And an output circuit 5 _A for performing class A amplification operation, transistors Q _{25 to} Q ₂₉ , and a constant current source I ₂ are included in transistors Q ₃₀ , Q ₃₃ , Q ₃₄ , Q ₃₇ , Q ₃₈ , Q.
It has a configuration including a bias circuit 4 _A for supplying a bias voltage to ₃₉ .

It is known that this circuit has a wide input voltage range and good frequency characteristics.

[Problems to be Solved by the Invention]

In the conventional operational amplifier circuit described above, the output circuit 5 _A is configured to perform class A amplification operation, so the maximum value of the sink current (in the case of the polarity of the circuit shown in FIG. 2) to the load is that of the transistor Q ₃₉ . This is the bias current value. Therefore, in order to increase the operating speed of this operational amplifier circuit, it is necessary to set the bias current value of the transistor Q ₃₉ large, which inevitably increases the power consumption. As a result, there is a drawback that the operating speed is greatly limited when the allowable power consumption is small.

An object of the present invention is to provide an operational amplifier circuit capable of increasing power consumption efficiency and operating speed.

[Means for solving the problem]

The operational amplifier circuit of the present invention is provided with first and second transistors of one conductivity type for correspondingly inputting the first and second input signals to the gates, and outputs the first and second differential signals. A differential pair circuit; a first cascode stage circuit including a third transistor of reverse conductivity type, which inputs the second differential signal and outputs a first cascode signal; and a fourth cascode stage of reverse conductivity type. A second cascode stage circuit including a transistor for inputting the second differential signal and outputting a second cascode signal; and a reverse conductivity type fifth transistor for inputting the first differential signal. And a third cascode stage circuit for outputting a third cascode signal, and a fourth cascode circuit for inputting the first differential signal and outputting a fourth cascode signal Stage circuit and one conductivity type seventh transistor A fifth cascode stage circuit that receives the first cascode signal and outputs a fifth cascode signal; and a fourth cascode signal that receives the fourth cascode signal and includes an eighth transistor of one conductivity type. A sixth cascode stage circuit for outputting the cascode signal of, and an output circuit including ninth and tenth transistors of one conductivity type and reverse conductivity type for connecting both drains to an output terminal, and first and second The second and third cascode signals are input to the respective input terminals, and the first transistor is input to the ninth transistor.
And a first single-ended exchange circuit that supplies a first single-ended signal that supplies a current to the gate of the ninth transistor for a period corresponding to one half cycle of one cycle of the second input signal, The fifth and sixth cascode signals are input to the first and second input terminals, respectively, and the other half cycle of one cycle of the first and second input signals is input to the tenth transistor. And a second single-end exchange circuit that supplies a second single-end signal that supplies current to the gate of the tenth transistor for a corresponding period.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In this embodiment, the gate has first and second input signals I
The P-type first and second transistors Q ₇ and Q ₈ which input N ₁ and IN ₂ correspondingly and commonly connect the sources, and the sources and power supply terminals (voltage V _{P of} these transistors Q ₇ and Q ₈ ) ) A transistor with a transistor Q ₆ connected between
A differential pair circuit 1 from the drain of Q _7, Q ₈ and outputs the first and second differential signal, said second differential signal comprises a third transistor Q ₁₀ and the transistor Q ₉ of N-type _A cascode stage circuit 2 _A that inputs and outputs a first cascode signal;
_A second cascode stage which includes an N-type fourth transistor Q ₁₁ and a transistor Q ₉ which is shared with the first cascode stage circuit 2 _A and which inputs the second differential signal and outputs a second cascode signal. A circuit 2 _B , a third cascode stage circuit 2 _C having an N-type fifth transistor Q ₁₄ and a transistor Q ₁₆ and receiving the first differential signal and outputting a third cascode signal; Type cascode stage circuit having a sixth transistor Q ₁₅ and a third cascode stage circuit 2 _C and a transistor Q ₁₆ which is shared with the third type cascode stage circuit 2 _C and outputs the fourth cascode stage signal. 2 _D , a fifth cascode stage circuit 2 _E having a P-type seventh transistor Q ₁₈ and a transistor Q ₁₉ and receiving the first cascode signal and outputting a fifth cascode signal; 8th transistor
A sixth cascode stage circuit 2 _F having a Q ₂₁ and a transistor Q ₂₀ and receiving the fourth cascode signal and outputting a sixth cascode signal, and a P-type and N-type drain both connected to the output terminal T _0. Type ninth and tenth transistors Q ₂₄ , Q
An output circuit 5 having ₂₃ and P-type transistors Q ₁₂ , Q ₁₃
And a transistor Q ₂₄ for inputting the second and third cascode signals corresponding to the first and second input terminals, respectively.
_A first single-ended exchange circuit 3 _A for supplying a first single-ended signal for supplying a current to the gate of the transistor Q ₂₄ for a period corresponding to one half cycle of one cycle of the input signals IN ₁ and IN ₂ And transistors Q ₁₇ and Q ₂₂ for inputting the fifth and sixth cascode signals corresponding to the first and second input terminals, respectively, and inputting the input signals IN ₁ and IN ₂ to the transistor Q ₂₃ for one cycle. the other half-cycle and the corresponding period by a second single-ended exchange circuit to the gate of the second single-ended signal transistors Q ₂₃ to flow a current 3 to _B of out, N-type transistors Q ₁ to Q _4, Transistor with P-type transistor Q ₅ and reverse current source I _{1
Q 6, Q 9 ~Q 11,} Q 14 to ~Q _16, Q ₁₈ ~Q ₂₁ is configured to have a bias circuit 4 which supplies a bias voltage.

The operation when the input signals IN ₁ and IN ₂ are input in this configuration will be described.

The differential output of the differential pair circuit 1, that is, the first and second differential signals have two signal paths and are transmitted to the output circuit 5. One of the signal paths is the transistor Q ₁₁ , Q. Input to the second and third cascode stage circuits 2 _B and 2 _C having ₁₄ and their outputs, that is, the second and third cascode signals, are converted into the first single-ended signal by the transistors Q ₁₂ and Q ₁₃ . Then, the gate of the transistor Q ₂₄ of the output circuit 5 is driven.

The other signal path is input to the first and fourth cascode stage circuits 2 _A and 2 _D having transistors Q ₁₀ and Q ₁₅ .
The output, that is, the first and fourth cascode signals are input to the fifth and sixth cascode stage circuits 2 _E and 2 _{F including the} transistors Q ₁₈ and Q ₂₁ , and the output thereof, that is, the fifth and sixth cascode signals. Is converted into a second single-ended signal by the transistors Q ₁₇ and Q ₂₂ , and the gate of the transistor Q ₂₃ of the output circuit 5 is driven.

Therefore, the output circuit 5 performs a so-called push-pull operation, which can improve the efficiency of power consumption and can operate at high speed in both positive and negative cycles with respect to the load.

〔The invention's effect〕

As described above, the present invention has an effect that power consumption can be improved and high-speed operation can be achieved by configuring the output circuit to perform push-pull operation. Further, since the cascode circuit has a multi-stage configuration, it has an effect of being stable against an oscillation phenomenon.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional operational amplifier circuit. 1,1 _A: Differential pair circuit, 2 _A to 2 _H: Cascode stage circuit, 3 _A
〜 3 _C …… Single-end exchange circuit, 4,4 _A …… Bias circuit, 5,5 _A …… Output circuit, I _{1 to} I ₂ …… Constant current source, Q _{1 to} Q ₄₀
... Transistor.

Claims (1)

[Claims] 1. A differential pair having first and second transistors of one conductivity type for receiving first and second input signals respectively corresponding to gates and outputting first and second differential signals. A circuit, a first cascode stage circuit having a reverse-conductivity type third transistor for inputting the second differential signal and outputting a first cascode signal, and a reverse-conductivity type fourth transistor. A second cascode stage circuit for inputting the second differential signal and outputting a second cascode signal; and a fifth transistor of the reverse conductivity type, the third differential circuit for inputting the first differential signal. A third cascode stage circuit for outputting the cascode signal, and a fourth cascode stage circuit for outputting the fourth cascode signal, the sixth cascode circuit having a sixth transistor of the reverse conductivity type and receiving the first differential signal. And a seventh-type transistor of one conductivity type 5 Type 1 cascode signal
A fifth cascode stage circuit which outputs the cascode signal of, and a sixth cascode stage circuit which includes an eighth transistor of one conductivity type and which inputs the fourth cascode signal and outputs a sixth cascode signal, An output circuit including ninth and tenth transistors of one conductivity type and opposite conductivity type, both drains of which are connected to the output terminal, and the second and third input circuits corresponding to the first and second input terminals, respectively. A cascode signal is input to the ninth transistor, and a first single-ended signal is supplied to the ninth transistor for a period corresponding to one half cycle of one cycle of the first and second input signals. And a first single-end exchange circuit for supplying to the gate of, and the fifth and sixth cascode signals corresponding to the first and second input terminals, respectively, and input to the tenth transistor. 1 of the first and second input signals
An operational amplifier having a second single-ended conversion circuit for supplying a second single-ended signal for supplying a current only to a period corresponding to the other half cycle of the cycle to the gate of the tenth transistor. circuit.