JPH0834416B2 - Hysteresis comparator circuit - Google Patents

Description

The present invention relates to a hysteresis comparator circuit.

[Conventional technology]

As shown in FIG. 2, the hysteresis comparator circuit in the conventional analog circuit is an operational amplifier 1 _{a in} which the negative phase input terminal is connected to the input terminal 5 and the output terminal is connected to the output terminal 6.
When, a resistor R ₄ to be inserted between the output terminal and the inverting input terminal of the operational amplifier 1 _a, was composed of the resistor R ₃ Metropolitan to the positive phase input terminal of the operational amplifier 1 _a is inserted between the ground terminal .

[Problems to be Solved by the Invention]

Since the above-mentioned conventional hysteresis comparator circuit is an analog circuit, for example, it is used for removing the unwanted wave component from the input signal by the filter, judging the filter output signal level, and converting it to the data of "1" and "0". In the comparator circuit, when the filter, that is, the roll-off filter is a switched capacitor filter, a smoothing filter for further removing a clock component included in the output of the switched capacitor filter needs to be placed in front of the hysteresis comparator circuit. In particular, when it is realized on a semiconductor integrated circuit, an RC active filter configuration is generally used, but at this time, there is a disadvantage that the area occupied by the resistor and the capacitor becomes large. Further, since it is necessary to design the resistors and capacitors in consideration of variations from the respective design values, there is a drawback that the number of designing steps is large.

[Means for solving the problem]

The hysteresis comparator circuit of the present invention includes a first switch, one end of which is connected to an input terminal and the other end of which is connected to one electrode of a capacitor, and which is driven by a first clock. An operational amplifier having a phase input terminal connected to the other electrode of the capacitor and outputting a comparison signal corresponding to a potential difference between the positive phase input terminal and the negative phase input terminal from the output terminal; and one end having the first switch. A second non-overlapping second clock connected to the other end of the first clock
In response to the second switch driven by the clock, the third switch inserted between the negative phase input terminal and the output terminal of the operational amplifier and driven by the second clock, and the supply of the comparison signal. A sample hold circuit including an even number of cascaded inverters that output a delay comparison signal and a flip-flop that holds the delay comparison signal in synchronization with the first clock and outputs a comparator output signal; And a resistance voltage dividing circuit for dividing the comparator output signal by a predetermined voltage dividing ratio to generate a voltage dividing signal to be supplied to the other end of the second switch.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram of an embodiment of the present invention.

As shown in FIG. ₁ , a first switch S ₁ driven by a _first clock Φ ₁ having one end connected to the input terminal 5, and
A second switch S ₂ driven at a _second clock Φ ₂ whose _one end is connected to the other end of the switch S ₁ and which does not overlap with the clock Φ _1, and one electrode serving as a connection node of the switches S ₁ and S _2. A capacitor C ₁ connected thereto, an operational amplifier 1 having a negative-phase input terminal “−” connected to the other electrode of the capacitor C ₁ and a positive-phase input terminal “+” connected to a ground terminal, and an inverse of the operational amplifier 1. A third switch S ₃ inserted between the phase input end and the output end and driven by the clock Φ ₂ , and an even number of first cascaded first ends whose input end is connected to the output end of the operational amplifier 1. an inverter group 2 _a made from the inverter 2, the flip-flop 3 which input is driven by the inverted clock ₁ is connected to the end of the output terminal of the inverter group 2 _a clock [Phi _1, input flip-flop 3 Is connected to the output terminal of and the output terminal is connected to the output terminal 6. A second inverter 4, the resistor R ₁ and the other end one end connected to the output terminal of the inverter 4 connected partial intermediate pressure point to the ground terminal is connected to the other end of the switch S ₂
And a voltage dividing resistor made of R ₂ . Switch S ₁
The circuit consisting of ~ S ₃ , the capacitor C ₁ and the operational amplifier 1 is a comparator circuit, but the timing is set so that the activation periods "1" of the complementary clocks φ ₁ and φ ₂ do not overlap each other. The deactivation period "0", that is, the slit, is provided above both. Switch S _{1 in the} slit above
To S ₃ are all turned off output of the operational amplifier 1 becomes an open state. Therefore, the output of the operational amplifier 1 is not normally output during the slit, and as a result, a malfunction output as a comparator circuit is likely to occur.

The inverter group 2a including the inverters 2 connected in cascade after the comparator circuit and the flip-flop circuit 3 constitute a hold circuit for sampling and holding the value of the input signal from the input terminal 5 when the clock φ ₁ is "1". The operation will be described. The output waveform of the operational amplifier 1 is delayed by the inverter group 2a and the flip-flop 3 outputs the clock φ.
By latching the _first inverted clock phi _1, negligible malfunction of the comparator circuit of the slits since put preparative output data in the normal non the slit period in the flip-flop 3.

If the roll-off filter in the preceding stage of the comparator circuit is a switched capacitor filter, the filter output waveform is a stepped waveform sampled and held at clock intervals, and the clock of each of these hysteresis comparator circuit and switched capacitor filter is Can be shared.

Therefore, if the inverter 4 is added to this hold circuit and the output terminal 6 is connected, an inverse phase comparator circuit is formed between the input terminal 5 and the output terminal 6. Where switch S ₂
Since the reference voltage value supplied to the operational amplifier 1 via is determined by the voltage division ratio of the resistors R ₁ and R ₂ of the voltage dividing resistor, the output voltage of the inverter 4 is V _OH (output voltage at high level).
And V _OL (output voltage at low level), the hysteresis width V _TH is expressed by equation (1).

Therefore, the hysteresis width V _TH expressed by the equation (1) is equivalent to the hysteresis width of the conventional hysteresis comparator circuit of FIG. 2 described above.

〔The invention's effect〕

As described above, the present invention does not require a smoothing filter when implementing a circuit on a semiconductor integrated circuit by using a switched capacitor type hysteresis comparator circuit from an analog circuit, and therefore,
This has the effect of reducing the semiconductor chip size.

Further, since it is not necessary to pay special consideration to the variation of the element in the design, there is an effect that the design period can be shortened.

In the embodiment of the present invention shown in FIG. 1, the inverter 4 is connected between the output of the flip-flop 3 and the output terminal 6, but the same operation is expected even if the inverter 4 is omitted. it can.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional hysteresis comparator circuit. 1,1 _a …… Operational amplifier, 2,4 …… Inverter, 2 _a …… Inverter group, 3 …… Flip-flop, 5 …… Input terminal,
6 ...... output terminal, C ₁ ...... capacitor, R ₁ to R ₄ ...... resistance,
S _{1 to} S ₃ ...... Switch, Φ ₁ , ₁ , Φ ₂ ...... Clock.

Claims (1)

[Claims] 1. A first switch, one end of which is connected to an input terminal and the other end of which is connected to one electrode of a capacitor, and which is driven by a first clock; and a positive-phase input end is a first power supply and a negative-phase input end. An operational amplifier connected to the other electrode of the capacitor to output a comparison signal corresponding to the potential difference between the positive-phase and negative-phase input terminals from the output terminal; and the other end of the first switch. And a second switch driven by a second clock that does not overlap with the first clock and is inserted between the negative-phase input terminal and the output terminal of the operational amplifier and driven by the second clock. A third switch, a cascaded even number of inverters that output a delayed comparison signal in response to the supply of the comparison signal, and a comparator output signal that holds the delayed comparison signal in synchronization with the first clock. A sample-hold circuit including a flip-flop that outputs a voltage, and a resistance voltage dividing circuit that divides the comparator output signal at a predetermined voltage dividing ratio to generate a voltage dividing signal to be supplied to the other end of the second switch. A hysteresis comparator circuit characterized by the above.