JPH0834420B2 - Power-on reset circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a power-on reset circuit for preventing a malfunction when a digital circuit is powered on and off.

[Conventional technology]

An example of a conventional power-on reset circuit is shown in FIG. That is, conventionally, the power supply V _{CC is connected} to the resistor R ₁₁ and the capacitor.
The circuit configuration is such that a series circuit of C ₁₁ is connected, and a diode D ₂₁ is connected in parallel to the resistor R ₁₁ , and the charging voltage of the capacitor C ₁₁ is output from terminal 1 and is used as the power-on reset signal V _0. Supply to the integrated circuit element 2. The integrated circuit element 2 is supplied with power for operation by turning on the power supply V _CC , but remains in the reset state until a power-on / reset signal higher than the reset release voltage V _B is applied, and the reset release voltage V Reset is released by the power-on reset signal of _B or higher, and normal operation is performed. Resistance R ₁₁
May be incorporated in the integrated circuit element 2.

In the above-mentioned conventional circuit, after the power supply V _CC is turned on, the capacitor C ₁₁ is charged through the resistor R _11, and when the charging voltage of the capacitor C ₁₁ reaches a predetermined level V _B , the reset of the integrated circuit element 2 is released. . Therefore, as shown in FIG. 6 (a), when the voltage rise at the time of power-on is stepwise, after the power-on as shown in FIG. 6 (b), the resistor R ₁₁ and the capacitor C are turned on.
Power on after a certain time t determined by the size of ₁₁
The reset signal V ₀ can exceed the predetermined level of the reset release voltage V _B to release the reset.

On the other hand, the integrated circuit element 2 is supplied with a voltage equal to or higher than a predetermined allowable operating voltage V _A immediately after the power is turned on. Therefore,
The integrated circuit element 2 will be released from reset after a given time t after the application of the allowable operating voltage V _A. When the power is turned off, the electric charge of the capacitor C ₁₁ is immediately discharged through the diode D _21, so that the integrated circuit element 2 is immediately reset and no malfunction occurs.

[Problems to be solved by the invention]

However, in such a conventional power-on reset circuit, when the voltage rise and fall of the power supply V _CC has a slope as shown in FIG. 7 (a), the power-on reset signal V ₀ is the power source as shown in Fig. 7 (b)
The reset release voltage V _B may be reached before the voltage of V _CC reaches the allowable operating voltage V _A. In this case, during the period x shown in FIG. 7B, the integrated circuit element 2 is released from reset while being supplied with the power supply voltage equal to or lower than the allowable operating voltage V _A, which may cause a malfunction. The same applies to the case of power off. That is, as shown in FIG. 7 (b), even if the voltage of the power supply V _CC falls below the allowable operating voltage V _A , it is not immediately reset, but reset after the lapse of the period x, which may cause a malfunction.

As described above, the conventional power-on / reset circuit shown in FIG. 5 sometimes fails to perform its purpose due to a malfunction when the power is turned on and off.

An object of the present invention is to solve the above-mentioned conventional drawbacks, to enable reset to be released after a certain period of time from when the power supply voltage reaches the allowable operating voltage of the integrated circuit, and when the power supply voltage falls below the allowable operating voltage. Is to provide a power-on reset circuit that can be reset immediately.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a collector of an NPN transistor to a cathode of a first diode and an anode of a second voltage regulator diode via a second resistor. Connection, the anode of the first diode is connected to one end of the capacitor and the cathode of the second diode, the other end of the capacitor is connected to the positive terminal of the DC voltage source, the anode of the second diode is grounded, The base of the NPN transistor is connected to the anode of the first voltage regulator diode via the first resistor, the cathode of the first voltage regulator diode is connected to the positive terminal of the DC voltage source, and the emitter of the NPN transistor is grounded. Then, connect the emitter of the PNP transistor to the positive terminal of the DC voltage source, connect the base of the PNP transistor to the cathode of the second voltage regulator diode, and connect the PNP transistor. Connect the collector of the output to one end of the output resistor and the output terminal,
The other end of the output resistor is grounded.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

 FIG. 1 is a circuit diagram showing an embodiment of the present invention.

As shown in FIG. 1, this power-on reset circuit includes a circuit composed of a first constant voltage diode ZD ₁ , a first resistor R ₁ and an NPN transistor Q ₁ , a capacitor C ₁ and a first diode. Using a circuit composed of D ₁ and a second resistor R ₂ , a circuit composed of PNP transistor Q ₂ and an output resistor R ₃ , a second constant voltage diode ZD ₂ and a second diode D _2. It is configured.

That is, between the power supply V _CC and ground, a capacitor C ₁
And the first diode D ₁ , the second resistor R ₂ and the collector-emitter series connection circuit of the NPN transistor Q ₁ are connected.
The base of the transistor Q ₁ is connected to the power supply V _CC through the first resistor R ₁ and the first constant voltage diode ZD ₁ . The sum of the Zener voltage V _{Z1 of} the first constant voltage diode ZD ₁ and the base-emitter voltage V _BE1 of the transistor Q ₁ is set to be equal to the allowable operating voltage V _A. Therefore,
Transistor Q ₁ is the power supply V _CC allowable operating voltage V voltage is constant of
When it becomes _A or higher, it is turned on.

In this embodiment, the transistor Q ₁ , the resistor R ₁ , and the constant voltage diode ZD ₁ form a first switching circuit. The capacitor C ₁ , the first diode D ₁ , and the second resistor R ₂ form a charging circuit. In addition, the power supply V _CC has a PNP transistor
The emitter of Q ₂ is connected, and the base of transistor Q ₂ is connected to diode D ₁ and resistor R ₁ via the _second constant voltage diode ZD _2.
Connect to the connection point with ₂ . And the transistor Q ₂ is
Connect the collector to ground through output resistor R ₃ . Also, as the discharging circuit of the capacitor C ₁ , the second diode
The cathode of D ₂ is connected to the capacitor C ₁ and the anode is grounded. The transistor Q ₂ is the second switching circuit. The second switching circuit, namely the transistor Q ₂
Is the charging voltage V _C of the capacitor C ₁ , the zener voltage V _{ZZ of the second} constant voltage diode ZD ₂ and the base of the transistor Q ₂ .
It is in the OFF state until it reaches a value obtained by subtracting the forward voltage V _D1 of the first diode D ₁ from the sum of the voltage between the emitters V _BE2, and is in the ON state at the above voltage or more. The diode D ₁ has a polarity that prevents the charge of the capacitor C _{1 from} flowing as a base current of the transistor Q ₂ when the power is cut off. Further, since the second switching circuit and the output resistance R ₃ are connected in series and the power-on reset signal V ₀ is output from one end of the output resistance R ₃ through the output terminal 1, the power-on reset signal is High level when the second switching circuit is in the ON state.

It should be noted that the output from the output terminal 1 is supplied to the integrated circuit element (not shown) as the power-on reset signal V ₀ , and the operating power is supplied to the integrated circuit element by turning on the power supply V _CC . This is similar to the case of FIG.

Next, the operation of this embodiment will be described with reference to FIG. 1 and FIG. In FIG. 2, (a) shows the voltage of the power supply V _CC , (b) shows the charging voltage V _{C of} the capacitor C ₁ ,
(C) is a time chart showing the power-on reset signal V ₀ .

 First, the power-on time will be described.

When the power supply is turned on, the voltage of the power supply V _CC rises as shown in FIG. 2 (a), and when it reaches a certain allowable operating voltage V _A , the first
Voltage regulator diode ZD ₁ is turned on and transistor Q ₁ is turned on.
To do. That is, the first switching circuit is turned on. This starts charging capacitor C ₁
The charging voltage V _C of C ₁ rises as shown in FIG. 2 (b). This voltage is the Zener voltage V _{ZZ of the second} constant voltage diode ZD ₂ and the base-emitter voltage V of the transistor Q _2.
When it reaches a constant value, which is the value obtained by subtracting the forward voltage V _D1 of the first diode D ₁ from the sum of _BE2 , the transistor Q ₂ or the second switching circuit is turned on, and the power supply V _CC outputs the output resistance R
₃ and a high level power-on reset signal V ₀ as shown in FIG. 2 (c) is output from the output terminal 1. The voltage on capacitor C ₁ drives the second switching circuit
The delay time t until turning on depends on the capacity of the capacitor C ₁ and the resistance value of the resistor R ₂ and the Zener voltage V _{ZZ of the second} voltage regulator diode ZD ₂ depending on the rising speed of the power supply V _CC. . This delay time is minimum when the power supply V _CC is applied stepwise. Therefore, if this minimum delay time t ₀ is set to a predetermined value, a delay time of t ₀ or more can be obtained. That is, since the integrated circuit element (not shown) is reliably reset for a certain delay time t ₀ after being supplied with a voltage equal to or higher than the allowable operating voltage V _A, it does not malfunction.

 Next, the time when the power is turned off will be described.

When the voltage of the power supply V _CC drops to the allowable operating voltage V _A as shown in FIG. 2 (a) when the power is turned off, the transistor Q ₁ is turned off and the base current of the transistor Q ₂ is cut off. To turn off. Therefore, power on
The reset signal V ₀ immediately goes to a low level as shown in FIG. 2 (c) to reset the integrated circuit element (not shown). As a result, malfunction of the integrated circuit device is completely prevented. On the other hand, the charging voltage V _C of the capacitor C ₁ is equal to that of the power source V _CC V _ZZ + V _BE2 -V _D1 -V _D2 (V _D2 is the second diode D ₂
Charge voltage is maintained because there is no discharge loop, and then the charge of the capacitor C ₁ is discharged through the diode D ₂ and becomes 0 as shown in FIG. 2 (b). . FIG. 2D shows the ON / OFF states of the transistors Q ₁ and Q ₂ during the above-mentioned operation.

FIG. 3 is a modification of the above embodiment, in which resistors R ₄ and R ₅ are respectively provided between the base and emitter of the transistors Q ₁ and Q ₂ of FIG.
Is a circuit that is connected. In this case, the leakage current of the first constant voltage diode ZD ₁ , the second constant voltage diode ZD ₂ , or the transistor Q ₁ prevents the transistors Q ₁ and Q ₂ from turning on, and the switching operation is more reliable. There are advantages to be made.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. In this embodiment, the resistor R ₆ is inserted in series with the transistor Q ₂ and the resistor R ₃ shown in FIG. In this case, the level of the output terminal 1 after reset release ensures that the integrated circuit device (not shown) has a resistor R ₆ to ensure the reset release voltage level.
By selecting, the power consumption of the transistor Q ₂ after reset release can be reduced.

〔The invention's effect〕

As described above, in the present invention, charging of the series connection circuit of the capacitor and the resistor is started by the first switching circuit in which the power source is turned on at the allowable operating voltage or higher, and when the capacitor is charged to the constant voltage or higher, the second switching circuit is started. By turning on the switching circuit of, and connecting the series connection circuit of the second switching circuit and the output resistor between the power supply and ground, when the power supply is turned on, after the power supply reaches the allowable operating voltage, The reset can be reliably continued for a time or longer, and when the power is turned off, the reset can be immediately performed when the voltage drops to the allowable operating voltage. That is, there is an effect that the malfunction of the digital circuit can be surely prevented when the power is turned on and off.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a time chart showing waveforms and operations of respective parts of the first embodiment, and FIG. 3 is a modification of the first embodiment. FIG. 4 is a circuit diagram showing a second embodiment of the present invention, FIG. 5 is a circuit diagram showing a conventional circuit, and FIG. 6 is a step-like increase / decrease in voltage at power-on / off. FIG. 7 is a time chart for explaining the operation of the conventional circuit in the case of, and FIG. 7 is the same time chart when the voltage rise and fall have a slope. 1 …… Output terminal 2 …… Integrated circuit element Q ₁ …… NPN transistor Q ₂ …… PNP transistor ZD ₁ , ZD ₂ …… Constant voltage diode D ₁ , D ₂ …… Diode C ₁ …… Capacitor R _{1 to} R ₆ …… Resistor V _CC …… Power supply V _C …… Capacitor charging voltage V ₀ …… Power-on reset signal V _A …… Permissible operating voltage V _B …… Reset release voltage V _Z1 , V _Z2 …… Constant voltage diode Zener voltage V _D1 , V _D2 …… Diode forward voltage V _BE1 , V _BE2 …… Transistor base-emitter voltage

Claims (3)

[Claims] 1. A collector of an NPN transistor is connected to a cathode of a first diode and an anode of a second constant voltage diode via a second resistor, and an anode of the first diode is connected to one end of a capacitor and a second Connect to the cathode of the diode, connect the other end of the capacitor to the positive terminal of the DC voltage source, ground the anode of the second diode, and
The base of the N-transistor is connected to the anode of the first voltage regulator diode through the first resistor, the cathode of the first voltage regulator diode is connected to the positive terminal of the DC voltage source, and NP
The emitter of the N transistor is grounded, the emitter of the PNP transistor is connected to the positive terminal of the DC voltage source, the base of the PNP transistor is connected to the cathode of the second voltage regulator diode, and the collector of the PNP transistor is connected to one end of the output resistor. And a power-on reset circuit, which is connected to the output terminal and the other end of the output resistor is grounded. 2. The power according to claim 1, wherein a third resistor is connected between the base and the emitter of the NPN transistor, and a fourth resistor is connected between the emitter and the base of the PNP transistor. On-reset circuit. 3. A power-on reset circuit according to claim 2, wherein a fifth resistor is connected between the collector and the output terminal of the PNP transistor.