JPH0834456B2 - Time division multiplexer - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a time division multiplex device in a time division multiplex communication system in which three or more time division multiplex devices are coupled to a plurality of high speed digital lines. It relates to a configuration related to the relay operation.

[Technical background of the invention]

FIG. 5 is a block diagram showing an example of a conventional time division multiplex communication system of this type. The time division multiplexer 1A is connected to the time division multiplexer 1B, and the time division multiplexer 1B is connected to the time division multiplexer 1C via high-speed digital lines. Further, each of the time division multiplexers 1A, 1B and 1C is connected to a plurality of terminal devices 2. The broken line from each time division multiplexer indicates a logical data parse and does not indicate a physical line. In such a time division multiplex communication system, a time division multiplex device
An operation in which 1A and the time division multiplexing apparatus 1C transmit and receive data via the time division multiplexing apparatus 1B is called relay.

FIG. 6 shows a structural example of a frame for controlling a data communication partner in the time division multiplex communication system shown in FIG. Reference numerals 3A, 3B and 3C are frames for controlling each time division multiplexer, and one frame is composed of n channels. Here, the frame 3A of the time division multiplexer 1A
Paying attention to, a channel is written as B between the corresponding terminal device connected to the time division multiplexer 1A and the corresponding terminal device connected to the time division multiplexer 1B using the channel. It indicates that the communication is performed, and the C in the channel in the frame is the corresponding terminal device connected to the time division multiplexer 1A and the corresponding terminal connected to the time division multiplexer 1C using the channel. 2 shows that the time division multiplexing apparatus 1B is relayed between the terminal devices of FIG. The same applies to the other frames 3B and 3C.

FIG. 7 is a block diagram showing a detailed example of a conventional time division multiplexing apparatus of this type. Reference numeral 4 is a system control unit that controls the entire time division multiplexing apparatus, and particularly controls a plurality of time division multiplexing and relay control units 5. A plurality of low speed side terminal interfaces (hereinafter referred to as ports) 8 are connected to each of the time division multiplexing and relay control units 5 via a bus 6 and a bus 7. Although not shown, a terminal device is connected to each port 8. Further, each time division multiplexing and relay control unit 5 is connected to high speed lines 101 and 102 via a high speed line interface 9, respectively. Further, the time division multiplexing and relay control unit 5 is connected to each other by a bus 11. The high-speed line interface 9 uses the time-division multiplexing and data from the relay control unit 5 and the high-speed line 101 (or 10).
It has the function of taking a frame structure and electrical interface with the data of 2).

Conventionally, when performing data transmission / reception with a terminal device connected to its own time division multiplexing apparatus via a high speed line 101 (or 102), the time division multiplexing and relay control unit 5 uses a bus 6
If the high speed line 101 (or 102) is connected to the corresponding port 8 via the (or bus 7) to communicate with the terminal device and relay between the high speed lines 101 and 102, the bus 1
This is done by connecting high-speed lines 101 and 102 via 1. Therefore, the time division multiplexing / relay control unit 5 controls the switching of the internal bus to be used depending on whether the data is transmitted / received to / from the port 8 or relayed.

[Problems of background technology]

In the time division multiplexing apparatus which constitutes the conventional time division multiplexing communication system as described above, the time division multiplexing and relay control unit 5 is selected depending on whether data is transmitted / received to / from the terminal device connected to itself or relayed between the lines. Internal bus used by (bus 6,7,
It is necessary to control the switching of 11), and the time division multiplexing and the relay procedure of the relay control unit 5 are complicated. Further, in the example of FIG. 7, the case where two high-speed lines 101 and 102 are supported is shown. However, if more n lines are supported and relay between all lines is possible, each time division multiplex is possible. The bus 11 that connects the conversion and relay control units 5 is n! / {(N-2)! 2!}.
This is necessary, and the hardware of the time division multiplexing and relay control unit 5 has a drawback that it is very complicated. Moreover, since the number of buses 11 connecting the time division multiplexing and relay control units 5 changes depending on the number of high-speed lines to be supported, the structure of the time division multiplexing and relay control units 5 becomes different each time. However, its structure is not constant. Therefore, it is very difficult to expand the system by arbitrarily increasing the number of high speed lines to be supported.

[Object of the Invention]

In view of the above-described drawbacks, an object of the present invention is to provide a time division multiplexing apparatus that can simplify a control unit that switches between data transmission / reception between terminal devices and relay operation between lines and improve the expandability of supported lines. To provide.

[Outline of Invention]

In the present invention, the first bus, the second bus, and the first bus
And a data input system that is connected to the bus and the terminal device and that receives data coming through the first bus and sends it to the terminal device, and data sent from the terminal device through the first bus. And a plurality of ports each having a data output system for transmitting the data, and a data input system for connecting to the second bus and the terminal device and for receiving data coming through the second bus and transmitting the data to the terminal device. And a plurality of ports each having a data output system for sending data sent from the terminal device via the second bus, a memory for storing data, and a data output system coming via the first bus. A virtual port having a data input system for taking in data and writing it in the memory, and a data output system for reading out the data stored in the memory and sending it out through the second bus. And the time-division-multiplexed data coming from the first high-speed line are taken in through the high-speed line interface, and the data of each channel related to the multiplexing is connected to the first bus of the corresponding address or the above-mentioned port. A first time division multiplexing control unit having a data write system for writing to a virtual port via the first bus, and data from the port or the virtual port connected to the second bus. Read through the bus, the second
Second time division multiplexing control unit having a data reading system which is arranged in a channel related to multiplexing corresponding to an address of a port or a virtual port connected to the bus and is transmitted to a second high speed line through a high speed interface. And these first and second
In the time division multiplexing control unit, the correspondence relationship between each channel related to multiplexing used by the data writing system and the data reading system and the address of the port or the virtual port is arbitrarily set, and The above-mentioned object is achieved by including a system control unit that performs control.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the time division multiplexing apparatus of the present invention. High-speed line 111 is high-speed interface 1
21, the line 201, the time division multiplexing control unit 131 and the bus 141 are connected to the plurality of ports 15 (R), and the high speed line 112 includes a high speed interface 122, a line 202, a time division multiplexing control unit 132, and Multiple ports 15 via bus 142
(S) is connected. The division / multiplexing control units 131 and 132 are controlled via the line 200 by the system control unit 16 that controls the entire apparatus. In addition, a virtual port 17 having a relay function is connected to the buses 141 and 142 in common. In this example, the time division multiplexer supports the second round of the high speed lines 111 and 112.

FIG. 2 shows the time division multiplexing control unit 131 (132) shown in FIG.
Is also the same). The time division multiplexing control unit uses the read port address generation unit 18R
And a data buffer 19R for reading, a port address generator 18W for writing, and a data buffer 1 for writing
It consists of 9W. At the time of reading, the port address generator 18R outputs the read signal RD and outputs the address of the port from which data is to be read to the address bus A. Each port 15 shown in FIG. 1 has a unique address, and if the read signal RD is output, the port 15 corresponding to the address output from the port address generation unit 18R will receive the data. It is sent to the data buffer 19R of the time division multiplexing control unit via the data bus D.
The data once held in the data buffer 19R is then transmitted to the high speed line via the high speed line interface.

When writing, the port address generator 18W outputs the write signal WR and the port 15
The address of is output to the address bus A. If the write signal WR is output, the port 15 of the corresponding address fetches data from the data buffer 19W of the time division multiplexing control unit via the data bus D. The data transmitted through the high speed line is written in the data buffer 19W through the high speed line interface. As described above, the time division multiplexing control unit 131
The time-division-multiplexed data coming from 01 from the high-speed line 111 is taken in via the high-speed line interface 121, and the data of each channel related to the multiplexing is connected to the bus 141 at the corresponding address port 15 (R) or virtual port 17 It has a port address generator 18W and a data buffer 19W which are data write systems for writing via a bus 141 which is a first bus. In addition, the time division multiplexing control unit 132 reads data from the port 15 (S) or virtual port 17 connected to the bus 142 via the bus 142 that is the second bus, and then reads the data from the port 15 (S) or virtual port. A port address generation unit 18R and a data buffer 1 which are data read systems arranged in channels related to multiplexing corresponding to the address of the port 17 and transmitting from the line 202 to the high speed line 112 via the high speed interface 122.
With 9R. The port address generating unit 18R and the data buffer 19R, which are the data reading system of the time division multiplexing control unit 131, read the data from the port 15 (R) connected to the bus 141, and the time division multiplexing control unit. Port address generator 18W and data buffer 1 for 132 data write system
9W writes data to the port 15 (S) connected to the bus 142.

FIG. 3 is a block diagram showing a detailed example of the port 15 shown in FIG. The port includes a write port address decode unit 20W, a write data buffer 21W, a read port address decode unit 20R, and a read data buffer 21R. When writing (when outputting write signal WR) Port address decode block
20W is the address of the write destination port (address bus A
If the above address is the self address, the data on the data bus D is fetched into the buffer 21W, and the fetched data is sent to the terminal device (not shown). When reading (when the read signal RD is output), the read port address decoding unit 20R reads the read data buffer 21R when the read destination address (on the address bus A) is the address of its own port. Although not shown in the figure, the data from the terminal device is sent to the data bus D. As mentioned above, port 15 (R)
A port address decoding unit 20W and a data buffer 21W, which are connected to the bus 141 and the terminal device, and are a data input system that captures data that arrives via the bus 141 that is the first bus and sends the data to the terminal device. It is provided with a port address decoding unit 20R which is a data output system for sending out data sent from the bus via a bus 141 which is a first bus, and a data buffer 21R. Also, port 15 (S)
Is connected to the bus 142 and the terminal device, and includes a port address decoding unit 20W and a data buffer 21W, which is a data input system for capturing data coming through the second bus 142 and sending it to the terminal device. Port address decoding unit 20R which is a data output system for transmitting data sent from the terminal device via the bus 142 which is the second bus
And a data buffer 21R.

FIG. 4 is a block diagram showing a detailed example of the virtual port 17 shown in FIG. The virtual port 17 is composed of address decoding blocks 22W and 22R for writing and reading, a memory access control unit 23 and a memory (RAM) 24. At the time of writing (when the write signal WR is output), the write address decoding unit 22W sets the memory access control unit 23 to the write mode when the write destination address on the data bus A is the address of its own port. To do. As a result, the memory access control unit 23 writes the data on the data bus D to the address of the memory 24 designated by the address bus A. Next, at the time of reading (when the read signal RD is output), the read address decoding unit 22R sets the memory access control unit 23 in the read mode when the address on the address bus A is its own address. This allows
The memory access control unit 23 reads the data stored in the address portion of the memory 24 designated by the address bus A and sends it to the data bus D. As described above, when the virtual port 17 is a data input system that captures data that arrives via the bus 141 that is the first bus and writes it to the memory 24, the address decode unit 22W, the memory access control unit 23, and the memory 24 It is provided with an address decoding unit 22R and a memory access control unit 23, which are data output systems for reading out stored data and sending it out via a bus 142 which is a second bus.

Next, the operation of this embodiment will be described. First, the relationship between the channel number and the port address in the frame that controls the time division multiplexer will be described. N in the frame
There is a channel, and the numbers are numbered from the beginning to No. 1, No. 2, ... N. For example, when passing the data of the first channel of the frame passed from the high-speed line interface 121 to the port of the address a, the time division multiplexing control unit 131 outputs the address a to the bus 141 at the timing of the first channel, At the same time, the data is passed to the relevant port.
The same applies to the channel numbers 2, 3, ... N, which are associated with the respective port addresses. The correspondence between the channel number and the port address is from the system control unit 16 to the port address generation unit 18R of the time division multiplexing control unit shown in FIG.
It is set to 18W, and this correspondence can be changed according to demand. Therefore, the time division multiplexing control unit 131 (or 132)
The data of each channel sent via (2) is sent to the corresponding port 15 in a time division manner, or the data from each port 15 is read in a time division manner and the high speed line 111 ( Or send it to 112).

Here, the virtual port 17 has, for example, a plurality of addresses equal to the number of channels included in the time division multiplexing communication system, except that the time division multiplexing control unit 131 (or 13).
From the viewpoint of 2), it operates exactly the same as other ports 15. In this example, the virtual port 17 is used to perform the relay operation between the time division multiplexers. For convenience of explanation,
For example, the time division multiplexer shown in FIG. 1 is referred to as 1B in FIG. 5, the high speed line 111 is connected to the time division multiplexer 1A in FIG. 5, and the high speed line 112 is connected to the time division multiplexer 1C. It is assumed that the data of the time division multiplexer 1A is relayed to the time division multiplexer 1C via the time division multiplexer 1B shown in FIG.

First, when data is sent through the high-speed line 111, the time division multiplexing control unit 131 transfers the address in the virtual port 17 corresponding to each channel by time division to the bus (address bus A in FIGS. 2, 3 and 4). ) 141 and outputs the data sent through the high speed line 111 to the address of the memory 24 of FIG. 4 through the bus 141 (bus D in FIGS. 2, 3, 4).
On the other hand, the time division multiplexing control unit 132 outputs the address in the virtual port 17 corresponding to each channel in time division to the bus (address bus A in FIGS. 2, 3 and 4) 142, and The data written in the address of the memory 24 is read through the bus (data bus D in FIGS. 2, 3, 4) 142,
After that, this data is sent to the high speed line 112. Therefore,
Data sent from the high-speed line 111 is temporarily virtual port 1
After being written in 7, it is immediately read out and sent to the high speed line 112. Therefore, the data from the terminal device of the time division multiplexer 1A connected to the high-speed line 112 is time-division multiplexed connected to the high-speed line 112 by using the time division multiplexer 1B of FIG. 1 as a relay. It will be sent to the terminal device of the digitalization device 1C. In addition, the data of the high-speed line 112
The operation of relaying to and sending to is also performed in the same manner.

According to this embodiment, even when the time division multiplexing device performs the relay operation, the time division multiplexing control unit 131 (or 132) only reads / writes data from / to the virtual port 17,
Since the reading / writing of data from / to the port 15 and the operation thereof during data communication between terminal devices are essentially the same, whether the time division multiplexing control unit 131 (or 132) is data communication between terminal devices or communication data Since it is not necessary to distinguish between the relay and the relay, both can be controlled by the same procedure. This eliminates the need for a bus that connects the time division multiplexing control units, simplifies the hardware configuration of the control units, and standardizes the control units regardless of the number of high-speed lines handled. The system expandability can be greatly improved. Further, the structure of the time division multiplexing apparatus is simplified by the above effect, so that the reliability of the system can be improved accordingly.

In the embodiment shown in FIG. 1, the case where two high-speed lines are supported has been described.
Since the memory 24 used in 17 has a large number of addresses, a plurality of relays between high speed lines of three lines or more can be performed by the same method. Further, the time division multiplexing control device 131 (or 13
In 2), since the transmission / reception (writing and reading) control units are provided independently as shown in FIG. 2,
Full duplex communication is also possible.

〔The invention's effect〕

As described above, according to the time-division multiplexer of the present invention, a virtual port composed of a read / write memory is connected to a bus connecting a terminal device and a port which is an interface, and data transmitted from one high-speed line. Is written to the virtual port, and then the written data is read out and sent to another high-speed line to relay the received data between a plurality of time division multiplexers. This has the effect of simplifying and improving the expandability of the supported lines.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the time division multiplexing apparatus of the present invention, FIG. 2 is a block diagram showing a detailed example of the time division multiplexing control unit shown in FIG. 1, and FIG. Is a block diagram showing a detailed example of the ports shown in FIG. 1, FIG. 4 is a block diagram showing a detailed example of the virtual ports shown in FIG. 1, and FIG.
FIG. 6 is a diagram showing an example of a time division multiplex communication system configured by using a plurality of conventional time division multiplex devices, and FIG.
FIG. 7 is a diagram showing a configuration example of a frame for controlling the time division multiplexing apparatus shown in FIG. 7, and FIG. 7 is a block diagram showing an example of a conventional time division multiplexing apparatus. 15 ... Port, 16 ... System control unit, 17 ... Virtual port, 22
W, 22R ... Address decoding unit, 23 ... Memory access control unit, 24 ... Memory, 111, 112 ... High speed line, 121, 122
... High-speed line interface, 131,132 ... Time division multiplexing control unit

Claims (1)

[Claims] 1. A first bus, a second bus, and a first bus and a terminal device, which are connected to the first bus, and which receive data coming through the first bus and send it to the terminal device. A plurality of ports each having a data input system and a data output system for sending out data sent from the terminal device via the first bus; and a port connected to the second bus and the terminal device, A plurality of ports including a data input system for receiving data coming through the second bus and sending it to the terminal device, and a data output system for sending data sent from the terminal device through the second bus. A memory for storing data, a data input system for receiving data coming through the first bus and writing the data into the memory, and reading the data stored in the memory And a virtual port having a data output system for sending out via the bus, and time-division-multiplexed data coming from the first high-speed line is taken in through the high-speed line interface, and data of each channel related to multiplexing is handled. To the port connected to the first bus of the address or the virtual port
A first time division multiplexing control unit having a data write system for writing via the bus, and reading data from the port or the virtual port connected to the second bus via the second bus, A second time division multiplex having a data reading system which is arranged in a channel related to multiplexing corresponding to an address of a port or a virtual port connected to the second bus and sends out to a second high speed line through a high speed interface. Of the multiplexing control unit and the first and second time division multiplexing control units, each channel relating to multiplexing used by the data writing system and the data reading system, and the address of the port or the virtual port. A time division multiplexing apparatus comprising: a system control unit that sets the relationship arbitrarily and controls the entire apparatus.