JPH0834570B2 - Solid-state imaging device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure amount control device for an image pickup apparatus using a solid-state image pickup element, and particularly, to improve the exposure amount control characteristic when picking up an image of a high-contrast subject. The present invention relates to the solid-state imaging device.

[Conventional technology]

A conventional exposure amount control device of this type is disclosed in, for example, Japanese Patent Application Laid-Open No. 57-4666. (Hereinafter, this is referred to as a first known row).

In the above apparatus, the image output signal from the image sensor is detected by the signal level detection circuit, and the diaphragm mechanism is controlled by the output of the level detection circuit. It is intended to deal with the imaging of.

Further, as another conventional technique, there is one described in the Proceedings of the 1982 National Conference of the Television Society of Japan, pages 31 to 32 (hereinafter,
This is called a second known example).

In this, it is shown that it is possible to control the signal charge storage time in the photoelectric conversion photodiode part of the solid-state image pickup device to compress the contrast when capturing a high-contrast object.

[Problems to be solved by the invention]

In the device of the first known example, when the area ratio of the high-luminance portion in the captured image is large, the aperture value is controlled so that the peak value level of the video signal becomes constant (called a peak detection method), When the area ratio of the brightness part is small,
The aperture value is controlled so that the average value level of the video signal is constant (called an average value detection method).

Due to the above characteristics, in the above-described conventional apparatus, when a main subject in a bright background occupying a large area (for example, a person against the background of the sea or the sky) is photographed, the background is appropriately set in exposure amount. Has the disadvantage that it will sink in the dark.
Also, if a bright part enters a part of the image, the other parts will be properly exposed, but the bright part will be a signal proportional to the light amount (brightness) due to the clip characteristics of the signal circuit of the video camera. The level cannot be maintained, and a so-called whiteout phenomenon occurs, resulting in loss of image information. further,
As a serious problem in this case, since the amount of incident light in the bright portion is excessive, the electric charge generated by photoelectric conversion in the image forming portion (light receiving surface) of the image pickup element becomes excessive, and the image forming portion of the high light amount image is detected. There is occurrence of so-called blooming development that overflows into the peripheral region. When blooming occurs, on the reproduced image, the image portion around the high-luminance image portion, which should be originally reproduced at low luminance, is reproduced at high luminance,
Image quality is significantly degraded. The reason why this development is a serious problem is that the image output, which is originally supposed to be, is lost in the signal output section of the image pickup element, so that recovery by a signal processing circuit or the like thereafter is theoretically impossible. It will be possible.

As a conventional example, an example has been described in which the aperture value is automatically controlled by switching between the peak detection method and the average value detection method, corresponding to the area ratio between the bright portion and the dark portion in the image.
In addition to the above example, there is also an automatic aperture control (auto iris) system which adopts the average value detection system at this time because the main subject is dimly sunk when the area ratio of the bright portion is large. Further, in order to alleviate the above-mentioned problems in the auto iris method, there are many cases in which it is possible to change the aperture value by the driving called exposure correction.

However, in the above-mentioned conventional methods, since the exposure amount is controlled by changing only the aperture value, it is always appropriate for various subjects with high contrast and a wide area ratio of bright and dark areas. It is difficult to obtain a large exposure amount. In other words, if you set the bright part as important so that whitening and blooming do not occur, it is unavoidable that the bright part is too dark (blacked out). In order to obtain a high level of exposure, it is inevitable that whitening and blooming will occur in bright areas.

Further, when the technique of the second known example is used,
When incident light of high contrast is used, the charge accumulation time of the solid-state image sensor is shortened to compress the contrast, so that white crushing, blooming, black sinking, etc. can be prevented. However, in the method described in the publicly known example, the contrast is lowered in the entire area of the screen, so that, for example, when the main subject is dark and the background has a high luminance, the detail information of the main subject is lost.

For this reason, conventionally, for example, when backlighting is performed, the contrast of the subject is lowered by supplementarily certifying a dark part using a spotlight, a light reflector, or the like.
There was a need for a photography method that required complicated and expert knowledge.

The device of the present invention makes it possible to obtain a video signal having a free contrast which does not depend on the contrast of the subject itself at the output by a simple operation, and is suitable for a bright part and a dark part of the subject. It is an object of the present invention to provide an apparatus capable of giving an exposure amount. Further, it is another object of the present invention to provide an apparatus capable of obtaining a reproduced image with a free contrast that does not depend on the contrast of the subject itself.

[Means for solving problems]

The above-mentioned object is to detect the accumulation time of photoelectric conversion charges in a photoelectric conversion element (hereinafter referred to as a pixel), which includes a photodiode or the like arranged on the image-forming light receiving surface (photoelectric conversion element array arrangement surface) of the solid-state image sensor. This is achieved by making it possible to set independently for each partial area of the surface.

[Action]

A control signal controls the accumulation start time t _W of photoelectric conversion charges in a pixel and the charge read time t _R for reading the charges accumulated in the pixel to the outside of the pixel. This control is independently performed for each picture element unit or each picture element region unit. From the above, the light accumulation time (exposure time)
Set T.

Exposure amount (photoelectric conversion charge accumulation amount) Q in the image sensor
Is expressed by the following equation.

Here, L is the amount of incident light from the taking lens, and A is the aperture value (so-called F number).

When a high-contrast subject is imaged, the amount of light that is incident on each part of the light-receiving surface to form an image varies greatly from part to part. In the conventional apparatus, the exposure amount is adjusted by appropriately setting A or T, but it is impossible to set different A or T values corresponding to respective portions of the received light amount, and the above-mentioned inconvenience occurs. .

According to the present invention, the exposure time T in each part of the light-receiving surface can be freely set by the control described above, so that the exposure amount in each part of the light-receiving surface can be freely adjusted. Therefore, the debel of the output signal of the image sensor can be freely controlled for each unit, and the disadvantage of the conventional example can be eliminated.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a solid-state image sensor, 2 is a drive pulse generation circuit for generating a pulse for operating the solid-state image sensor, and 4 is a video signal output from the solid-state image sensor. Is a signal processing circuit 4 that performs processing such as amplification and conversion into a television signal, and generates an output signal 3 in the form of a television signal or the like.

First, the configuration of the solid-state image sensor 1 will be described. Picture element cell PC
Is composed of a photodiode 5, a vertical switch 6 and a horizontal switch 7 formed of MOS transistors, which are arranged in a horizontal direction (left and right direction in the figure) and a vertical direction (up and down direction in the figure).
To form a light receiving surface. A vertical scanning line A8 for sequentially selecting the pixel cell rows arranged in the horizontal direction, a horizontal scanning circuit 9 for sequentially selecting the pixel cell columns arranged in the vertical direction, and outputs of these vertical and horizontal scanning circuits. Each pixel cell is connected by a vertical gate line 10 and a horizontal gate line 11 which guide the pulse to the gate terminals of the vertical switch 6 and the horizontal switch 7, respectively.
The PC is sequentially scanned to sequentially derive the light amount conversion charges accumulated in the junction capacitance of the photo and the ion 5 to the horizontal signal line 12. This electric charge is introduced to the output terminal 14 via the MOS transistor 13 which is a signal read switch that is simultaneously selected and conduction controlled by the vertical scanning circuit A8 corresponding to the selection of the pixel cell row.

A power source 15 having a reference voltage called a video bias voltage and a load resistor 16 are connected to the output terminal 14 of the solid-state image sensor 1 described above, and a solid-state image sensor output signal is obtained as a voltage proportional to the derived charge amount. , To the signal processing circuit 4.

In the drive pulse generation circuit 2, the read timing control pulse generator 17 generates a pulse for controlling the read timing of the pixel cells, and the vertical scan circuit A8 and the horizontal scan circuit 9 are generated.
Are driven by this pulse.

The configuration up to this point is as follows:
No. 11 (November 1986) (hereinafter referred to as Reference 1), page 1069, FIG.
This is the same as the solid-state image sensor described in 1 above and the image pickup apparatus using the same.

A feature of the present invention is that, in addition to the above configuration, a pulse generation circuit 20 that drives the vertical scanning circuit B18, the charge discharging switch MOS transistor 19, and the vertical scanning circuit B18, and controls the signal charge accumulation start timing in the photodiode. , Is provided.

Next, the operation of the image pickup apparatus shown in FIG. 1 will be described in detail with reference to FIGS. 2 and 3.

2 and 3 are operation waveform diagrams of the respective parts in FIG.
The vertical scanning circuits A8, B18, and horizontal scanning circuit 9 have the configuration and operation described in FIG.

In FIG. 2, Φ _1NA , Φ _IA , and Φ _2A are driving pulses for the vertical scanning circuit A8, Φ _1NA is a synchronizing pulse, and Φ _1A and Φ _2A are driving pulses (clock pulse) for the shift register that constitutes the scanning circuit. . Further, N _1A , N _2A , and N _3A are the pixel cell rows in FIG. 1 (the first row is PC (1,1), (1,2), ..., (1,
m), the second line is PC (2,1), (2,2) …… (2, m), and the following is the l-th line PC (l, 2) …… (l, 2) …… (1, m)), and Φ _1A , Φ _2A , and Φ _3A correspond to the first row, the second row, and the third row, respectively. In the FIG. 2 is intended but since N _3A is omitted for generating up to N _lA in the same phase relationship with the N _1A to N _3A.

Here, the vertical repeating cycle of vertical scanning is T _V (T _V is a field period of a television signal in a general TV camera). Therefore, the output period T _{1 of} N coincides with T _V.

FIG. 3 shows the operation timing of the horizontal scanning circuit 9. The horizontal scanning circuit 9 repeats the same operation every time the output N of the vertical scanning circuit occurs at any output terminal. The horizontal scanning circuit 9 has the same configuration as the vertical scanning circuit, and
_1NH is a synchronizing pulse, and Φ _1H and Φ _2H are shift register clock pulses. Also, Φ _1NH occurs in synchronization with N,
The horizontal scanning circuit outputs N _1H , N _2H , ... N _mH are the pixel cell columns (the first column is PC (1,1), PC (2,1), PC (3,1), ... PC
(L, 1), the second column is PC (1,2), PC (2,2), PC (3,2) ……
PC (l, 2), m-th column is PC (l, m), PC (2, m), PC (3, m),
...... PC (1, m)) is the pulse output to the horizontal gate line 11 corresponding to, and N _1H , N _2H , ... N _mH are in the 1st, 2nd, ... mth columns, respectively. Correspond. Although N _{3H and the} following are omitted in FIG. 3, they are sequentially output in the same phase relationship as N _1H and N _2H .

If N is now N _3A in FIG. 2, the accumulated charge of the photodiode of PC (3,1) is N _2H at the generation timing of N _1H in FIG. 3 and each of PC (3,2) is N _2H . It is read from the solid-state imaging device 1 as a signal output at the generation timing. Second
As can be seen from the figures and FIG. 3, as a result of the above, the photodiodes arranged in the third row instantaneously read out the charges accumulated therein in the cycle of T ₁ in FIG. 2 and thus the accumulation of photoelectric conversion charges. The period is the time between one read timing and the next read timing, and the accumulation time is approximately T _{1 in} FIG.

In a conventional television camera or the like, the signal is read from the solid-state image pickup device only by the above operation, so that the charge accumulation time in all photodiodes in the light receiving surface is the same.

It will be described below that the storage time can be set to a different value for each pixel block in the present invention.

A drive pulse is applied to the vertical scanning circuit B18 having the same configuration as the vertical scanning circuit A8 from the pulse generating pocket 20 that operates in synchronization with the read timing control pulse generating circuit 17. This drive pulse is shown in Fig. 2, Φ _INB , Φ _1B , and Φ _2B .
The output pulses of the scanning circuit 18 are shown as N _1B , N _2B , and N _3B . The operation of the vertical scanning circuit B18 is the same as that of A8.

However, the generation timing of the synchronizing pulse Φ _INB is offset from Φ _INA for the time T ₂ shown in FIG. ₂ , and the clock pulses Φ _1B and Φ _2B are output from the vertical scanning circuit outputs N _1B and N _2B. It is a characteristic of the operation control of the vertical scanning circuit B18 that it is supplied only until it is output.

The output pulses of the vertical scanning circuits A and B are the logical sum means (diodes 21, 22 in FIG. 1) provided in the vertical gate line portion.
The diode OR circuit composed of 1) supplies the logical OR to the vertical gate line.

Therefore, the charge accumulated in the photodiode of the first row at the timing of generation of N _1B in FIG. 2 and that of the second row at the timing of generation of N _2B are discharged switch MOS transistor 1
It is led out to the video bias power supply 15 via 9.

Therefore, at this point, the accumulated charges in the photodiodes in the first and second rows are once discharged, and the charge accumulation is restarted thereafter.

As is clear from the above description, in the image pickup device of FIG. 1 which operates at the drive pulse timing of FIG. 2, the charge accumulated as a signal is accumulated in the pixel blocks on the first and second rows. The time becomes T ₂ , and T _{1 in} the blocks of other picture elements. That is, a different charge storage time is set for each pixel block.

FIG. 4 is a block diagram showing a specific example of the pulse generation circuit for controlling the accumulation start timing of FIG. 1, and FIG. 5 is an operation waveform diagram of each part thereof.

In the figure, a reference frequency clock generation circuit 101 and a logic circuit 102 including a counter and the like form a pulse generation circuit (17 in FIG. 1) that generates a drive pulse for the solid-state image pickup device described in the above-mentioned document 1.

In the pulse generation circuit 20, first, the monostable multi-bi-break 103 inputs Φ _INA to generate a pulse 104 having a phase delayed by the time shown in T _d in FIG. Since the pulse 104 resets the T-flip block (TFF) 106 via the OR circuit 105, the TFF 106 starts operating with the pulse Φ _2A as the clock after the generation of the pulse 104, and the pulse 107 at its Q output And outputs the polarity inversion pulse 108.

The monostable multivibrator 109 receives the pulse 108 and produces an output pulse 110 having a pulse width T _W. A pulse 112 is generated by a D flip-flop (DFF) 111 in which the pulse 110 is data input and Φ _1A is a clock pulse. From pulse 112 and pulse 110 through OR circuit 113, pulse 114
Are generated, and AND circuits 115 and 116 perform AND operation of Φ _1A and Φ _2A and the pulse 114, respectively, to obtain pulses 117 and 118.

The pulses 107, 117, 118 are Φ _INB , Φ in FIG. 2 respectively.
Corresponds to _IB and Φ _2B . The TFF 119 generates the pulse 120 after the pulse 107 is generated once, and stops the generation of the pulse 120 when the pulse 104 is generated. Pulse 120 to OR circuit 105
Since it is input to the reset terminal of the TFF 106 via, the pulse 107 is generated only once for each repeating period of Φ _INA .

Here, the monostable multivibrator 103 is connected to the variable resistor 122 whose one end is connected to the operating power supply 121, and by changing the resistance value, Td in FIG. 5 can be varied, and accordingly, in FIG.
You can change T ₂ . In addition, the Tw in FIG. 5 can be changed in the same manner as in the monostable multivibrator 109, and pulse 117,1
Since the number of generated pulses of 18 can be changed, the area of the pixel block having the charge storage time T ₂ can be changed.

 The effect of the embodiment described above will be described with reference to FIG.

FIG. 6 is a conceptual diagram showing a screen of a monitor television to which the output of the apparatus of the above embodiment is supplied. The upper part of the screen is the accumulation time T ₂
The reproduction position of the signal generated in step ₁ , and the shaded portion is the reproduction position of the signal generated in the accumulation time T ₁ . In the above embodiment, T ₂ <
Since it is T ₁ , if the brightness of the copy is uniform on the entire screen, the upper part of the screen is reproduced darker than the lower part.

By the way, in a subject photographed by a normal video camera, a bright sky or the like often enters the upper part of the screen. In such a case, the use of the present device can reduce the accumulation time of the high-intensity part and prevent the occurrence of white crushing, blooming and the like.

When the drive pulse generating circuit of FIG. (4) is used,
While it is possible T ₁ and two accumulation time setting of T _2, a description will be given of an embodiment of a drive pulse generating circuit which enables two or more time setting below.

FIG. 7 is a block diagram showing another specific example of the drive pulse generating circuit, which includes a reference frequency clock generating circuit 101,
Two logic circuits 102 are provided, and Φ _INA , Φ _1A , and Φ _2A are obtained from one system as in FIG. Other one system by changing the oscillation capacitance 201 of the clock generation circuit 101, Φ _1A, repeated cycles of different [Phi _1A and Φ _2A ', Φ _2A' generates a. From Φ _INA and Φ _1A ′, Φ _2A ′, Φ _INB , Φ _1B , and Φ _1B by the same pulse generation circuit 20 for controlling the storage start timing as in FIG.
Generate Φ _2B .

According to this configuration, N _1B of FIG. 2, occurrence time difference of N _2B is, N _1A, the different from the time difference T _H of N _2Al, the although connexion first row of photodiodes and the second row of photodiodes You can change the storage time with.

As a result, the accumulation time for each scanning line can be changed more finely at the portion T ₂ in FIG. 6, so that even if a subject having a uniform brightness is photographed, the contrast on the reproduced image will change from the top to the bottom of the screen. It is also possible to obtain a so-called gradation effect that gradually changes toward.

The present invention has been described above with reference to the embodiment shown in FIG.
Interlace scanning systems are adopted in television systems such as C, PAL, and SECAM systems, and solid-state imaging devices compatible with interlace scanning are also adopted in solid-state imaging devices corresponding to these television systems. . That is what is shown in FIG. 8 on page 1070 of the aforementioned literature 1.

FIG. 8 is a block diagram showing another embodiment of the present invention.
The interlace circuit A301 uses a pulse _{Fa aA for a} MOS transistor during a certain field period (referred to as a field a).
By making 302 conductive, the second row, the third row, the fourth row, the fifth row, the sixth row, the seventh row, ... Of the picture element column are output by the same output pulse of the vertical scanning circuit A8. It is possible to select at the same time. Further, in the subsequent field period (referred to as field b), the MOS transistor 303 is turned on by the pulse F _bA , and the first and second rows, the third and fourth rows, the fifth and sixth rows, ... It is possible to select two lines at the same time.

The output gate A304 is composed of a MOS transistor, and outputs the control pulse to the vertical gate line 10 and the signal read switch 13 by taking the logical product of the output of the vertical scanning circuit A8 and the pulse Φ _3A . It also serves as a unidirectional conducting means (similar to the role of the diode 21 in FIG. 1) for taking the logical sum of the outputs of the vertical scanning circuits A and B of the vertical gate lines.

The vertical scanning circuit B18, the interlace circuit B305, and the output gate B306 are respectively a vertical scanning circuit A8 and an interlace circuit A3.
01, has the same configuration as the output gate A304.

The signal charge reading operation from the pixel cell PC via the signal read switch 13 and the discharging operation via the charge discharging switch 19 are the same as those in the solid-state image sensor of FIG.

FIG. 9 is an operation waveform chart of each part of the embodiment shown in FIG. In FIG. 9, only the pulse generation timing is shown, and the pulse width is different from the actual one.

In the figure, in the interlaced scanning system, one field period T _v is (integer + 1/2) times the horizontal scanning period T _H. For this reason, the repeating period of Φ _INA generated in synchronization with Φ _1A changes by T _H between the field a and the field b. Here T _V1 in the field a is, T _V1 in the field b
T _V2 is shorter than T _H. Further, in FIG. 9, the output gate A30
4. Assume that the applied pulses Φ _3A and Φ _{3B of} B306 are always generated (the gate is made conductive).

By the operation of the interlace circuit A301 described above, pulse
In field a where F _aA occurs, the second and third lines,
A pulse N _2A is simultaneously applied to the vertical gate lines on the 4th and 5th rows.
N _3A , N _4A and N _5A are output. In the field where pulse F _bA is generated, pulses N _1A and N _2A , N _3A and N _4A , N _5A
And N _6A are output at the same time. As a result, in the solid-state imaging device described in Document 1 in which the vertical scanning circuit B is not provided,
As shown in the figure of pulse N _4A , N _5A , and N _6A , the accumulation time T
Two picture element rows each having _V1 and T _V2 are simultaneously read to generate a video signal of one scanning line. However, the (NTSC scheme for T _H is sufficiently small with respect to T _V1 T _V1
= 264T _H ) There is no problem in practice.

Here, in the present invention, the pulse generator circuit 20 of FIG.
Figure Φ _INB , Φ _1B , Φ _2B and F _aB (F _aA pulse part shows the generation timing with a broken line) and F _bB (also shown in F _bA pulse part) are generated, and the vertical scanning circuit B 18 and the interlace circuit B 30 are generated.
5, drive output gate B306, pulse to the vertical gate line
N _1B , N _2B , N _3B , N _4B , N _{5B, etc.} are applied.

As a result, the photodiode charge of the first to the picture element columns of the fourth row to be read in field b becomes to have been accumulated in the accumulation time of T _2, it fifth and subsequent rows were periods accumulation of T ₁ Will be things.

Next, in the field b, by generating the generation timing of Φ _INB with respect to Φ _INA by delaying T _H from the time of the field a, the first read-out in the subsequent field a is performed.
~ Set the photodiode charge accumulation time in the third row
Match T ₂ .

FIG. 10 is a configuration diagram showing still another specific example of the pulse generation circuit that realizes the above-mentioned operation. In the period from the output of TFF106 to the input of TFF119 and monostable multivibrator 109 of FIG. Composed of NAND circuit 402, pulse F
Controlled by _aB and F _bB , the output of TFF106 and thus Φ
If a switch circuit for switching and outputting the output pulse of DFF401 delayed by one cycle of ₂ A, that is, T _H, is inserted, the other configurations can be realized with the same configuration as the pulse generation circuit 20 shown in FIG. .

Alternatively, by using the output gate B306 of the image sensor of FIG. 8, [Phi _1A to [Phi _1B, as it is used [Phi _2A to [Phi _2B, [Phi _INB and the third figure pulses 114 generated at the timing of Figure 9 shown Supplied from the pulse generation circuit 20 that is a combination of FIG. 10 and
If the pulse 114 is used as Φ _3B , the same N _1B ,
N _2B , N _3B and N _4B outputs are obtained.

FIG. 11 is another operation waveform diagram of FIG. 8, and FIG. 12 is a conceptual diagram of the monitor TV screen, and illustrates one operation example using the output gate B306. FIG. 11 is a pulse generation timing chart used here, in which the same Φ _1B as Φ _INB and Φ _1A and Φ _2B same as Φ _2A are applied to the vertical scanning circuit B18, and the same is applied to the output gate B306. Φ _3B shown in Fig. 11
Is applied.

As described above, the output gate B306, like the output gate A304, gives an output pulse of the logical product of the output of the vertical scanning circuit and Φ _3B to the vertical gate line.
A pulse having a waveform as shown by N _{B1 to} N _B2n is applied to the vertical gate lines around the row. As can be seen from the above description, in the portion where the vertical gate pulse N is output, the accumulation time becomes T ₂ which is determined by the phase relationship of Φ _INB with respect to Φ _INA , and in the portion where the gate pulse N is not output, the photodiode Charge is not discharged, the storage time becomes T ₁ which is determined by the repeating period of Φ _INA .

As a result, when the solid-state image pickup device 1 is driven as shown in FIG. 11, the shaded portion on the reproduced image shown in FIG. 12 is the signal accumulated at T ₁ , and the other portion is the signal accumulated at T ₂ . If Φ _3B is inverted in polarity from that shown in FIG. 11, the regions T ₂ and T _{1 in} FIG. 12 are also inverted.

Further, by changing the waveform of Φ _3B variously, it is possible to give an accumulation time of either T ₂ or T _{2 to} each arbitrary area on the screen.

FIG. 13 is a configuration diagram showing a specific example of the pulse generation circuit for generating the pulse Φ _3B as shown in FIG.

In the figure, the monostable multivibrator 401 is Φ _INB.
Set up 12 region of Figure D ₁ as inputs. The DFF 402 generates an output 404 that synchronizes the output 403 of the multivibrator 401 with the phase of the pulse Φ _2B . The monostable multivibrator 405 sets the area of D ₂ in FIG. The DFF 406 produces an output 408 that synchronizes the output 407 with the pulse Φ _2B . The monostable multivibrator 409 sets the area D4 and 410 in FIG.

The AND circuit 411 is connected to the output 404 and the voltage source 412 having one logic level, and the AND circuit 413 is connected to the output 408 and the output 419 of the multivibrator 410. Further, if the AND circuit output is input to the OR circuit 414, a pulse output as shown in Φ _3B in FIG. 11 is obtained at the output 415. Further, if the polarity inversion pulse 417 of the output 415 is obtained by the inverter 416 and switched by the switch 418 to obtain Φ _3B , T _{1 in} FIG.
The region and T ₂ region can be reversed.

Furthermore, from an output 404 an output 408 Metropolitan can generate pulses indicating the region D3, which Figure 12 D3 possible i.e. D2 to the area in the region of the storage time T _2, D5 only logical product region of the T ₁ using It is easy to make a region.

Further, if the horizontal scanning circuit clock Φ _1H shown in FIG. ₃ is used to generate Φ _3B , the accumulation time T ₁ or T ₂ may be changed for each pixel.
It is also possible to have.

The embodiments in which the present invention is configured by using the MOS type image pickup device described on pages 1067 to 1072 of Document 1 have been described above. Next, the present invention is realized by using the CCD type image pickup device. Here is an example:

FIG. 14 (a) is a configuration diagram showing an embodiment in which the present invention is configured by a CCD type image pickup device, and FIG. 14 (b) is a drive pulse waveform diagram thereof.

In the figure, the CCD type image pickup device has the same structure as the known example shown in FIG. 1 of Japanese Patent Publication No. 60-46594, that is, a photodiode section 501, a vertical transfer CCD 502, a transfer gate 50.
3, consisting of horizontal transfer CCD 504, transfer gate 503
It is characterized in that a plurality of lines (two lines in FIG. 14) of gate lines 505 and 506 are provided so that a part of the above can be controlled at a timing different from that of other transfer gates.

Although not shown in FIG. 14 (a) using the above image pickup device, the clock pulses ΦV ₁ and ΦV ₂ applied to the clock input terminal of the vertical transfer CCD 502 provided in the same manner as the device described in the above-mentioned known example are used. On the other hand, if the transfer gate pulses Φ TG ₁ and Φ TG ₂ are applied in the phase relationship shown in FIG. 14 (b), the signal charge read timing from the photodiode can be changed for each pixel region.

Here, the signal charge storage time can be changed for each pixel region by using the technology of the second known column previously described in the section of the prior art and aligning the storage start times of all the photodiodes at the same time. .

As another method, by using the technique of the second known example, a plurality of voltage applying conductors for applying a bias voltage to the well of the photodiode section are provided for each photodiode region at different timings. By performing the bias voltage control described in the above-mentioned known art, the signal charge storage time can be controlled by changing the storage start time for each pixel area.

FIG. 15 is a block diagram showing a concrete application of the present invention,
The signal output of the solid-state imaging device 1 is amplified by the signal amplification circuit 601, and the output 602 is processed by the same auto iris means 600 as the first known column including the rectification circuit 603, the operational amplifier 604, and the diaphragm drive mechanism 605, The diaphragm plate 606 installed on the lens 613 is controlled.

At the same time, the output 602 is compared with the reference voltage V ₁ by the comparator 607, and a pulse 609 indicating a region below the predetermined signal level and a region above the predetermined signal level with binary voltage levels is obtained. Where the output 602
Is input to the comparator 607 via an appropriate low-pass filter, it is possible to divide each area having a relatively large area.

FIG. 16 is an operation waveform diagram of FIG. 15, showing a waveform example of the output 602 and the pulse 609. HSYNC indicates the generation phase of the horizontal synchronization signal.

Since pulse 609 is generated in synchronization with Φ _INA in FIG. 9,
This is delayed by the delay circuit 610 and synchronized with Φ _INB . As the delay circuit, for example, a digital memory circuit may be used. If the delay circuit output is used as Φ _{3B in} FIG. 8,
As can be seen from the description in FIG. 11, it is possible to control the accumulation time only in the above-mentioned region of the predetermined signal level or higher. That is, with the above configuration, the area setting described with reference to FIG. 12 can be automatically performed. By inserting a low-pass filter in the delay circuit output section and setting the output to Φ _3B , it is possible to prevent noise in the pulse edge part of Φ _{3B from} being superimposed on the output of the solid-state imaging device.

Here, in the drive pulse generation circuit 20, if the variable resistor 122 described in FIG. 3 is manually or automatically adjusted, the signal level can be lowered only in the high luminance portion, so that blooming or the like is not generated and the low luminance portion is not generated. Exposure correction that makes the detail clear becomes possible.

In order to automatically adjust the variable resistor 122 shown in FIG. 15, the output 602 is input to the same rectifier circuit 611 as in the first known example, and this output is compared with the reference voltage V ₂ by the operational amplifier 612. The resistance value variable control may be performed with the output 608.

Here, the rectifier circuit 603 is set to the average value detection characteristic, the rectifier circuit 611.
If the peak detection characteristic is used, blooming and the like can be automatically prevented.

Further, even if the rectification circuit 603 uses either the average value detection method or the peak detection method, it is inevitable that the main subject will be dark when the main subject has a high contrast and a small area and is dark. At this time, if the auto iris circuit is released and the aperture is opened manually, there is a risk of whiteout blooming in the high-brightness area in the conventional device, but at this time the automatic storage time control in Fig. 15 should be activated. If there is no such fear.

FIG. 17 is a block diagram showing another specific application example of the present invention, which is different from the embodiment of FIG.
Instead of the Φ _3B generating circuit consisting of the delay circuit 610, FIG.
Using the image region setting gate pulse generating circuit 700 as described in FIG. 13, and using the output of the gated pulse generating circuit as Φ _3B , at the same time, the signal of the portion corresponding to the image region is removed from the video signal. This is what I tried to remove with the Tori gate 701. The control pulse 702 for the image removal gate 701 is a pulse synchronized with Φ _INA.
It can be generated in the same way as the generation of _3B .

In the case of the concrete example shown in FIG.
It is also possible to adopt the CCD type element as described in FIG. In this case, the gate pulse 702 may correspond to the image area determined by the structure of the image sensor, and the Φ _3B pulse is unnecessary.

With the above configuration, one of the image areas is automatically controlled by the auto iris, and the other is automatically controlled by the storage time control of the present invention. For example, when a proper exposure is given to the central portion of the image by the auto iris, whitening at the peripheral portion, It can be automatically corrected to prevent blooming and blackout.

In the above embodiments, the apparatus suitable for use mainly in the television camera has been described. However, it is not an apparatus for continuously scanning a solid-state image sensor to generate a moving image, but a so-called electronic device for obtaining a still image by one-time scanning. In still cameras and the like, the following embodiments can be considered.

That is, if the vertical scanning circuit A8 is subjected to the gate operation described in FIGS. 11 to 13 by the Φ _3A pulse of the image pickup device shown in FIG. 8, only a certain region in the image is longer than the field cycle. It is possible to store charges for a period. If the gated operation of the Φ _3A pulse is stopped after the lapse of a predetermined time, and the picture element charges of all areas are read and recorded in the same field, a still image generated from the signal charges accumulated for different times for each picture element area can be obtained. To be In this case, the vertical scanning circuit B and the like are not always necessary, and the conventional type solid-state imaging device described in Document 1 can be used.

The present invention has been described above with an emphasis on the contrast compression effect. However, as is clear from the equation (1), the present invention can change the shutter speed for a normal film camera for each image area. , Images with different shutter speeds can be generated in the same image. Therefore, for example, it is possible to realize a special effect in which the main subject in the central portion of the image is photographed with proper exposure and without deviation, and the peripheral portion is photographed as an image floated in white to make the main subject stand out. It is also possible to darken the peripheral portion to almost no signal level while leaving the central portion exposed properly.

〔The invention's effect〕

As described above, according to the present invention, it is possible to set the accumulation time of the signal charges by the picture elements to different values for each picture element region of the solid-state image sensor, so that (a) when photographing a high-contrast subject (B) The main subject can be photographed with an appropriate exposure amount regardless of the brightness of the peripheral portion of the main subject, and white in the peripheral portion can be prevented. It is possible to prevent the occurrence of crushing and blooming, or to shoot with reduced black shift, and (c) realize a special effect of generating an image of a contrast that does not depend on the contrast of the subject itself in the device output. It is possible to provide a solid-state imaging device having an excellent function, excluding the drawbacks described above.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIGS. 2 and 3 are operation waveform diagrams of respective portions in FIG. 1, and FIG. 4 is a specific example of a pulse generation circuit for controlling a storage start timing. Block diagram, fifth
4 is an operation waveform diagram of each part of FIG. 4, FIG. 6 is a conceptual diagram of a monitor television screen, FIG. 7 is a block diagram showing another specific example of the drive pulse generating circuit, and FIG. 8 is another embodiment of the present invention. FIG. 9 is a configuration diagram showing an example, FIG. 9 is an operation waveform diagram of each part of FIG. 8, and FIG. 10 is a configuration diagram showing still another specific example of the pulse generating circuit, FIG.
8 is another operation waveform diagram of FIG. 8, 12 is a conceptual diagram of a monitor television screen, FIG. 13 is a configuration diagram showing still another specific example of the pulse generation circuit, and FIG. 14 (a) shows the present invention. FIG. 14 (b) is a configuration diagram showing an embodiment in which the CCD is constituted by a CCD image pickup device.
Is a drive pulse waveform diagram, FIG. 15 is a configuration diagram showing a concrete application example of the present invention, FIG. 16 is an operation waveform diagram of FIG. 15, and FIG. 17 is another concrete application example of the present invention. It is a block diagram. 1 ... Solid-state image sensor, 2 ... Drive pulse generation circuit, 17 ...
... Readout timing control pulse generation circuit, 18 ... Pixel charge reset scanning vertical scanning circuit, 20 ... Accumulation start timing control pulse generation circuit, 600 ... Auto iris circuit, 607 ... Comparator, 610 ... Pulse delay circuit,
700 …… Gate pulse generator.

Claims (4)

[Claims] 1. A photoelectric conversion surface composed of a plurality of photoelectric conversion elements in which a plurality of horizontal rows of photoelectric conversion elements arranged in a horizontal direction are arranged in a vertical direction, and a first period having a constant period T _V. And a read timing control pulse circuit for generating a read timing control pulse composed of the first synchronization clock and a first clock having a period T _H shorter than the period T _V, and the read timing control pulse is supplied. In the solid-state imaging device having a first scanning unit that sequentially selects the plurality of photoelectric conversion elements for each synchronization pulse in a predetermined order according to the arrangement, and outputs the accumulated charge as a video signal, the second synchronization pulse and the second accumulation start timing control pulse and a second clock of the period T _H in synchronism with the sync pulses of T _V occurs, the second clock A pulse generation circuit for controlling the accumulation start timing, which is generated for each second synchronization pulse; first means for varying the phase difference of the second synchronization pulse with respect to the first synchronization pulse; The number determined by the second means for varying the number of the second clocks in the cycle T _V and the number of the second clocks on the photoelectric conversion surface supplied with the storage timing start control pulse Second scanning means for sequentially selecting the photoelectric conversion elements in the selected region consisting of the horizontal row of the photoelectric conversion elements in the predetermined order to read out and discharge the accumulated charges, and the second scanning means in the photoelectric conversion elements. In the photoelectric conversion element in the selected area of the photoelectric conversion surface, the accumulation time of the accumulated charges for reading out as a video signal by the first scanning means is selected by the second scanning means. And the selection timing by the first scanning means immediately after that, in the photoelectric conversion element in the area other than the selected area of the photoelectric conversion surface, the period between the selection timing by the first scanning means. Solid-state imaging characterized in that the size of the selected area on the photoelectric conversion surface can be set as desired as time equal to T _V , and the contrast of the video signal from the selected area can be arbitrarily changed. apparatus. 2. The charge stored by the second scanning means according to claim 1, wherein a portion of each of the horizontal columns of the photoelectric conversion elements forming the selected area on the photoelectric conversion surface is stored. A solid-state imaging device comprising means for selectively prohibiting discharge. 3. A photoelectric conversion surface having a plurality of photoelectric conversion elements arranged in horizontal and vertical directions, and means for reading out photoelectric conversion charges accumulated in the photoelectric conversion elements from the plurality of photoelectric conversion elements to obtain a video signal. In the solid-state imaging device, the photoelectric conversion charge accumulation start times in the plurality of photoelectric conversion elements are set to be the same, and the photoelectric conversion charge read times are different from each other in n (where n is an integer of 2 or more) times. The solid-state imaging device is configured so that the storage time of the photoelectric conversion charge of each photoelectric conversion element can be different. 4. A photoelectric conversion surface having a plurality of photoelectric conversion elements arranged in horizontal and vertical directions, and means for reading out photoelectric conversion charges accumulated in the photoelectric conversion elements from the plurality of photoelectric conversion elements to obtain a video signal. In the solid-state imaging device, the photoelectric conversion charge accumulation start time in the plurality of photoelectric conversion elements is set to any one of n (where n is an integer of 2 or more) different from each other, The solid-state imaging device is characterized in that the means for making the same reading time is provided so that the accumulation time of photoelectric conversion charges of each photoelectric conversion element can be made different.