JPH083812B2 - Function operation control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] This is a method of controlling a function operation of vector data and the like. When there are multiple sets of constants to be used for function calculation, for example, coefficients of approximate polynomials, and one set is determined by the value of the argument and used for calculation, multiple index cables are duplicated in the constants. Table indexes that are stored in memory and have a continuous index order allow different tables to be accessed so that processing delay is less likely to occur due to read contention of the same term.

[Industrial applications]

The present invention relates to a method of controlling a function operation of vector data or the like in a computer system.

In the approximation calculation of the function using the approximation polynomial,
In order to obtain a desired approximation accuracy, for example, a method of using different coefficient values depending on the range of argument values is generally used.

In this case, the coefficient values are arranged in a table, and in the function operation, a set of coefficients is obtained by indexing the table with an index determined by a predetermined method from the argument.

Therefore, in order to speed up the function calculation, it is necessary to execute the table index at high speed.

[Problems to be solved by conventional technology and invention]

FIG. 2 is a block diagram showing the configuration of a computer system having a vector processing device.

In the figure, 1 is a vector processing device, 2 is a main storage device, and in the vector processing device 1, under the control of the execution control unit 3, the main storage access control unit 4 connects the vector register 5 and the main storage device 2 to each other. Controlling the data transfer between them, the arithmetic control unit 6 reads the data of the vector register 5 and processes it, and stores the processing result in the vector register 5.

In the function calculation, as described above, the value of, for example, the coefficient of the approximate value calculation formula of the function is set to be different depending on the value of the argument (the number to be substituted into the variable of the calculation formula). A method that maintains the calculation accuracy of is assumed.

As an example, in one operation method in which the function is a square root, the argument x is first converted into x ′ such that the range is 1/16 ≦ x ′ <1, the square root is obtained for x ′, and the result is By the method of returning to the square root corresponding to x by the inverse transformation,
The square root of a positive number x up to a predetermined maximum value is calculated.

Here, in the case of a well-known floating-point number in 16 power form, the conversion is, in principle, an operation of setting the exponent part of x in a so-called normalized form to 0, and x ′ is The obtained inverse transformation is an operation of adding 1/2 of the exponent part of x to the exponent part of the result obtained from x '.

An approximate value calculation of the square root of x'is a function of x'y '
According to the known so-called Newton's iterative method, the initial value y ′ is divided into, for example, the range of x ′ into, for example, four regions, and the coefficient a _i which is different for each region,
The required approximation accuracy can be obtained by a constant number of iterations for the entire range of x ′ by obtaining the calculation expression having b _i .

When 1/16 ≦ x ′ <1/8 y ′ = a ₀ x ′ + b ₀ 1/8 ≦ x ′ <1/4 y ′ = a ₁ x ′ + b ₁ 1/4 ≦ x ′ <1 When / 2 y ′ = a ₂ x ′ + b ₂ 1/2 ≦ x ′ <1 y ′ = a ₃ x ′ + b _{3 When} performing approximation of such a function on vector data, For example, first, the main memory access control unit 4 sets the vector data x on the main memory 2 to
The data is read into the vector register 5, and the arithmetic unit 6 converts this to generate a data vector 10 of x '(FIG. 3).

Next, the arithmetic unit 6 extracts a bit string serving as an index for indexing the constant table holding the coefficient from each element data of the data vector 10 and outputs the index vector 11 (Fig. 3) as a vector register. Create in 5.

This index uses, for example, the upper 3 bits of the mantissa part of the floating point number x'normalized in the above format.

The main memory access control unit 4 reads the constants from the constant table 12 using the start address of the constant table 12 (FIG. 3) and the index vector 11 stored in the main memory 2 and stores them in the vector register 5. .

Here, the constant table 12 is a table holding the paired values of the coefficients a _i and b _i in each term, and for indexing by the index determined as described above, for example, the same coefficient is partially duplicated. The table is composed of 8 items.

In parallel with the control of the main memory access control unit 4, the arithmetic unit 6 performs an approximate calculation using the data of the data vector 10 of the vector register 5 as an argument by using the above-mentioned sequentially read constant, for example, a pipeline method. It is executed by the arithmetic circuit of.

In the case of the data vector 10 illustrated in FIG. 3, the second,
Data of the same value range, such as the third and fourth element data 14, 15, 16 and the like, will naturally read the same term on the constant table 12, so that in this case, When the data of various relations are continuous, to the main storage device 2,
It is possible that access requests of the same address will continue, and subsequent access requests will be kept waiting until the execution of the access by the previous request is completed.

That is, in a main storage device in a relatively large-scale computer system, as is well known, by a method such as so-called interleaving, access to different addresses in adjacent storage areas can be executed in parallel. Generally, it is possible to read data with high throughput.

However, even in such a case, access to the same address as described above has to be processed serially, and as a result, in the vector processing device 5, the flow of data supply to the arithmetic unit 6 is delayed and the processing is performed. There is a problem that performance is degraded.

[Means for solving problems]

 FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, 20-0, 20-1, ... Are constant tables of the same contents provided in the main storage device 2, respectively, and 21 is an index vector generated in the vector register 5.

[Action]

The constant table for determining the coefficient of the approximate calculation formula is the same as the conventional one except that 20-0, 20-1, 20-2
Etc., a plurality of them are provided so as to overlap the main storage device 2.

In the index generation for the constant number cable index, the calculation unit 6 first creates the primary index vector 11 with the bit string extracted from the vector data 10 as in the conventional case. By adding bit strings for designating the tables 20-0, 20-1, ..., So that consecutive indexes on the index order (array order on the vector) point to different constant tables, Generate the index vector 21.

The storage access control unit 4 uses the index vector 21 to store the constant tables 20-0, 20-1, ... Of the main storage device 2.
Access ...

With this configuration, for example, if four constant tables are provided in duplicate, even if the same term is accessed up to four times,
Since the waiting for the access of the main storage device 2 does not occur, the delay in the acquisition of the coefficient and the like can be significantly reduced.

〔Example〕

FIG. 1 shows the configuration of an embodiment of the present invention for performing the approximate calculation of the same data as in the case of the description of the conventional example.

The contents of the constant table for determining the coefficients of the approximate calculation formula may be the same as the conventional one. Such constant table
As shown by 20-0, 20-1, 20-2, and 20-3, a plurality (four in this example) of the main storage device 2 are provided in duplicate.

Each constant table 20-0 to 20- in the main memory 2
The storage areas of No. 3 do not necessarily need to be continuous, but in general, the continuous area is easier to control, and will be described below as a continuous area.

In the index generation for the constant table index, the arithmetic unit 6 first creates the primary index vector 11 with the bit string extracted from the vector data 10 as in the conventional case, and places 0, 1, 2 in the upper order of each index. The bit vector representing 3 is sequentially added to generate the index vector 21.

As a result, when the storage access control unit 4 accesses the main storage device 2 by using the index vector 21 with the head address of the constant table 20-0 as a base address as in the conventional case, the index vector 21 is adjacent to the index vector 21. Each index has a different constant table 20-0 to 20
-3 will be specified.

〔The invention's effect〕

As is clear from the above description, according to the present invention, there is a remarkable industrial effect of improving the processing performance of the functional calculation of vector data and the like in the computer system.

[Brief description of drawings]

FIG. 1 is a block diagram of a configuration example of an embodiment of the present invention, FIG. 2 is a block diagram of a configuration example of a computer system, and FIG. 3 is a block diagram of a conventional configuration example. In the figure, 1 is a vector processing device, 2 is a main storage device, 3 is an execution control unit, 5 is a vector register, 4 is a main storage access control unit, 6 is a calculation unit, 10 is a data vector, 11 and 21 are index vectors. , 12, 20-0 to 20-3 are constant tables.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobunobu Akita 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References Japanese Patent Laid-Open No. 50-26439 (JP, A) 50756 (JP, U)

Claims (1)

[Claims] 1. When determining a constant used for approximating a value of a function for an argument by indexing a table based on the value of the argument, a plurality of the tables are stored in the table storage means. Then, if the value is a value that indicates a term that holds each of the required constants of the table based on the value of each argument and corresponds to the arguments that are consecutive with each other in a predetermined index order, An index having a value indicating the item of the table at a different position on the table storage means is generated and held in the index storage means, and the index is held by the index storage means according to the index order. A function operation control method, characterized in that the table of the table storage means is indexed to determine the constant for each argument.