JPH083959B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a semiconductor mask ROM (read only memory) in which a memory cell is written by an ion implantation method. It is related to effective technology.

[Conventional technology]

A mask ROM in which stored information is written by changing the threshold voltage of a memory cell by ion implantation is described, for example, in pages 198 to 199 of the September 26, 1983 issue of Nikkei Electronics. ing.

[Problems to be solved by the invention]

With the progress of semiconductor technology, devices have been miniaturized, and mask ROMs having a large storage capacity have been studied. Due to such factors as reduction in breakdown voltage of the memory element due to miniaturization of the memory element, the higher threshold voltage of the ion-implanted memory cell is limited to about 2 to 3V. It was On the other hand, the lower threshold voltage in the memory cell in which the ion implantation is not performed is a voltage such as about 1V, so the difference Δth between the high threshold voltage and the low threshold voltage is about 1.5. It becomes a small voltage like V. Therefore, in the read operation, when the word line to which the control terminal of the memory cell is coupled is set to a selection level such as about 5V, the memory cell having the higher threshold voltage is turned on. Will end up.

In order to solve this, the present invention or the like previously provides a voltage limiting circuit in the X address decoder or the word line corresponding to each word line, and sets the potential of the word line at the time of read operation,
A method of limiting (clamping) the following voltage to the higher threshold voltage of the memory element subjected to ion implantation was devised.

However, in the above method, since the voltage control circuit is provided for each word line, the number of circuit elements increases and the word line selection level is clamped,
It becomes difficult to carry out a stress test for aging the memory element, and the reliability of the mask ROM is lowered.

An object of the present invention is to provide a semiconductor memory device having an improved read operation margin and improved reliability with a simple circuit configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is,
A voltage clamp circuit whose clamp operation is controlled by a test signal is provided, and the selection level of the word line is set according to the output voltage of the voltage clamp circuit.

[Action]

According to the above-mentioned means, in the normal read operation, the selection level of the word line is clamped to a predetermined voltage equal to or lower than the higher threshold voltage of the memory cell, so that the read margin of the mask ROM can be improved and During the stress test, since the clamping of the selected level of the word line can be released, the stress test for aging the memory cells can be performed.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of a mask ROM to which the present invention is applied. The circuit elements that make up each circuit block in FIG.
It is formed on a single semiconductor substrate such as single crystal silicon by a CMOS circuit manufacturing technique.

In the mask ROM of this embodiment, the information of the memory cell is read in units of 4 bits. Data of 2 bits each out of 4 bits which is a unit of reading,
It is stored in the memory arrays M-ARY1 and M-ARY2. Furthermore, the sense amplifiers SA0 to SA3 and the data output buffer DO are associated with each of the 4 bits that are the unit of reading.
B is provided. In the read operation, a word line selection level clamp circuit WLVC is provided to clamp the voltage level of the word line selection timing signal,
A test pad () for supplying a stress test mode signal () is provided to release the clamp operation during the stress test of the memory cell.

The memory array M-ARY1 has m word lines W0 to Wm-1 arranged horizontally in FIG. 2 and 2 × n data lines D00 to D0n-1 and D10 to D1n arranged vertically. −
1 and n common source lines CS0 to CSn-1 and 2 × m × n memory MOSFETs Qm, which are memory cells arranged at the intersections of the word lines and the data lines.

In the memory array M-ARY1, the control gates of the memory cells arranged in the same row have corresponding word lines W0 to Wm−.
Combined with 1. A word line selection signal formed by an X address decoder XDCR described later is supplied to each of these word lines W0 to Wm-1.

On the other hand, the drains of the memory cells arranged in the same column are
Data line D00 to D0n-1 or D10 to D1n-1 every other column
Is combined with The sources of the memory cells coupled to the data lines D00 and D10 or D0n-1 and D1n-1 are coupled to the corresponding common source lines CS0 to CSn-1 respectively.
In this way, the data lines and the common source lines are alternately arranged, and each data line has an end data line D00 and Dn-1.
Except for, the drains of the memory cells to which adjacent Y addresses are assigned are commonly connected.

The data lines D00 to D0n-1 are connected to the common data line CD0 via switching MOSFETs Q5, Q10, Q11, etc., which are typically shown in the column switch CSW. Also, the data line D
10 to D1n-1 are common data lines through the switching MOSFETs Q7 and Q8 which are typically shown in the column switch CSW.
Connected to CD1. Similarly, common source lines CS0 to CSn-1
Column switch CSW is a typical switch M
It is connected to the ground potential of the circuit through OSFETs Q6, Q9, Q12 and the like.

The gates of these switch MOSFETs Q5 to Q7 to Q8 to Q10 are commonly connected, and corresponding data line selection signals Y0 to Yn-1 are supplied from a Y address decoder YDCR described later.

Although not particularly limited, the above data lines D00 to D0n-1,
A load MOS is connected between D10 to D1n-1 and the power supply voltage Vcc of the circuit.
FETQ1 to Q3 are provided. The MOSFETs Q1 to Q3 act as resistance elements having a predetermined conductance by supplying a predetermined bias voltage Vb to their gates.

The X address signals AX0 to AXi supplied from the outside are input to the X address buffer XADB. X address buffer
The XADB forms a complementary internal address signal including an internal address signal having the same phase as the external address signal and an internal address signal having the opposite phase, and supplies the complementary internal address signal to the X address decoder XDCR.

The X address decoder XDCR decodes these complementary internal address signals and synchronizes with one word line in synchronization with the word line selection timing signal φw supplied from the timing control circuit TC via the word line selection level clamp circuit WLVC. Form a word line selection signal for selecting. Further, in the X address decoder XDCR, in the stress test mode for performing aging or the like, an inversion signal ST of the low level stress test mode signal supplied from the external test apparatus through the test pad ▲ ▼ is input by the inverter circuit N3. To be done. When the inverted signal ST of the stress test mode signal is set to the high level, the X address decoder XD
CR sets all word lines to the selected state at the same time.

Since the test pad ▲ ▼ to which the stress test mode signal ▲ ▼ is supplied is coupled to the power supply voltage Vcc of the circuit through the high resistance in the normal state where the mask ROM is used, the stress test mode signal ▲ ▼ Normally becomes a high level, and the inverted signal ST by the inverter circuit N3 becomes a low level. When performing a stress test on a memory cell, a low-level stress test mode signal ▲ ▼ (that is, its inverted signal ST is high level) is supplied to the test pad ▲ ▼ from an externally connected test device. At the same time, the power supply voltage Vcc is set to a relatively high voltage because of an engine or the like.

The stress test mode signal ▲ ▼ is also supplied to the word line selection level clamp circuit WLVC as it is. The word line selection level clamp circuit WLVC clamps the voltage level of the timing signal φx supplied from the timing control circuit TC in the normal read operation mode in which the stress test mode signal is at high level, and the word line selection timing signal φw Is supplied to the X address decoder XDCR. At this time, the clamp voltage of the word line selection timing signal φw is set to a voltage close to a relatively high threshold voltage of the memory cell which does not turn on the ion-implanted memory cell. This allows
In the normal read operation mode, it is prevented that a memory cell, which has a relatively high threshold voltage due to the high level of the word line selection level, is erroneously turned on and is erroneously read. Also, stress test mode signal ▲
In the stress test mode in which ▼ is set to the low level, the clamp operation of the word line selection level clamp circuit WLVC is stopped, and the high level of the word line selection timing signal φw becomes a voltage such as a relatively high power supply voltage Vcc. Become.

The Y address signals AY0 to AYj supplied from the external terminals are
Input to Y address buffer YADB. The Y address buffer YADB forms a complementary address signal composed of an internal address signal having the same phase as the external address signal and an internal address signal having the opposite phase, and supplies the complementary address signal to the Y address decoder YDCR. The Y address decoder YDCR decodes these complementary address signals, forms data line selection signals Y0 to Yn-1 for selecting two data lines and one common source line, and supplies them to the column switch CSW. To do. For example, when the data line selection signal Y0 is set to the high level by the Y address decoder YDCR, the switch MOSFETs Q5 to Q7 are simultaneously turned on. As a result, the MOSFET Q
The ground potential of the circuit is supplied via 6 and is coupled to the selected word line and selected data lines D00 and D10 2
Information stored in one memory cell is read out to the common data lines CD0 and CD1. At this time, the memory cells connected to the selected word line and other data lines are not supplied with the ground potential of the circuit because the switch MOSFETs provided in the corresponding common source lines are in the off state. It is turned off. By such common source line selection operation,
All the memory cells provided between the selected data line D10 and the common source line CS1 are also inactivated. Therefore, the data line D10 and the data line D10 are common source line CS0.
And a potential according to the stored information of the memory cell selected by the word line.

Also, when the selection signal Y1 is set to the high level by the Y decoder YDCR, the switch MOSFETs Q8 to Q10 are simultaneously turned on. As a result, the common source line CS1 is connected to the MOSFE
The ground potential of the circuit is supplied via TQ9, and the storage information of the two memory cells coupled to the selected data lines D10 and D01 is read to the common data lines CD1 and CD0. At this time, as in the case described above, the memory cell coupled between the selected data line D10 and the common source line CS0 and the data line D01 and the common source line CS2 has a corresponding switch.
Inactive because MOSFETs Q6 and Q11 are turned off. Therefore, the data lines D10 and D01 are provided between the respective data lines and the common source line CS1, and have potentials according to the stored information of the two memory cells selected by the word line.

With the configuration of the memory array M-ARY1 as described above,
Even though many memory cells are connected to one word line, only the current according to the stored information of the memory cells connected to the selected data line and the common source line flows, so that the power consumption is reduced. It is possible to reduce. Further, by the selection operation according to the Y address of the common source line, it is possible to combine the memory cells to which adjacent Y addresses are assigned to one data line, and it is possible to realize a high density arrangement of the memory cells. .

The storage MOSFET Qm has different threshold voltages according to the stored information. That is, although not particularly limited, in the memory cell in which the memory information of logic “1” is stored, the selective ion implantation is performed by using the mask means which is optionally manufactured according to the user. Therefore, the memory cell is made to have a relatively high threshold voltage by introducing an impurity of the same conductivity type as that of the semiconductor substrate into the semiconductor substrate (channel region) under the gate electrode. The writing process using such an ion implantation technique is an almost final process of a semiconductor integrated circuit formed on a semiconductor wafer, for example, an ion implantation process through a gate electrode of a MOSFET that becomes a memory cell after forming a data line made of aluminum. It is carried out by.

Common data lines CD0 and C through selected data lines
The read signal of the memory cell output to D1 is supplied to one input terminal of the sense amplifiers SA0 and SA1. The other input terminal of the sense amplifiers SA0 and SA1 has a reference voltage
Vref is supplied. This reference voltage Vref is between a low level read signal from a memory cell having a relatively low threshold voltage and a high level read signal from a memory cell having a relatively high threshold voltage in the memory array. Is set to almost the middle level. The sense amplifiers SA0 and SA1 are operated by the timing signal φce supplied from the timing control circuit TC, determine the read signal of the memory cell by the reference voltage Vref, and output the data output buffer DOB as a high level / low level binary signal.
Supply to.

Although not particularly limited, the above X address decoder circuit XD
A memory array M-ARY2 shown by a dotted line in FIG. 2 is symmetrically provided on the left side of the CR. This memory array M-ARY2 is provided with a Y address decoder circuit like the memory array M-ARY1.

By dividing the memory array M-ARY in this manner, the length of one data line and word line can be shortened, and the number of memory cells coupled to the data line and word line can be reduced, so that the operation speed can be increased. .

The read operation is also performed in the memory array M-ARY2 at the same time, and another 2-bit read data is supplied to the data output buffer DOB via the common source lines CS2, CS3 and the sense amplifiers SA2, SA3.

The data output buffer DOB is activated by the timing signal φoe supplied from the timing control circuit TC, further amplifies the read data supplied from the sense amplifiers SA0 to SA3, and then externally outputs via the output terminals D0 to D3. Output to the device.

FIG. 1 is a circuit diagram showing an embodiment of the word line selection level clamp circuit WLVC of the mask ROM of FIG. In the figure, the MOSFET in which a straight line is added between the source and drain is an N-channel depletion type MOSFET.
The MOSFET with an arrow added to the channel (back gate) part is a P-channel type, and other MOSFETs
The SFET is an N channel type.

A timing signal φ formed by the chip control signal ▲ ▼ in the timing control circuit TC, which is set to low level when the mask ROM is not selected and is set to high level when selected.
x is inverted by the inverter circuit N1 and input to one input terminal of the AND gate circuit AG1. The other input terminal of the AND gate circuit AG1 has a test pad ▲
Stress test mode signal supplied from ▼▼
Is entered. The output signal of the AND gate circuit AG1 is a P-channel MOSFE whose source is coupled to the power supply voltage Vcc.
It is supplied to the gate of TQC1 and also to the gate of an N-channel MOSFET QC7 provided between the ground potential of the circuit and the output terminal. A depletion type MOSFET QC2 is provided between the MOSFET QC1 and the output terminal of the circuit.
Between the output terminal of the circuit and the ground potential, depletion type MOSFETs QC3, QC4 and N channel MOSFE in series form.
TQC5 is established. The source and gate of MOSFET QC3 are connected together and further coupled to the gate of MOSFET QC2 above. The conductance of the MOSFET QC3 is set to a value sufficiently smaller than the conductance of the MOSFET QC2. Further, the MOSFET QC3 is brought into an operating state in a saturation region of its operating characteristic and acts as a constant current source for flowing the current i. MO
The gate of SFETQC4 is coupled to the output terminal of the circuit. The MOSFET QC4 receives the constant current i and acts as a constant voltage source for supplying a constant voltage Vn to the gate of the MOSFET QC2. The stress test mode signal ▲ ▼ is supplied to the gate of MOSFET QC5.

As mentioned above, in the normal read operation mode,
The stress test mode signal ▲ ▼ is set to high level,
A timing signal φx, which is generated in synchronization with the chip selection signal ▲ ▼, is supplied from the timing control circuit TC to the word line selection level clamp circuit WLVC. Chip selection signal ▲
When ▼ is at a high level, that is, when the timing signal φx is at a low level when the mask ROM is not selected, the AND gate is set by the high level of the inverted signal of the timing signal φx by the inverter circuit N1 and the high level of the stress test mode signal ▲ ▼. The output signal of the circuit AG1 becomes high level. Therefore, the P-channel MOSFET QC1 is turned off and the N-channel MOSFETs QC6 and Q are
C7 is turned on, and word line selection level clamp circuit
Word line selection timing signal φw which is an output signal of WLVC
Is at a low level like the ground potential of the circuit. As a result, all the word lines are in the non-selected state.

Further, when the chip selection signal ▲ ▼ is low level, that is, the mask ROM is in the selected state and the timing signal φx is high level, the output signal of the AND gate circuit AG1 becomes low level due to the low level of the inverted signal by the inverter circuit N1. Become. Therefore, the P channel
MOSFET QC1 turns on and N channel MOS
FETQC6 and QC7 are turned off, and a predetermined clamp operation is performed. That is, the stress test mode signal ▲
By the high level of ▼, the N-channel MOSFET QC5 is in the ON state, and the word line selection level clamp circuit WLVC
The voltage Vw of the word line select timing signal φw is the output signal of at _{i = β (W 4 / L} 4) × conditions _{{(Vw-V TH4) Vn} -Vn 2/2} and the relationship is established, Clamped. Where β, W ₄ , L ₄ and V _TH4 are depletion type MOSFETs.
QC4 channel conductivity, channel width, channel length and threshold voltage.

This can be qualitatively explained as follows.
That is, the constant current formed by operating the MOSFET QC3 in the saturation region is passed through the MOSFET QC4 to form the constant voltage Vn. Based on this constant voltage Vn, the output voltage φw is
It is clamped to a voltage higher by the threshold voltage of MOSFET QC2. The MOSFET QC2 has a MOSFE as the constant current source.
Since the load circuit including TQC3 and the like is provided, it is possible to prevent the output level from being set to a high level such as the power supply voltage Vcc due to the leakage current with respect to the capacitive load, such as an open source output. Further, the output voltage φw is supplied to the gate of the MOSFET QC4 as a resistance means for forming the constant voltage Vn, so that the gate voltage can be stabilized. That is, when the output voltage φw is about to increase
The conductance of MOSFET QC4 increases and the constant voltage Vn decreases. Conversely, when the output voltage φw is about to decrease, the conductance of the MOSFET QC4 decreases and the constant voltage Vn increases. By such a negative feedback operation, the output voltage φw can be made highly stable so as to satisfy the above conditional expression.

The word line selection timing signal φw is used as the word line driving MOSFET QC8 which constitutes the unit circuit of the X address decoder XDCR.
It is also supplied as the operating voltage for QC9 to all unit circuits. The gate of MOSFET QC9 has NOR gate circuit NOR
Of the inverter circuit N2 is supplied to the gate of the MOSFET QC8. The output signal of the AND gate circuit AG2 whose output signal is at a high level is supplied to one input terminal of the NOR gate circuit NOR by a combination of predetermined internal address signals. In the case of FIG. 1, inverted signals of the internal address signals ax0 to axi are input to the AND gate circuit AG2 corresponding to the word line W0. To the other input terminal of the NOR gate circuit NOR,
An inverted signal ST of the stress test mode signal is supplied. The inverted signal ST is supplied to all NOR gate circuits NOR of the X address decoder XDCR including this unit circuit. When the word line is in the non-selected state, the output signal of the AND gate circuit AG2 and the inversion signal ST of the stress test mode signal are both low level, and therefore the output signal of the NOR gate circuit NOR becomes high level. As a result, the MOSFET QC9 is turned on, the MOSFET QC8 is turned off by the low level output signal of the inverter circuit N2, and the potential of the word line W0 is turned to the low level by the ground potential of the circuit supplied through the MOSFET QC9.

When the word line W0 is selected, the inverted internal address signals ax0 to axi all become high level, and the output signal of the AND gate circuit AG2 becomes high level. As a result, the output signal of the NOR gate circuit NOR becomes low level, the MOSFET QC9 is turned off, and the MOSFET QC8 is turned on by the high level output signal of the inverter circuit N2. The threshold voltage V _{TH of the} MOSFET QC8 is designed so that Vcc-Vw> V _TH , so the word line drive MOSFET
The output voltage of QC8 is almost clamped Vw voltage.

On the other hand, in the stress test mode, since the low-level stress test mode signal ST is supplied from the external test equipment, the MOSFET of the word line selection level clamp circuit WLVC is
QC5 turns off. Further, the output signal of the AND gate circuit AG1 becomes low level, the MOSFETs QC6 and QC7 are turned off, and the QC1 is turned on. As a result, the clamp operation by the depletion type MOSFETs QC2 to QC4 is not performed, and the word line selection timing signal φw is set to MOSF.
The voltage Vcc 'supplied via ETQC1 and QC2 results in a high level that is not clamped. In the stress test mode, this voltage Vcc 'is set to a higher voltage than the normal operating voltage, for example, a relatively high voltage such as 9 V, and an accelerated test such as aging of memory cells is performed.

In the stress test mode, the trace test mode signal is supplied to all NOR gate circuits NOR of the X address decoder.
Since the high level of the inverted signal ST of ▼ is supplied, the output signal becomes low level, and the MOSFETs of all unit circuits are
QC8 is turned on by the high level output signal of the inverter circuit N2, and MOSFET QC9 is turned off.
Therefore, the high level of the word line selection timing signal φw is transmitted to all the word lines as it is, and the stress test is performed.

As shown in the above embodiment, the present invention is masked.
When applied to ROM, the following effects are obtained. That is, (1) the voltage level of the word line selection timing signal supplied to the address decoder that selects and specifies the word line is
In the normal read operation excluding the stress test, the read margin of the mask ROM can be improved by clamping the voltage near the higher threshold voltage of the memory cell.

(2) Since the voltage limiting circuit is provided in common to all word lines, it is possible to reduce the number of circuit elements for clamping the word line selection level.

(3) Since the clamping operation of the word line selection timing signal φw by the voltage limiting circuit is stopped during the stress test, it is possible to perform the stress test for aging the memory cells and the like.

(4) According to the above items (1) and (3), the higher threshold voltage of the memory element can be made relatively low without causing erroneous reading of the memory cell. As a result, it is possible to realize high integration and high integration, and it is possible to obtain an effect that a mask ROM having a large storage capacity and high reliability can be provided to the user.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, MOSFETQC
A constant voltage Vn may be supplied to the second gate. Further, a constant voltage Vn is formed by the MOSFET QC3 as the constant current source and the MOSFET QC4 as the resistance means, and it is supplied to the gate of the tiption type MOSFET QC2,
The clamp voltage may be obtained from the source. In this case, in order to stop the operation during the tres test, the circuit power supply voltage Vcc may be supplied to the gate of the MOSFET QC2 instead of the constant voltage Vn. In addition, the specific circuit configuration of the word line selection level clamp circuit WLVC of FIG. 1 is a comparison of memory cells which have been ion-implanted at the level of the word line selection timing signal φw in the read operation mode except the stress test mode. Various embodiments can be adopted under the condition that the voltage is clamped to a voltage close to an extremely high threshold voltage. Further, the word line selection level clamp circuit WLVC may be provided with a plurality of circuits due to its driving capability or other reasons. Also,
In the case of this embodiment, the memory array is a 2-mat system and has a read function in units of 4 bits, but it is also possible to read in units of 1 bit or 8 bits or more. Various embodiments such as the configuration of the memory array and its peripheral circuits and the combination of each control signal can be adopted.

In the above description, the case where the invention made by the present inventor is mainly applied to the mask ROM which is the field of application which is the background of the invention has been described, but the invention is not limited to this and is incorporated in, for example, a microcomputer or the like. The same can be applied to ROM for storing programs. The present invention can be applied to a semiconductor memory device including a memory element that has two different threshold voltages according to at least stored information.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application. That is, the voltage level of the word line selection timing signal supplied to the address decoder that selects and specifies the word line is clamped to a voltage near the higher threshold voltage of the memory cell in the normal read operation excluding the stress test. Then, by adding a relatively simple circuit,
It is possible to realize a semiconductor memory device such as a mask ROM with improved read margin and improved reliability.

[Brief description of drawings]

1 is a circuit diagram showing an embodiment of a word line selection level limiting circuit of a mask ROM to which the present invention is applied, and FIG. 2 is an example of a mask ROM including the word line selection level limiting circuit of FIG. It is a block diagram which shows an Example. WLVC …… Word line selection level clamp circuit, QC1 …… P
Channel MOSFET, QC2 to QC4 ... Depletion type MOSF
ET, QC5 to QC9 …… N-channel MOSFET, N1 to N2 …… Inverter circuit, AG1 to AG2 …… And gate circuit, NOR ……
NOR gate circuit. M-ARY1 to M-ARY2 ... Memory array, Qm ... Memory cell, Q1 to Q12 ... N-channel MOSFET, CSW ... Column switch, XADB ... X address buffer, XDCR ... X address decoder, YADB ... Y address buffer, YDCR ...
Y address decoder, SA0 to SA3 ... Sense amplifier, DOB
...... Data output buffer, TC ...... Timing control circuit,
N3 ... Inverter circuit, PST ... Test pad,

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isamu Kobayashi 1450 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Musashi Factory (72) Inventor Hisahiro Morinuchi 1450, Kamimizuhonmachi, Kodaira, Tokyo Hitachi, Ltd. Inside the Musashi Factory (72) Inventor Masahiro Ogata 1448, Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Ultra Engineering Co., Ltd.

Claims (4)

[Claims] 1. A memory array formed by matrix-arranging storage elements having a relatively high threshold voltage or a relatively low threshold voltage according to stored information, and a power supply voltage according to a test signal. Alternatively, the voltage clamp circuit includes a voltage clamp circuit that selectively outputs a predetermined intermediate voltage, and a word line selection circuit in which the selection level of the word line is set by the output voltage of the voltage clamp circuit. A semiconductor memory device provided in common to a line selection circuit. 2. The voltage clamp circuit is connected in series with a first depletion type MOSFET (QC2) and the MOSFET (QC2), and is operated in a saturation region.
Depletion type second MOSFET (QC3) whose conductance is set smaller than that of the other MOSFET (QC2).
And a third MOSFET (QC4) whose gate is coupled to the source of the first MOSFET (QC2).
The output voltage is obtained from the source of the first MOSFET (QC2) and the first MOSFET (QC2) and the third MOSFET (QC
The 4) is connected with P-channel type and N-channel type switch MOSFETs (QC1, QC5) which are controlled according to a test signal and respectively supply a power supply voltage and a ground potential of the circuit. 2. The semiconductor memory device according to item 1. 3. The memory element is made to have a relatively high threshold voltage by selectively introducing an impurity of the same conductivity type as that of the substrate gate into its channel region by an ion implantation method. The semiconductor memory device according to claim 1 or 2, wherein: 4. The word line selection circuit according to claim 1, wherein the plurality of word line selection circuits are configured to simultaneously output a high level word line selection signal during a test operation according to a test signal. The semiconductor memory device according to item 2 or 3.