JPH084322B2 - Frame synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field of use B Outline of the invention C Conventional technology (Figs. 2 to 7) D Problems to be solved by the invention E Means for solving problems (Fig. 1) F Action G Implementation Example (Fig. 1) H Effect of the invention A Industrial field of use The present invention relates to a frame synchronization apparatus suitable for use in sampling a signal provided with a specific frame synchronization pattern.

B Outline of the Invention The present invention is an apparatus for recording / reproducing a signal provided with a specific frame synchronization pattern in a VTR or the like, and processing is performed by sampling this input signal at a frequency different from the clock frequency of the frame synchronization pattern. By supplying this sampling clock to the PLL to form a clock with the frequency of the frame synchronization pattern and detecting the frame synchronization pattern using this formed clock, good frame synchronization can be obtained and optimal sampling can be performed. It enables processing.

C Conventional technology MUSE as a new transmission system for so-called high-definition television
(Multiple Sub-Nyquist Sampling Encoding) system has been proposed (Foundation Memorial Lecture Proceedings, "New Transmission System for High-Definition Television (MUSE)", Yuichi Nikakan, June 6, 1984, NHK Comprehensive Technical Research Institute of Broadcast Science).

That is, in this method, for example, the second
When there are the luminance signal Y and the color difference signals C _N and C _W as shown in FIGS. A to C, the color difference signals C _N and C _W among them are respectively compressed by a time axis of 1/4, and each is arranged in line order. Insert the corresponding luminance signal Y in the horizontal blanking period at the leading end of the corresponding luminance signal Y and set the TC as shown in FIG.
Form the I signal. This TCI signal is changed to 6 as shown in FIG.
Sampling is performed at 4.8 MHz, and one sample is extracted from every four samples of this sampling data to form a sub-Nyquist sampling signal which is interleaved with each other as shown in FIG. Therefore, the frequency of sub-Nyquist sampling is 16.2
The baseband signal bandwidth, which was originally 20MHz, can be compressed to 8.1MHz. This signal is frequency-modulated (FM), for example, and transmitted via broadcasting hygiene or the like.

On the other hand, on the receiving side, the received signal is demodulated and the 8.1 MHz sub-Nyquist sampling signal is extracted. This signal is sampled at 16.2 MHz, this sampling data is written in the memory as shown in E of the above figure, and these data and the data of the non-sampling point indicated by the blank are converted as shown in G of the same figure. Interpolated and D in the above figure
The TCI signal as shown in is restored. Then, from this signal, the luminance signal Y and the pigment signal C _N as shown in A to C of the above-mentioned figure are obtained.
・ C _W can be taken out.

In this way, it becomes possible to transmit a high-definition television signal by the MUSE system by, for example, one-channel sanitary broadcasting having a bandwidth of 27 MHz.

By the way, on the receiving side, the 16.2MHz clock signal for obtaining sampling data is 16.2M on the transmitting side.
It must be exactly in phase with the Hz clock. This is particularly because the sampling on the transmission side is sub-Nyquist sampling, and there is a possibility that accurate sampling data cannot be obtained if the phase is shifted.

A part of the horizontal blanking period of the signal transmitted there (the remaining part in which the color difference signal is inserted) is used as a reference for phase synchronization and the horizontal difference is also used to determine the color difference signals C _N and C _W included in the horizontal period. A synchronization signal HD is provided. That horizontal synchronizing signal HD is specifically formed between the time (1) of the next clock at the end of the luminance signal Y as shown in FIG. 3 up to the point (12), the color difference signals, respectively C _N · C Two types of waveforms corresponding to _W are used. And time point (1) is a transition point,
Each of them is an intermediate level between the terminal level of the previous signal (luminance signal Y) and the next level, and one of the two types has an intermediate level between the level of 64/256 of the maximum amplitude of the video signal. On the other hand, the level is intermediate to the level of 192/256. Next, at the time points (2) to (5), the level of 64/256 is continued on the one hand and the level of 192/256 is continued on the other hand. Further, at time (6), the levels of 128/256 are set for both one and the other. Next, at points (7) to (11), on the other hand, 192/25
6 levels are continuous, while 64/256 levels are continuous. Further, the time point (12) is also a transition point similar to the above-mentioned time point (1), and is set to an intermediate level between the level of the leading edge of the next signal (color difference signal C) and the level of the previous level. The level is intermediate to the level of 256, while the level is intermediate to the level of 64/256. Then, the color difference signal C _N or C _W continues from the time of the next clock.

The horizontal synchronizing signal HD is inserted with the same polarity (positive polarity) as the video signal (luminance signal Y, color difference signals C _N and C _W ). This is because, for example, when a sync signal of opposite polarity such as the NTSC system is used, the overall amplitude of the signal expands, especially FM
This is to prevent the band from expanding when signals are transmitted.

Then, regarding the conventional horizontal synchronization signal HD, time (3)-
The period (9) is set as a phase detection portion, and the level A at the time point (4), the level B at (8), and the level C at (6) are detected during this period. The phase error can be detected with the characteristic shown in FIG. However, as is clear from this figure, the phase synchronization by the horizontal synchronization signal HD is not performed unless it is within ± 1 clock period from the synchronization point in advance.

Therefore, a frame synchronization signal for previously pulling in the above conditions is separately provided. That is, FIG. 5 shows a frame synchronization pattern provided at the 605th and 606th positions in the 1125 horizontal periods of the high definition television.

In the figure, a horizontal synchronization signal HD is provided with a blank period of an arbitrary length continuously, and thereafter, 17.5 pairs of pulses for inverting the signal to the highest level and the lowest level are provided every four clock periods. After that, the pulse of the highest or lowest level of the 16 clock signal is provided, and then 8
A pulse is provided that is the inverse of the previous portion of the clock period. Immediately after the pulse of 8 clock periods, the horizontal synchronizing signal HD of the next horizontal period is continued. The frame synchronization signal is provided in a mutually inverted manner in the 605th and 606th horizontal periods, and the leading edge of the pulse is used as a reference for phase synchronization in 16 clock periods of the frame synchronization signal.

Therefore, to obtain synchronization from the above signals, first detect the above frame synchronization pattern of the signals, use this detection signal to pull in synchronization within ± 1 clock period, and then use the horizontal synchronization signal HD to perform phase synchronization. Try to apply Therefore, conventionally, for example, a circuit as shown in FIG. 6 has been proposed.

In the figure, the above-mentioned received and demodulated MUSE signal is supplied to an input terminal (1). This signal is supplied to the AD conversion circuit (2), and the clock signal from the voltage controlled oscillator (VCXO) (3) whose reference oscillation frequency is 16.2 MHz is AD.
The signal supplied to the conversion circuit (2), sampled by the clock signal, and digitally converted into, for example, 8 bits is taken out to the output terminal (4) and supplied to a restoration processing circuit (not shown) such as a memory in the subsequent stage. .

Further, the signal from the conversion circuit (2) is supplied to the frame synchronization pattern detection circuit (5), and the above-mentioned clock signal is also supplied to this detection circuit (5) to change the least significant bit of the digital data as a clock signal. The frame synchronization signal is detected by making a determination according to The detected frame synchronization signal is supplied to the frame phase detection circuit (6). Further, the above clock signal is supplied to the 1 / 540,000 frequency divider (7) to form a signal having a frame frequency (30 Hz). This signal is supplied to the detection circuit (6), and the detected phase error signal is added to the VCXO (3) through the adder (8).
Is fed back to and a sync loop with the frame sync signal is formed.

Further, the signal from the conversion circuit (2) is supplied to the phase detection circuit (9) of the horizontal synchronizing signal HD, and the detected phase error signal is supplied to the adder (8) through the low pass filter (LPF) (10). .

As a result, the frame synchronization pattern in the signal is first detected, synchronization is pulled within ± 1 clock period by this detection signal, and further phase synchronization is applied using the horizontal synchronization signal HD.

However, on the receiving side described above, the above-mentioned 8.1 MHz sub-Nyquist sampling signal (shown by the solid line in FIG. 7) was received by 16.2.
When the signal is sampled at MHz, the signal band spreads up and down 8.1 MHz around 16.2 MHz as shown by the chain line in the figure, and becomes a band of 8.1 to 24.3 MHz. On the other hand, the band of the signal is generally not completely at 0 level at that frequency, for example, at the point where the response is lowered by 6 dB, and there is a low level signal outside thereof. Therefore, in the above example, signals overlap each other around 8.1 MHz, and so-called folding noise due to these weights may cause interference on the screen.

Therefore, the applicant of the present application has started the technique of eliminating the above-mentioned interference by performing sampling at a higher frequency obtained by an integer ratio with the frequency (16.2 MHz) of sub-Nyquist sampling on the transmission side. That is, 16.2MHz = 480f above
20.25MHz = 600f for _H (f _H is horizontal frequency: 33.75kHz)
By sampling using the _H clock signal, the information of the Samb Nyquist sampling can be satisfactorily taken out, and its signal band is 12.15 to 28.35 MHz as shown by the broken line in the above figure. Can be completely separated from. This makes it possible to eliminate interference caused by aliasing noise.

However, in the above-described synchronization circuit, when performing AD conversion sampling is performed at the clock signal of 600f _H, for detection operation in the detection circuit of the frame synchronization pattern (5) is in units of 4 clock 480f _H sync There is a possibility that pattern detection may not be performed smoothly.
That is, 4 clocks of 480f _H corresponds to 5 clocks of 600f _H , and it is extremely inconvenient in the case of digital processing to use 5 which is not a power of 2 as a unit. Note for example 480f 2 times 960f _H = 32.4MHz above disadvantages if Re use a clock signal of the _H is eliminated, so the band of the signal is very high frequency, the greater the problems in circuit design.

D Problems to be Solved by the Invention Conventional synchronization has been performed by the method as described above. Therefore, there are problems that interference due to aliasing noise occurs and that the frame synchronization pattern cannot be detected well.

E Means for Solving the Problems In the present invention, an input signal (input terminal (1)) in which a frame same pattern formed by a clock of a first frequency (480f _H ) is inserted is set to the first frequency. Sampling at a higher second frequency (600f _H ) clock (AD conversion circuit (1
2)) and the processing is performed, an oscillator (VCXO (13)) for the clock of the second frequency and a PLL for supplying the clock of the second frequency to form the clock of the first frequency. (18), a synchronization detection circuit (5) for detecting the frame synchronization pattern from the input signal by using the formed clock of the first frequency, the detected frame synchronization pattern and the second A phase detection circuit (6) for detecting a phase difference from a frequency signal of the frame synchronization pattern obtained by dividing a frequency clock, and controlling the oscillator by using a detection output of the phase difference detection circuit. Is a frame synchronizer for synchronizing the clock of the second frequency generated by the oscillator with the input signal.

According to this device, good sampling can be performed using the second clock signal having a frequency higher than the frequency of the first clock signal, and at the same time, a predetermined frequency can be obtained by the PLL from the second clock signal. Since the first clock signal is formed to detect the frame synchronization pattern, it is possible to always detect good frame synchronization, and further use this frame synchronization signal to generate the second clock signal. Good synchronization can be applied.

G Example FIG. 1 shows a VTR recording / reproducing apparatus using the present invention. In this circuit, a VTR input signal from an input terminal (1) is supplied to an AD conversion circuit (12) through a gain control circuit (11). . Further, the clock signal from the VCXO (13) having a reference oscillation frequency of 20.25 MHz is supplied to the conversion circuit (12) to perform sampling and digital conversion. The converted signal is supplied to the magnetic head (22) through the recording amplifier (21) and recorded on the tape (23). In addition, this tape (2
The signal reproduced by the head (22) from 3) is supplied to the DA conversion circuit (25) through the reproduction processing circuit (24), and the 20.25 MHz clock signal is also converted from the terminal (26) to the conversion circuit (25).
To the output terminal (4).

Furthermore, the signal from the conversion circuit (12) is the amplitude detection circuit (4
1), which is supplied to point A and B of the horizontal synchronizing signal HD described above.
A difference between the levels of the points is detected, and the difference data is supplied to the comparison circuit (42). The digital reference data from the setting circuit (43) is supplied to the comparison circuit (42), and the comparison output is supplied to the control terminal of the gain control circuit (11) through the integration circuit (44). This allows the automatic gain control loop (1
4) is formed, and the amplitude of the signal supplied to the AD conversion circuit (12) is optimized. In this example, the output of "1" and "0" from the comparison circuit (42) is integrated to obtain the analog control voltage. However, the output of the detection circuit (41) is DA converted, and thereafter the analog processing is performed. Alternatively, the control voltage may be obtained.

Further, the signal from the input terminal (1) is supplied to the comparator (15), and is discriminated by the reference level from the terminal (16) to be a binary signal. This binary signal is supplied to the frame synchronization detection circuit (5). On the other hand, the signal from the VCXO (13) is divided by the 1/20 frequency divider (17) and supplied to the phase detector (81), and the reference oscillation frequency of the VCXO (8
The clock signal from 2) is frequency-divided by the 1/16 frequency divider (83) and supplied by the phase detector (81), and this check output is passed through the low-pass filter (84) to the control terminal of the VCXO (82). Supplied. This creates a PLL (18), 20.25MHz
16/20 of 16.2MHz clock signal is formed. This signal is supplied to the frame synchronization detection circuit (5).

The detected frame synchronization signal is supplied to the frame phase detection circuit (6), and the signal from the VCXO (13) is divided by the 1/675000 frequency divider (19) to detect a 30 Hz signal. It is supplied to (6). This detects a frame phase error, and this detection signal is passed through the adder (8).
It is fed back to VCXO (5) to form a frame synchronization loop.

Further, the signal from the conversion circuit (12) is supplied to the phase detection circuit (9) of the horizontal synchronizing signal HD, and the detected phase error signal is supplied to the adder (8) through the LPF (10).

In this way, the frame synchronization and the phase synchronization with the horizontal synchronization signal HD are applied, but according to the above example, 600 f
Since to detect the frame synchronization pattern through 480f _H clock signal phase-synchronized from the clock signal _H, can be detected easily and satisfactorily frame synchronization pattern, is possible to apply good synchronization with a clock signal it can. In the above example, the frequency of the second clock signal is 60
Can be any frequency higher than the frequency of the first clock signal is not limited to 0f _H.

EFFECT OF THE INVENTION According to the present invention, good sampling can be performed using the second clock signal having a frequency higher than that of the first clock signal, and at the same time, the PLL can be used to perform predetermined sampling from the second clock signal. Since the first clock signal having the frequency of is formed to detect the frame synchronization pattern, it is possible to always detect good frame synchronization,
Further, it becomes possible to apply good synchronization to the above-mentioned second clock signal by using this frame synchronization signal.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of the present invention, and FIGS. 2 to 7 are diagrams for explaining a conventional device. (1) is an input terminal, (4) is an output terminal, (5) is a frame synchronization detection circuit, (6) is a frame phase detection circuit,
(9) is a horizontal synchronizing signal phase detection circuit, (12) is an AD conversion circuit, (13) is a voltage controlled oscillator, (15) is a comparator, (18) is a PLL, and (19) is a frequency divider.

Claims (1)

[Claims] 1. An input signal in which a frame synchronization pattern formed by a clock of a first frequency is inserted is sampled by a clock of a second frequency higher than the first frequency to perform processing. An oscillator of a clock of a second frequency, a PLL supplied with the clock of the second frequency to form the clock of the first frequency, and the input using the formed clock of the first frequency A synchronization detection circuit for detecting the frame synchronization pattern from the signal, and a phase detection for detecting a phase difference between the detected frame synchronization pattern and a signal of the frequency of the frame synchronization pattern obtained by dividing the clock of the second frequency. A circuit for controlling the oscillator using the detection output of the phase detection circuit to generate a clock of the second frequency generated by the oscillator. The click frame synchronization apparatus that synchronizes with the input signal.