JPH085220B2 - High-speed printing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to a recording head in which a plurality of recording elements corresponding to vertical dots of a dot matrix are arranged laterally at intervals of an integral multiple of a dot pitch. The present invention relates to a high-speed printing method for a printer that performs printing while moving the printer in the horizontal direction.

<Prior Art> Conventionally, as a printer having this type of recording head,
For example, an inkjet printer is known. In this ink jet printer, a digital recording signal is applied to a nozzle which is a recording element, and when the signal is "1", ink is ejected from the nozzle to obtain dot recording on recording paper. However, since the nozzles are vertically long due to the structure, if multiple nozzles are arranged in a vertical row corresponding to the vertical dots of the dot matrix, the printhead becomes too high, and if they are arranged in a vertical row, ink is supplied to each nozzle. Because of the difference in force, a plurality of nozzles corresponding to vertical dots are arranged laterally at intervals of an integral multiple of the dot pitch. In the example shown in FIG. It is ten times d (l = 10d). And, for example, the fifth
In order to print four dots vertically in one line with each nozzle while running the recording head H having the nozzles N1, N2, N3, N4 as shown in the figure at a speed v in the direction of the arrow, the recording signal corresponding to each dot That is, it is necessary to sequentially delay the print data by l / v and output the print data.

However, due to the CPU and memory, the processing of print data inside the printer is performed in 8-bit or 1-byte units, and the print data to be output is sent from the host in byte units regardless of the nozzle layout, and in print order. They are arranged in the row direction and stored at consecutive addresses in the memory.
Therefore, when the nozzle interval 1 is not 8n times the dot pitch d (n: integer) as shown in FIG. 5, it is necessary to shift the print data stored in the above memory for each nozzle bit by bit and output it to the nozzles. In this example, in the remainder of l / 8d, that is, in units of 2 bits, for the nozzle N1, N2: 2 bits, N
Print data must be shifted in the order of 3: 4 bits, N4: 6 bits. The conventional inkjet printer shifts the print data bit by bit by a program control method in which the CPU reads the print data byte by byte from the memory, bit-shifts the print data, and outputs the bit-shifted data to each nozzle. .

<Problems to be Solved by the Invention> However, in the above-described conventional inkjet printer, since bit shift of print data to be output to each nozzle is performed byte by byte by the shift register of the CPU, this processing requires a lot of time. It has a drawback that it is expensive and extremely inefficient, and high-speed printing cannot be performed.

Therefore, an object of the present invention is to provide a high-speed printing method capable of realizing high-speed printing and significantly improving the printer system efficiency by processing the bit shift of the print data at high speed.

<Means for Solving Problems> In order to achieve the above object, the high-speed printing method of the present invention is
Under the control of the processor, the recording head, in which a plurality of recording elements corresponding to the vertical dots of the dot matrix are arranged in the lateral direction at intervals of an integral multiple of the dot pitch, moves in the lateral direction relative to the recording paper. In a printer that outputs print data to each recording element while moving to perform printing, a memory that collectively stores the print data of each recording element at consecutive addresses in the printing order and a recording element that is input from this memory An array conversion circuit that bit-shifts the print data on a byte-by-byte basis based on a shift signal corresponding to the interval between the recording elements, and the shifted print data output from the array conversion circuit is stored at successive addresses for each recording element. After that, the shift signal is output under the control of the buffer memory for outputting to each recording element and the processor, Includes a DMA controller for controlling the direct transfer of print data between Li and the buffer memory,
The feature is that high-speed printing of print data is performed.

<Operation> As an example, the recording head includes four recording elements P1, P2, P3, and P.
When the four are arranged laterally at intervals of N times the dot pitch (N: integer), the processor prints the recording element P1 based on the value S of the remainder obtained by dividing N by 8, for example. A shift signal that shifts the print data of P2, P3, and P4 with respect to the data by S, 2S, and 3S bits respectively is output to the array conversion circuit. Next, the DMA controller transfers the print data collectively stored in the memory in consecutive addresses in the printing order to the buffer memory directly through the array conversion circuit, and the array conversion circuit records each print in response to the shift signal. The print data of the element is bit-shifted byte by byte, and the bit-shifted print data is stored in the buffer memory. Unlike the conventional program control method, the direct memory access method by the DMA controller has a high processing speed, and print data stored in the buffer memory in a state shifted according to the intervals of the recording elements. Is immediately output to each recording element, and printing is performed at high speed.

<Examples> Hereinafter, the present invention will be described in detail with reference to illustrated examples.

FIG. 1 is a block diagram of an inkjet printer adopting the high-speed printing method of the present invention. Reference numeral 1 is a block for controlling each block of the printer, and a plurality of nozzles corresponding to vertical dots of a dot matrix are dotwise in a horizontal direction. CP for controlling the lateral running of the recording head H (see FIG. 5) arranged at intervals l (l = N · d) that is an integer N times the pitch d
U, 2 is a RAM as a memory for collectively storing the print data of each nozzle in consecutive addresses in the printing order, and 3 is the print data of each nozzle input from the RAM 2 based on the shift signal corresponding to the interval l. Array conversion circuit for bit-shifting in byte units, 4 is this array conversion circuit 3
After storing the bit-shifted print data output from each of the nozzles at consecutive addresses, the RAM 5 serving as a buffer memory that outputs to each nozzle outputs the shift signal, and print data between the RAM 2 and RAM 4 It is a DMA (direct memory access) controller that controls direct transfer, and each block is a control bus 7 of the data bus 6.
Are connected to each other.

The nozzles are, for example, N1, N2, N3, N4 as shown in FIG.
Four cases, the above RAM2 is a first print data of each nozzle corresponding to one column of dots, for example, as shown in FIG. 4, Q ₁₁ one byte to the right end of the four column channels, Q _21, Q _31, alongside Q _41, stored in a continuous arranged in these subsequent bytes of print data to the print order in the row direction leftward (see a solid line grid in the drawing), the final print data Q printing one line _{After 1} n to Q ₄ n, “00H” is stored in byte units, and data for one subsequent printing line (not shown) is similarly stored one after another. The CPU 1 has a nozzle interval l = N.
A shift signal for shifting the print data of each nozzle by S, 2S, 3S bits is output to the print data of the reference nozzle based on the remainder S obtained by dividing the N value of d by 8, and the shift signal is received. The array conversion circuit 3 is the RAM 2
The print data stored in is bit-shifted in byte units. That is, in the case of N = 10 shown in FIG. 5, based on the remainder S = 2 of 10/8, as shown by the broken line in FIG. 4, for the reference first channel data Q ₁₁ , Q ₁₂ , ... , The second channel Q ₂₁ , Q ₂₂ , ... has 2 bits, and the third channel Q ₃₁ , Q
_32, ... is 4 bits, the 4-channel Q _41, Q _42, ... it is shifted to the respective backward by 6 bits, the shifted print data is stored in the printing line minutes by RAM 4. The array conversion circuit 3 is designed so that the CPU 1 can directly write print data to the RAM 4 and read it from the RAM 4 without going through the array conversion circuit 3.

FIG. 2 is a diagram showing a specific configuration example of the array conversion circuit 3. This array conversion circuit uses the data bus 6a
8-bit first buffer register 11 connected to RAM2
And an 8-bit second buffer register 12 connected in series with the first buffer register, and the outputs of these two buffer registers 11 and 12 are combined to form an R via the data bus 6b.
Eight logic elements 13a, 13b, 13c, 13d, 13e, 13 output to AM4
f, 13g, 13h, a decoder 14 for converting a 3-bit binary code into a decimal code Y0 to Y7 for selecting one of these logic elements, a data bus 6b and a data bus 6a. Buffer for direct connection without going through the array conversion circuit
It consists of 15.

The first buffer register 11 and the second buffer register
An AND output of a write signal ▲ ▼ and a chip select signal ▲ ▼ of the RAM 4 as shown in FIG. 3 is input to the clock terminal 12 via the AND gate 16. Then, in synchronization with the rising edge of the write signal ▲ ▼,
As shown in FIG. 3, the first 1-byte print data Q ₁₁ from RAM 2 is stored in the first buffer register 11, and at the next clock, the above Q ₁₁ is stored in the second buffer register 12 and Q _11.
The 1-byte print data Q _{12 following} is stored in the first buffer register 11, and the contents of both buffer registers are sequentially updated byte by byte in synchronization with the clock. On the other hand, the gate terminals of the decoder 14 and the buffer 15 are input with the bit shift execution signal () via the NOR gate 17, and the other input of the NOR gate 17 is the chip select signal (). Then, in response to the bit shift execution signal ▲ ▼, the decoder 14 converts the binary code input representing the remainder S obtained by dividing the N value indicating the nozzle interval by 8 into a decimal code, and outputs the corresponding output terminal YS. One of the logic elements 13a to 13h is selected via the
Connects the data buses 6a and 6b via an array conversion circuit.

Both buffer registers 1 by the above logic elements 13a to 13h
How to combine the outputs of 1 and 12 is clear from the connection in FIG. That is, for example, "000" is input to the decoder 14,
When the logic element 13a operates via the output terminal Y0, the second
Data Q of the first channel in the buffer register 12
₁₁ (, ...,), the next data Q ₁₂ (7, ..., 1,0) is stored in the first buffer register 11, respectively. Q
₁₁ (, ...,) is output to the data bus 6b as it is, and the output data V ₁ is the AND gate 16 shown in FIG.
It is written to RAM4 in synchronization with the output signal of. Further, for example, when "010" is input to the decoder 14 and the logic element 13c operates via the output terminal Y2, the second buffer register 12 receives the data Q ₂₁ (, ...,) of the second channel in the first buffer. The next data Q _{22 in} register 11 (7, ……, 1,0)
, Respectively, the logic element 13c determines that the upper 2 bits (,) of the data Q ₂₁ of the second buffer register 12 and the lower 6 bits (5, 5) of the data Q ₂₂ of the first buffer register 11 (5,
... 0) are combined to form data V ₁ (5, ... 0,,), and this is written to the address Ad shown in Fig. 4 of RAM 4 at the same timing.

The operation of the ink jet printer having the above-described structure will be described below for the case of four nozzles.

Prior to printing, the CPU 1 sends a bit shift execution signal to the AND gate 16 and the NOR gate 17, and print data stored in the RAM 2 continuously and collectively as shown by the solid line grid in FIG. The data is directly transferred to the RAM 4 via and the bit shift processing required for output to each nozzle is performed. That is, the print data for one line of printing in the RAM2 first moves in the row direction from the first channel corresponding to the first nozzle to Q ₁₁ , Q ₁₂ , ... Q ₁ n, 00H, 00H, and then to the second channel. Q _21, ... Q ₂ n, Te ..., sequentially Q ₄ n and 00H, is read to 00H, are input via the data bus 6a in two stages buffer register 11 and 12 of the array conversion circuit 3. The DMA controller 5 calculates a remainder value S obtained by dividing the N value of the nozzle interval l = N · d by 8, and when the last data 1 byte “00H” of the i channel is written in the first buffer register 11. Then, the numerical value i · S is input to the decoder 14 as a 3-bit binary code. For example, if N = 10, then S = 2, 2 at the end of the first channel, 4 at the end of the second channel, and 6 at the end of the third channel are input to the decoder 14, and outputs Y2, Y4, Y6 corresponding thereto. As a result, the logic elements 13c, 13e and 13g respectively operate to bit shift the channel data next. Therefore, the data Q ₁₁ , ... Q ₁ n of the first channel is the logic element 13a.
The second buffer register 12 without being bit-shifted by
Is written as it is to RAM4 as shown by the broken line in Fig. 4, and the second "00H" 1 byte from the end of the first channel is also written as it is at the beginning of the second line of RAM4, and the last "00H" 1 byte is the second. When the first 1-byte Q ₂₁ of the second channel is in the buffer register 12 and the first buffer register 11, the logic element 13c operates and the second buffer register 1
2 high-order 2 bits “0,0” and Q _{21 of} the first buffer register 11
Lower six bits of the write _{(q 5, ......, q 0} , 0,0) as the dashed line of FIG. 4 in two rows and two row RAM4 combination as.
In this way, the print data corresponding to the second nozzle stored in the second row of the RAM 4 is continuously stored with the start being shifted by 10 dots from the print data of the first nozzle. Similarly, there is 3 bytes of "00H" data at the end of the second channel, and 4 bytes of "00H" data at the end of the third channel. As shown by the broken line in FIG. 4, the head of the print data on the third row of RAM4 is shifted by (2 × 8 + 4) dots, and the head of the print data on the fourth row of RAM4 is (3 ×
It is offset by 8 + 6) dots.

In this way, when the print data for one print line is stored in the RAM 4 in a bit-shifted state, the CPU 1 causes the AND gate 16 and the NOR gate 17 to execute the execution signals ▲ ▼, ▲.
After stopping ▼ and ▲ ▼, the contents of RAM4 are output to the nozzles that are recording elements directly from the data bus 6b through the buffer 15 through the data bus 6a directly through the data bus 6b in the print order of 1 byte for each channel. To be done. Each nozzle ejects ink according to the recording signal that is bit-shifted appropriately according to the nozzle interval, and recording can be obtained in a state where dots of the ejected ink are aligned in a vertical line on the recording paper.

As described above, according to the present invention including the above-described embodiment, the print data of the respective recording elements such as nozzles collectively stored in the memory in the print order are buffered via the array conversion circuit 3 by the DMA controller 5 controlled by the processor. Memory 4
Directly to the array conversion circuit 3 at that time, a shift signal corresponding to the distance between the recording elements is output to the print data to be appropriately bit-shifted in byte units. Bit shift processing can be performed at a much higher speed than that of the system, and therefore high-speed printing by the recording element can be realized. Further, in the above embodiment, the buffer 15 is provided to bypass the array conversion circuit so that the print data can be read and written between the RAM 4 and the CPU 1 and the like, which is very convenient for system control.

In addition, in the above-described embodiment, the case where the recording element is the inkjet nozzle is described, but the number of nozzles is not limited to four, and it goes without saying that the recording element is not limited to the inkjet nozzle. Also, in an inkjet printer for color recording in which three nozzles of each of the above-described embodiments are arranged in the lateral direction and red, blue, and yellow inks are ejected to be overlaid,
The present invention can be effectively applied.

<Effects of the Invention> As is apparent from the above description, in the high-speed printing method of the present invention, the plurality of recording elements corresponding to the vertical dots of the dot matrix are laterally spaced from each other by an integer multiple of the dot pitch. In a printer with a recording head placed,
By the DMA controller controlled by the processor, the print data of each recording element stored in the memory in the printing order at once is directly transferred to the buffer memory through the array conversion circuit. At that time, the shift signal corresponding to the interval between the recording elements is transferred. To the array conversion circuit and appropriately bit-shift the print data in byte units, and the bit-shifted print data transferred to the buffer memory is output to the recording element for printing. Therefore, the bit shift processing can be performed at a significantly higher speed than that of the conventional program control method using a processor, and therefore high-speed printing by the recording element can be realized, and the efficiency of the printer system can be remarkably improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an inkjet printer adopting the high-speed printing method of the present invention, FIG. 2 is a diagram showing a concrete configuration of the array conversion circuit of FIG. 1, and FIG. 3 is a diagram showing the operation of the array conversion circuit. Timing chart, Figure 4 is the RAM of Figure 1
The figure which shows the state of the print data which is housed in 2,4, 5th
The figure shows the nozzle arrangement of the recording head of the inkjet printer. 1 ... CPU, 2 ... RAM (memory), 3 ... array conversion circuit, 4 ... RAM (buffer memory), 5 ... DMA controller.

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Claims (1)

[Claims] 1. A recording head, in which a plurality of recording elements corresponding to vertical dots of a dot matrix are arranged laterally at intervals of an integral multiple of a dot pitch, relative to a recording paper under the control of a processor. In a printer that prints by outputting print data to each recording element while moving horizontally in a horizontal direction, a memory that collectively stores the print data of each recording element described above in consecutive addresses in a printing order, and a memory that is input from this memory. An array conversion circuit that bit-shifts the print data of each recording element on a byte-by-byte basis based on a shift signal corresponding to the interval between the recording elements, and the shifted print data output from this array conversion circuit for each recording element. After storing at consecutive addresses, output the buffer memory to each recording element, and output the shift signal under the control of the processor. The high-speed printing method is characterized by including a DMA controller that controls direct transfer of print data between the memory and the buffer memory to perform high-speed printing of the print data.