JPH087160B2 - Defect data acquisition circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention detects the type of defect, the size of the defect and the position of the defect of a defect data capturing circuit of a defect detection device, particularly a transparent plate such as a glass plate. The present invention relates to a defect data acquisition circuit of an identification type defect detection device capable of performing the above.

[Conventional technology]

When manufacturing a transparent plate such as a glass plate, the types of defects (defects) present in the transparent plate (foreign matter, bubbles, humps, drip etc.),
As a device for detecting the size of the defect and the position of the defect, there is a flying spot type identification type defect detection device.

An outline of an example of the identification type defect detection device developed by the present applicant is shown in FIG. In this identification type defect detection device, a laser beam from a laser light source 1 is incident on a polygonal rotary mirror 2 to scan a laser spot on a glass plate 3 flowing through a manufacturing process line. The scanning direction is a direction perpendicular to the flowing direction of the glass plate (Y-axis direction), that is, the width direction of the glass plate (X-axis direction). The laser light is obliquely incident on the surface of the glass plate 3. This is to avoid interference between the light reflected from the front surface of the glass plate and the light reflected from the back surface of the glass plate.

The transmitted light, the transmitted scattered light, and the reflected light of the laser light incident on the glass plate 3 are received by the light receivers D1, D2, D3, D4, D5 having a light receiving surface elongated in the width direction of the glass plate. Each of these light receivers is configured by arranging a large number of glass fibers. The light receiver D1 receives the transmitted light, the light receiver D2 receives the paraxial transmitted scattered light, the light receivers D3 and D4 receive the far axial transmitted scattered light, and the light receiver D5 receives the reflected light. The glass fibers that make up each light receiver are
The light guided to the corresponding photomultiplier tubes PM1, PM2, PM3, PM4, PM5 and received is converted into an electric signal by each photomultiplier tube. In the signal processing circuit 4, signal processing such as differentiation processing, width processing, comparison processing, and waveform shaping is applied to these electric signals to create defect data D ₁₁ , D ₁₂ , ..., D ₅₂ . There are multiple types of defect data, but defect data D ₁₁ is, for example,
It is data showing a comparison result obtained by comparing a differential waveform obtained by negatively differentiating an electric signal obtained by photoelectrically converting the transmitted light received by the light receiver D1 with a predetermined detection level.

For convenience of description below, the configuration up to the signal processing circuit 4 will be described.
The defect detector 5 is used. The defect data from the defect detector 5 is fetched by the defect data fetching circuit 6 and subjected to signal processing, and then sent to the central processing unit (CPU) 7. In the CPU 7, a defect pattern is created from the defect data and collated with a defect identification pattern table stored in advance to determine the defect type, size, etc.

The present invention relates to an improvement of the defect data capturing circuit in such an identification type defect detection device, but the present invention is not intended only for the identification type defect detection device described above, but is of a flying spot type. If so, any type of identification type defect detection device can be targeted. Further, the reflected and scattered light may be further added to the light for detecting the change in the light amount.

A conventional defect data fetch circuit is shown in FIG. In addition,
The defect data is output from the defect detector 5 shown in FIG. The defect data fetching circuit 10 includes an X-axis counter 11, an OR unit 12, and a frequency dividing circuit 13. The X-axis counter 11 is a clock CL for X-coordinate division.
It is a counter that counts K and is reset by a start pulse ST that is a scanning start signal. The start pulse ST is obtained by extracting the laser light reflected by the polygonal rotary mirror 2 of the defect detector 5 at a specific position with a glass fiber, performing photoelectric conversion, and shaping the waveform. The X-axis counter 11
The count value when the defect data is taken in is output as the X coordinate position data.

The OR unit 12 is a unit for accumulating defect data for a plurality of scans from the defect detector 5 and outputting the defect data at a predetermined timing.
It is disclosed in Japanese Patent Laid-Open No. 56-39419, “Defect Detection Device”.
The purpose of the OR unit 12 is to increase the processing capability of the identification type defect detection device in relation to the processing speed of the CPU 7.

The frequency dividing circuit 13 frequency-divides the line synchronization signal PG corresponding to the moving distance of the glass plate in the line direction and inputs the frequency-divided signal to the OR unit 12. The OR unit 12 outputs the divided line sync signal.
The accumulated defect data is output at the timing of PG.

In the conventional defect data fetching circuit having the above configuration, the defect data stored in the OR unit 12 is transferred to the memory of the CPU 7 by direct memory access (DMA) every time there is a defect. Therefore, the defect data may not be taken in during DMA, so that the defect data may be missing. In this case, there is a problem that the defect cannot be detected.

Further, in the conventional defect data fetching circuit, recognition of the Y coordinate position of the defect is performed by software processing on the CPU side. That is, when the data transferred from the acquisition circuit is stored in the memory of the CPU 7, "0" is inserted for each data division, and the position of the Y coordinate is recognized by counting the number of "0". There is. However, this method has a problem that since the memory capacity of the CPU 7 is limited, the Y coordinate position is erroneously recognized when the storage is completed.

An object of the present invention is to provide a defect data capturing circuit of an identification type defect detecting device which solves the above problems.

[Structure of Invention]

According to the present invention, a transparent plate running in the length direction is scanned with a light spot in the width direction, and based on a combination of light amount changes of any one of transmitted light, transmitted scattered light, reflected light, and reflected scattered light. In the defect data acquisition circuit of the identification type defect detection device for detecting the type, size, position, etc. of the defect, the first pulse train related to the position of the transparent body in the width direction is counted, and the defect data is acquired. A first counter that outputs a count value when the second pulse train that counts a second pulse train that is related to the position of the transparent body in the lengthwise direction, and outputs a count value when the defect data is captured. A counter, an OR unit for accumulating OR processing of defect data for a plurality of scans, and outputting the processed defect data at the pulse generation timing of the second pulse train; and the X-axis counter, Y-axis counter, OR unit Store the output of It is characterized by having a buffer memory.

〔Example〕

 Examples of the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of the present invention.
The defect data shall be input from the defect detector 5 shown in FIG. This defect data acquisition circuit 20 is
In the conventional defect data acquisition circuit shown in FIG.
Further, a Y-axis counter 21 is added after the frequency dividing circuit 13, and a FIFO memory 22 is added after the X-axis counter 11, the OR unit 12, and the Y-axis counter 21. The Y-axis counter 21 counts the frequency-divided line synchronization signal PG from the frequency dividing circuit 13 and outputs the count value to the FIFO memory 22 as Y-coordinate position data when the defect data is input. The Y-axis counter
21 is reset by software. The FIFO memory 22 is
X coordinate position data from X axis counter 11, OR unit 12
And the Y coordinate position data from the Y-axis counter 21 are temporarily stored. Then, the defect data and the defect position data (X, Y) are transferred from the FIFO memory 22 to the memory of the CPU 7 by DMA.

FIG. 2 shows an example of the OR unit 12. This OR unit
12, a plurality of types of flaw data D _11, D _12, ..., corresponding respectively to D _52, the OR circuit OR _11, OR _12, ..., and OR _52, a random access memory _{RAM 11, RAM 12, ... RAM} 52 And gate circuits G ₁₁ , G ₁₂ , ..., G ₅₂ .

FIGS. 3 and 4 are diagrams for helping understanding of the operation of the OR unit 12, and FIG. 3 shows scanning by the laser spot, clock CLK, and line synchronization signal PG after frequency division.
FIG. 4 is a schematic diagram showing the relationship with the above, and FIG. 4 is a diagram showing a state of being filled with defect data D _{11 in} the RAM ₁₁ of the OR unit. With reference to these drawings, the defect data as an example in the OR unit 12
The operation of accumulating D ₁₁ will be described. It is assumed that the glass plate is scanned n times in the X-axis direction by the laser spot during the line synchronization signal PG after frequency division. It is also assumed that each RAM of the OR unit 12 has addresses up to 1000. The address of each RAM corresponds to what number clock the clock CLK is.

Now, as shown in FIG. 3, when the glass plate 3 has a defect 40, the defect data D ₁₁ input from the defect detector 5 in the first scanning is written in the RAM ₁₁ and the bit “1” is set at the addresses 502 and 503. "Is standing. Flaw data D ₁₁ that has been entered in the second scanning after the OR is taken in flaw data and the logical OR circuit OR ₁₁ read from the RAM _11, is re-written to RAM _11, ... n-th scan Defect data D entered in
₁₁ is the defect data read from the RAM ₁₁ and the OR circuit O
After being ORed in R ₁₁ , it is rewritten in RAM ₁₁ ,
Finally, the bit “1” is stored in the addresses 501 to 504. The defect data D ₁₁ stored in the RAM ₁₁ in this way is the line synchronization signal PG divided by the divider circuit 13.
It is output through the gate circuit G ₁₁ at the timing of.

As a result of the processing performed by the OR unit 12 as described above, defects located at a close distance in the Y-axis direction are regarded as the same, and as a result, the amount of information to be processed by the CPU can be reduced. As a result, the traveling speed of the glass plate can be increased to speed up the inspection. Alternatively, if the traveling speed of the glass plate is the same, it is possible to reduce the laser spot diameter and improve the detection sensitivity several times.

Now, returning to FIG. 1, the operation of the defect data fetch circuit of this embodiment will be described in more detail. The start pulse ST and the clock CLK are input to the X-axis counter 11,
The R unit 12 has defect data D ₁₁ , D from the defect detector 5.
₁₂ , ..., D ₅₂ are input, and the line synchronizing signal PG is input to the frequency dividing circuit 13. The X-axis counter 11 counts the clock CLK and outputs the count value when the defect data is taken in to the FIFO memory 22 as X coordinate position data. X
The axis counter 11 is reset by the start pulse signal ST.

The OR unit 12, as described with reference to FIGS. 3 and 4, stores defect data for a plurality of scans for each defect data D ₁₁ , D ₁₂ , ... D ₅₂ , and divides the frequency by the frequency dividing circuit 13. And outputs it to the FIFO memory 22 at the timing of the line synchronization signal PG. The Y-axis counter 21 counts the frequency-divided line synchronization signal PG from the frequency dividing circuit 13 and outputs the count value to the FIFO memory 22 as Y-coordinate position data when the defect data is input. The Y-axis counter 21 is reset by software.

As described above, the X coordinate position data, the defect data, and the Y coordinate position data are temporarily stored in the FIFO memory 22, and these data are transferred to the memory of the CPU 7 by DMA between the FIFO memory 22 and the memory of the CPU 7. This data transfer is performed according to the data processing speed of the CPU 7. Therefore, unlike the conventional defect data capturing circuit, it is not possible to capture defect data during DMA and the defect data is not lost, and it is possible to reliably capture all the defect data.

In addition, since the Y-coordinate position data, which has been conventionally performed by software, is detected by hardware by providing the Y-axis counter 21, the defect Y-coordinate position can be detected as in the conventional case. The problem of misrecognition disappears.

〔The invention's effect〕

As described above, according to the defect data fetching circuit of the present invention, the Y-axis counter is provided so that the Y coordinate position data of the defect is detected by hardware. It is possible to avoid erroneously recognizing the Y coordinate position of the defect.

In addition, since the buffer memory is provided and the defect data, Y coordinate position data, and Y coordinate position data are temporarily stored in the buffer memory, the defect data can be taken in without fail, and therefore the conventional DMA Since the defect data cannot be taken in, there is no fear that the defect data will be missing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the OR unit of FIG. 1, and FIGS. 3 and 4 explain the operation of the OR unit. FIG. 5 is a block diagram showing an outline of an identification type defect detection device, and FIG. 6 is a block diagram showing a conventional defect data acquisition circuit. 1 …… Laser light source 2 …… Polygonal rotating mirror 3 …… Glass plate 4 …… Signal processing circuit 5 …… Fault detector 6,10,20 …… Fault data acquisition circuit 7 …… CPU 11 …… X-axis counter 12 …… OR unit 13 …… divider circuit 21 …… Y-axis counter 22 …… FIFO memory 40 …… Disadvantages

Claims (1)

[Claims] 1. A transparent plate running in the length direction is scanned with a light spot in the width direction, and based on a combination of changes in the light amount of any one of transmitted light, transmitted scattered light, reflected light, and reflected scattered light. In the defect data acquisition circuit of the identification type defect detection device for detecting the type, size, position, etc. of the defect, the first pulse train related to the position of the transparent plate in the width direction is counted, and the defect data is acquired. A first counter that outputs a count value when the defect data is obtained, and a second counter that counts a second pulse train related to the position of the transparent plate in the longitudinal direction and outputs a count value when defect data is taken in. And the defect data for multiple scans are accumulated and OR-processed, and the second
Defect data comprising an OR unit for outputting the processed defect data at the pulse generation timing of the pulse train, and a buffer memory for temporarily storing the outputs of the X-axis counter, the Y-axis counter, and the OR unit. Capture circuit.