JPH087337B2 - Circuit structure for liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type liquid crystal display device, and more particularly to a structure of a drive circuit portion of a matrix type liquid crystal display device in which a switching transistor for address is added to each picture element in a matrix type display pattern. .

[0002]

2. Description of the Related Art As a matrix type liquid crystal display device using a non-linear element for driving a liquid crystal display, a thin film transistor for addressing (hereinafter abbreviated as TFT) is incorporated in a liquid crystal display panel in a matrix form to reduce a duty ratio. There is known a TFT active matrix type liquid crystal display device capable of obtaining a high-contrast display equivalent to that of static drive even when performing a small or multi-line multiplex drive.

As a driving method of this TFT active matrix type liquid crystal display device, there is one having a circuit configuration and a signal waveform as shown in FIGS. Reference numeral 11 in the figure is a liquid crystal display panel, and a TFT 11c is connected to an intersection of the row electrode 11a and the column electrode 11b as shown in the figure. 11d is the capacitance of the liquid crystal layer. Reference numeral 12 denotes a row electrode driver, which is mainly composed of a shift register, and sequentially shifts the scanning pulse S by a clock φ1 from the gate signal control unit 13 and outputs the scanning pulse S to each row electrode. When the total scanning period of this row electrode is T and the number of scanning lines is N, the scanning period H is represented by H = T / N. A pulse voltage having a pulse width equal to the scanning period H is sequentially applied to each row electrode so as to turn on the TFT 11c row by row. Reference numeral 14 is a column electrode driver, which is a drive system for directly sampling and holding (SH) data on the display panel (hereinafter referred to as a panel SH drive system) and a drive system for giving the column electrode driver a function of sampling and holding data (hereinafter, There is a driver SH drive system). As shown in FIG. 7, the column electrode driver of the panel SH driving system is composed of a shift register 31, a sampling switch 32, etc., and the data sent in series from the data signal controller 15 is clocked by a clock φ2 at a timing corresponding to each column. The sampling is performed in synchronism with
Writing to the liquid crystal layer through 1c. In this driving method, sampling of data and writing of the liquid crystal layer through the TFT 11c are performed within the same horizontal scanning period. Next, the driver SH driving method will be described with reference to FIGS. 8 and 9. The sampling switch 42 is turned on in synchronization with the output of the shift register 41, and the charge corresponding to the data signal is stored in the capacitor 43. Next, a discharge pulse signal located in the first half of the horizontal blanking period is applied to Ce to discharge the remaining charge and form the reference state. Next, when the transfer pulse signal located in the latter half of the horizontal blanking period is applied to Cg, the charge accumulated in the capacitor 43 is transferred to the transistor 44 and output. In this driving method, data is written in the liquid crystal at the next 1H after sampling.

[0004]

In the case of taking out the row electrodes from the liquid crystal display panel, the method of taking out all of the row electrodes on one end side as shown in FIG. 5 or FIG.
As shown in (B), a method of distributing the row electrodes to the left and right alternately by allocating them to both ends of the liquid crystal display panel can be considered for convenience of mounting. When taking out the row electrodes at both ends in the left and right directions, the signals applied to the row electrodes must be alternated left and right in terms of time.Therefore, if the row electrode driver is arranged on one side, the routing lines are connected in the connection with the liquid crystal display panel. The length of the wiring becomes longer and the wiring crosses over, resulting in an increase in the area of the wiring or wiring using through holes, which causes problems in terms of downsizing and reliability. When row electrode drivers are arranged on both the left and right sides, one takes out the output of the odd-numbered shift register and the other takes out the output of the even-numbered shift register, so only half the total number of stages is used. There is a problem in terms of miniaturization and power consumption. Moreover, a start pulse signal and a clock signal for operating the shift register are required on the left side and the right side, respectively, which causes an increase in the number of input signals.

The present invention has been made in view of the above-mentioned problems in the conventional drive circuit of the matrix type liquid crystal display device, and it is a novel and useful liquid crystal which consumes less power and is easily miniaturized and highly integrated. It is an object of the present invention to provide a structure of a drive circuit unit of a display device.

[0006]

SUMMARY OF THE INVENTION According to the present invention, an output terminal sequentially connected to a scanning electrode connected to the switching element of a liquid crystal display panel in which an address switching element is added to each picture element of a matrix type display pattern. In a drive circuit for a liquid crystal display device, which comprises a scanning circuit for sequentially outputting a scanning pulse via an input terminal in synchronism with a start pulse supplied to an input terminal, the scanning circuit is synchronized with the input of the start pulse. A first circuit system forming a first pulse output state in which scanning pulses are output from the output terminal as scanning pulses for every other scanning electrode and sequentially corresponding to a scanning period; In synchronism with the input, the scan pulse is delayed from the output terminal by one scan period with respect to the first pulse output state, and the scan electrodes are scanned every other scan electrode. Second to form a second pulse output state is sequentially outputted in correspondence with and the scanning period as a pulse
And a third pulse output state in which the scan pulse is sequentially output from the output terminal as the scan pulse for each scan electrode and corresponding to the scan period in synchronization with the input of the start pulse. And a switching terminal for selectively setting the scanning circuit to one pulse state by switching between the third circuit system and the third circuit system.

[0007]

Since the driving circuit for the liquid crystal display device of the present invention is provided with the scanning circuit which generates three different scanning pulses from the start pulse and the signal of the switching terminal, the driving circuit which requires different driving states. The same drive circuit can be used in the circuit, and it is not necessary to separately generate the start pulse even in the drive circuit for taking out the left and right sides.

[0008]

EXAMPLE An example in which the drive circuit section of the liquid crystal display device according to the present invention is applied to a liquid crystal television will be described below.

FIG. 1 can be used whether the row electrodes of the liquid crystal display panel are taken out on one side or on both left and right sides.
FIG. 6 shows a circuit diagram of a row electrode driver which consumes less power and is easily integrated. When the row electrode of the liquid crystal display panel is taken out on one side, the R / L terminal is "1", the B / S terminal is "0", H
Set the ₂ / H ₁ terminal to “1”, the D / P terminal to “0”, and the Low terminal to “1”. If the row electrode is taken out on one side,
In order to perform line-sequential driving, scan pulses must be supplied to the scan electrodes from the output terminal of the scan circuit for each successive scan period. The timing waveform in that case is shown in FIG. A start pulse signal SP having a width of 4H is supplied to the flip-flop 61.
(FIG. 2A) and a clock signal CL having a period of 1H (see FIG. 2A).
(B)) is input, and its output signal Q (FIG. 2C) is selected by the clocked inverter 64 and selected by the shift register 7.
8 data terminals. This shift register 78
Shifts by half a bit. On the other hand, flip-flop 6
After the inverted output Q of 1 and the start pulse signal SP are processed by the NAND circuit 67, the output signal is selected by the clocked inverter 69 and input to the reset terminal of the flip-flop 71 (FIG. 2D). The flip-flop 71 triggers at the falling edge of the clock signal CL (FIG. 2 (B)), and the clocked inverter 74 selects a signal whose frequency is divided by 1/2 and inputs it to the clock terminal of the shift register 78 (see FIG. 2 (E)). The output of the shift register 78 (FIG. 2 (G)) has a pulse width of 4H as shown by H and I, and 1H.
The signals are shifted one by one.

The output of the OR circuit 76 is an enable signal for the row electrode driver output, which is "0" in the setting of this embodiment.
(FIG. 2 (F)). For example, when the Low terminal is set to "0", the row electrode outputs are all "0".

Reference numeral 77 is a delay circuit for adjusting the timing. The inversion of the output of the first stage (FIG. 2G) of the shift register 78 and the output of the second stage (FIG. 2)
(H)) and an enable signal (currently "0" at the output of the delay circuit 77) are output from the NOR circuit 80, and the pulse signal is level-shifted and output by the level shifter 81 (FIG. 2 (J)). Is a scanning side drive signal applied to the row electrodes of the liquid crystal display panel. The signal at the terminal 86 is the output of the nth stage of the shift register 78, and is input to the SP terminal which is the start pulse signal input of the row electrode driver of the next stage when a plurality of row electrode drivers are continuously connected. Thus the R / L terminal "1", the B / S pin "0", H ₂ / H ₁ pin "1", the D / P terminal "0", the Low terminals "1"
When set to, the row electrode driver output is as shown in FIG.
A pulse having a width of 1H is shifted bit by bit as in (K).

Next, the case where the row electrodes of the liquid crystal display panel are taken out in both left and right directions will be described. First, in the case of the right side, the R / L terminal is “1”, the B / S terminal is “1”, H ₂ /
The H ₁ terminal is set to “0”, the D / P terminal is set to “0”, and the Low terminal is set to “1”. When the row electrodes are taken out in both the left and right directions, in order to perform line-sequential driving, scanning pulses must be alternately supplied to the scanning electrodes from the output terminals of the scanning circuits arranged on both the left and right sides every scanning period. The timing waveforms in that case are shown in FIGS. First, FIG. 3 shows timing waveforms of the scanning circuit arranged on the right side. Up to the data input signal of the shift register 78 and the reset signal of the flip-flop 71, the row electrodes of the liquid crystal display panel are taken out on one side (FIG. 2 (A)-
(D) and FIGS. 3 (A) to (D)). Flip-flop 71
Output Q is input to the clock terminal of the flip-flop 72, and the clocked inverter 73 selects the signal (FIG. 3 (E)) further divided by 1/2, and the shift register 78
Input to the clock terminal of. The output of the shift register 78 that shifts by half bits is as shown in FIGS.
As in (I), the signal has a pulse width of 4H and is shifted by 2H. The output (enable signal) of the delay circuit 77 is as shown in FIG. The finally output signal has a pulse width of 1H, as shown in FIGS.
Then, shift one by one. That is, this output is equivalent to the one obtained by extracting the odd-numbered or even-numbered signal of the signal which is continuously shifted by one bit. Terminal 86
Is a signal that triggers the output of the nth stage of the shift register 78 at the rising edge of the inverted output of the flip-flop 71. When a plurality of row electrode drivers are continuously connected, the start pulse signal of the row electrode driver of the next stage is input. Input to a certain SP terminal.

Next, in the case of the left side, the R / L terminal is set to "0", and other settings are the same as in the case of the right side. The timing waveform for the left side is shown in FIG. The output Q (FIG. 4) obtained by inputting the start pulse signal to the data terminal of the flip-flop 61 and the clock signal to the clock terminal
FIG. 4D shows a signal obtained by inputting (C)) to the data terminal of the flip-flop 62 and triggering at the falling edge of the clock signal. Further, this signal is input to the data terminal of the flip-flop circuit 63, and the signal (FIG. 4E) obtained by triggering at the rising edge of the clock is selected by the clocked inverter 65 and input to the data terminal of the shift register 78. To do. A NAND signal of the output Q of the flip-flop 62 and the inverted output Q of the flip-flop 63 is output from the NAND circuit 68, selected by the clocked inverter 70, and this signal is input to the reset terminals of the flip-flops 71 and 72 (Fig. 4 (F)). The signals input to the data terminals of these shift registers 78 and the signals input to the reset terminals of the flip-flops 71 and 72 are 1H later in time than the signals when they are set for the right side of the row electrode driver. The clocked inverter 73 selects a signal, which is triggered by the falling edge of the clock signal and is divided by ¼ by the flip-flops 71 and 72, and is input to the clock terminal of the shift register 78 (FIG. 4).
(G)). Shift register 78 for shifting by half bit
As shown in FIGS. 4 (I), (J), and (K), the output of is a signal having a pulse width of 4H and shifted by 2H. The start position of the output signal of the shift register 78 is 1H later in time than when the row electrode driver is set for the right side.
The output (enable signal) of the delay circuit 77 is shown in FIG.
It becomes like (H). The final output signal is shown in Figure 4.
As shown in (L) and (M), the pulse width is shifted by 1H at every 1H. However, the position of the first output is 1 more in time than when the row electrode driver is set for the right side.
H will be late.

Therefore, when the row electrode drivers are arranged on the left and right sides of the liquid crystal display panel, the start pulse signal SP and the clock signal CL can be made common, and the setting of the R / L terminals of the left and right row electrode drivers can be changed. The right and left row electrodes of the liquid crystal display panel can be driven alternately.

[0015]

As described above in detail, in the structure of the driving circuit of the present invention, the row electrode driver has the switching terminals for taking out one side and both sides of the left and right sides, whereby the row electrodes of the liquid crystal display panel can be taken out. It can be applied to either one side or both sides. Further, even in the case of taking out both the left and right sides, the start pulse and the clock can be driven by a signal common to the left and right. Therefore, by using the row electrode driver of the present invention, it is possible to take out the row electrodes of the liquid crystal display panel on one side or on both the left and right sides, and it is possible to realize small size and high integration with low power consumption. it can.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a row electrode driver showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of a main part when the row electrode driver of the embodiment shown in FIG. 1 is set for taking out one-way terminals.

FIG. 3 is a waveform diagram of a main part when the row electrode driver of the embodiment shown in FIG. 1 is set for the right side by taking out bidirectional terminals.

FIG. 4 is a waveform chart of a main part when the row electrode driver of the embodiment shown in FIG. 1 is set for the left side by taking out bidirectional terminals.

FIG. 5 is a block diagram showing a configuration of a conventional liquid crystal display device.

6 is a timing chart showing main driving waveforms of the liquid crystal display device shown in FIG.

FIG. 7 is a circuit diagram illustrating a column electrode driver of a conventional panel SH driving method.

FIG. 8 is a circuit diagram illustrating a column electrode driver of a conventional driver SH driving method.

9 is a timing waveform chart showing drive waveforms in the circuit of FIG.

10A and 10B are explanatory views showing the connection with the scanning circuit when the row electrode is taken out on one side and when the row electrode is taken out on both sides.

[Explanation of symbols]

H horizontal scanning period 31, 41, 78 shift register 32, 42 analog switch 43 sampling capacitor 44 transistor 61, 62, 63, 71, 72, 82 flip-flop 64, 65, 69, 70, 73, 74, 83, 84 Clocked inverter 67,68 NAND circuit 80 NOR circuit 77 Delay circuit 81 Level shifter

Continuation of the front page (56) Reference JP-A-58-75195 (JP, A) JP-A-55-41442 (JP, A) JP-A-57-52088 (JP, A) JP-A-56-14296 (JP , A)

Claims (1)

[Claims] 1. A scan pulse is input through an output terminal sequentially connected to a scan electrode connected to the switching element of a liquid crystal display panel in which an address switching element is added to each picture element of a matrix type display pattern. In a drive circuit for a liquid crystal display device, which comprises a scanning circuit for sequentially outputting in synchronization with a start pulse supplied to the scanning circuit, the scanning circuit is configured to scan a pulse from the output terminal in synchronization with the input of the start pulse. A first circuit system that forms a first pulse output state that is sequentially output as scanning pulses for every other scanning electrode and corresponding to a scanning period; and the output in synchronization with the input of the start pulse. The scanning pulse from the terminal is 1 for the first pulse output state.
A second pulse which is sequentially output as scanning pulses for every other scanning electrode in a state of being delayed by the scanning period and corresponding to the scanning period.
And a second circuit system that forms a pulse output state of the scan pulse, and in synchronization with the input of the start pulse, the scan pulse is sequentially output from the output terminal as the scan pulse for each scan electrode and corresponding to the scan period. A third circuit system for forming a third pulse output state, and a switching terminal for selectively setting the scanning circuit to one pulse state by switching between the third circuit system and the third circuit system. Drive circuit for display device.