JPH087608B2 - Pulse output device - Google Patents

Description

The present invention relates to a pulse output device, and more particularly to a pulse output device that outputs a pulse width modulation signal at high speed using a microcomputer.

[Conventional technology]

2. Description of the Related Art In recent years, with the development of integrated circuit technology, a microcomputer equipped with a CPU, a memory, an interrupt control circuit, and peripheral devices such as a timer on the same semiconductor substrate has appeared. There are various types of devices to which this microcomputer is applied, but an inverter that drives an induction motor by pulse width modulation (hereinafter abbreviated as PWM) is also one application example.

Generally, an induction motor has a simpler structure than a DC motor, but it is said that the control device is complicated because the frequency needs to be changed to control the rotation speed, and the entire device is expensive. However, with the advent of the above-mentioned microcomputer, the induction motor drive by PWM has become common in recent years.

FIG. 6 is a block diagram showing a pulse output device using a conventional microcomputer. As shown in FIG. 6, this pulse output device includes a general-purpose register (hereinafter abbreviated as REG) 24, an arithmetic logic operation unit (hereinafter abbreviated as ALU) 25, corresponding to the data bus 108. , Program status word (abbreviated as PSW) 26
An execution control unit 27 for controlling a central processing unit (hereinafter abbreviated as CPU) and a program counter (hereinafter abbreviated as PC) 28 for holding a program execution address.
A read-only memory (hereinafter abbreviated as ROM) 29 that stores a program, a random access memory (hereinafter abbreviated as RAM) 30 that stores various data, a timer 31, and an input / output request signal An interrupt control unit (hereinafter abbreviated as INTC) 32 for performing priority control and a port 33 are provided.

7. FIG. 7 is a block diagram of the timer 31, which is composed of a counter 34 that counts the periodic signal Φ and a compare register 35 that detects a match with the counter 34.

Hereinafter, with reference to the time chart showing the PWM signal of FIG. 5 and the flowchart of FIG. 8, a conventional example will be described in which the PWM signal is formed and output by P1, P2 and P3.

In FIG. 7, the predetermined periodic signal Φ is counted by the counter 34, and its output is sent to the compare register 35. In the compare register 35, a numerical comparison with the output of the counter 34 is performed, and at the time of coincidence (t ₁ ), the coincidence signal 106 is output. The coincidence signal 106 is input to the counter 34 to initialize the counter 34 and is also sent to the INTC 32 as the input / output request signal 106. Sixth
In the figure, when the input / output request signal 106 is generated at time t ₁ , the INTC32 outputs this input / output request signal 106.
In response to this, an interrupt request signal 107 is generated and sent to the execution control unit 27. In the execution control unit 27, the process of saving the PSW 26 and the PC 28 to the RAM 30 is executed after the input of the interrupt request signal 107 is completed and the instruction currently being executed is completed, and the timer corresponding to the interrupt request signal 107 is executed. The execution of the interrupt process is started.

In this timer interrupt processing, various REG24 are
Then, the port 33 is set and the process up to the return is executed. Such processing means are performed repeatedly until the time t _6, is processing corresponding to one period T is completed, a predetermined PWM signals P1, P2 and P3 are output from the port 33 (FIG. 5 reference). Needless to say, by shifting the time, the PWM signals P1, P2 and P3 are output in the same procedure in the next cycle T as well.

[Problems to be Solved by the Invention]

In the above-mentioned conventional pulse output device, there is a drawback that it is impossible to increase the frequency of the PWM signal to be output due to the restriction of the time required for the interrupt request, and in order to solve this drawback. When performing PWM control using a dedicated LSI separately from the microcomputer,
The pulse generator itself has a high price and is economically unfit.

[Means for solving the problem]

A pulse output device of the present invention includes a memory that stores programs and data, a central processing unit that selectively executes a process based on a process request (1) generated from a predetermined peripheral device and a process by a predetermined program. In a pulse output device formed by using a microcomputer including, an interrupt control means for receiving the processing request (1) and controlling the processing priority of the microcomputer, and a counting means for counting a predetermined periodic signal. And outputs a coincidence signal generated by detecting the coincidence between the output of the counting means and its own set value, initializes the counting means with the coincidence signal, and responds to the processing request (1). One generated by detecting the coincidence between the output of the counting means and the individual self-set value, and the comparing means for sending the included predetermined processing request (2) to the interrupt control means. 2K (K: integer of 2 or more) that individually outputs signals and sends a predetermined processing request (3) included in the processing request (1) to the interrupt control means via the coincidence signal. Pulse control means for outputting a predetermined pulse width modulation signal, which is set or reset by the output of K combination pairs of the coincidence signals output from the comparison means group. In addition, the microcomputer suspends the execution of the processing by the program in the central processing unit in response to the processing request (1), and saves the processing information at the interruption time to another storage area. Without transferring the data set in the memory in advance to the comparison means group, and sequentially, for each cycle set in each comparison means group, a plurality of the pulse widths. It is provided with a control function for outputting a modulated signal.

〔Example〕

Next, the present invention will be described with reference to the drawings. First
1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams of a REG (general-purpose register) and a pulse control unit included in this embodiment, respectively. As shown in FIG. 1, this embodiment uses a bus line.
Corresponding to 105, REG1 that temporarily stores various data
ALU2 that executes addition, subtraction, multiplication, division, and logical operations, PSW3 that holds the program execution state, etc., execution control unit 4 that controls the execution of the central processing unit, and execution of each instruction included in execution control unit 4 Control microprogram
A microprogram ROM including a ROM and its sequencer /
Holds the sequencer 10 and program execution address
PC5, ROM6 where programs and data are stored,
A RAM 7 for storing various data, a pulse control unit 8 for outputting a predetermined PWM signal, an INTC 9 for receiving a predetermined input / output request signal and performing processing such as priority determination and interrupt processing mode designation, Is equipped with.

In FIG. 1, when the interrupt request signal 102 output from INTC9 and input to the execution control unit 4 is logic "1", it indicates that the execution control unit 4 is requested to interrupt. Further, when it is logical "0", it indicates that no interrupt request is issued to the execution control unit 4. When the interrupt request signal 102 is a logic "1" and the interrupt processing mode designation signal 103 is a logic "0", the execution control unit 4 suspends the execution of the program after the end of the instruction currently being executed, The contents of PSW3 and PC5 are set by a pointer (not shown) preset inside REG1.
After being saved in the RAM 7, the vector address according to the input / output request signal 101 is set in the PC 5, and the interrupt processing program is executed based on the contents of the ROM 6.

At the end of the interrupt processing program, the PC5 and PSW3 are restored from the RAM7 by the interrupt return command, and the execution of the program suspended by the interrupt processing is restarted. This interrupt processing form is hereinafter referred to as vector processing. If the interrupt request signal 102 is a logic "1" and the interrupt processing mode designation signal 103 is also a logic "1", the execution of the program is suspended after the end of the instruction currently being executed, and PSW3 and In response to an input / output request, the contents of a specific address on RAM7 are preset according to the input / output request without executing the save process while holding the contents of PC5. The data transfer is executed, and immediately after the end of the transfer, the execution of the interrupted program is resumed. This interrupt processing form is hereinafter referred to as macro service.

2 and 3 are block diagrams showing the configurations of the pulse control unit 8 and INTC9, respectively. The former pulse control unit 8 is constituted by a counter 11, compare registers 12-18 and SR flip-flops 19-21. The latter INTC 9 is composed of a priority order determination / interruption hold control unit 22 and a plurality of processing mode designation registers 23a-23g.

In FIG. 2, the predetermined periodic signal Φ is counted by the counter 11, and its output is the compare registers 12-18.
Sent to In the compare register 12, the counter
Numerical comparison with the output of 11 is performed, and when they match, a match signal 101a is output. This coincidence signal 101a is
It is input to the counter 11 to initialize the counter 11 and is also sent to the INTC 9 as one of the input / output request signals 101.
In addition, the counters 11 are also provided in the compare registers 13 to 18.
Numerical comparison is performed, and at the time of coincidence, coincidence signals 101b to 101g are respectively output and input to the corresponding SR flip-flops 19 to 21, and these coincidence signals are also input / output request signal 101. It is sent to INTC9 as a part.

In FIG. 3, a plurality of input / output request signals 101a to 101g sent from the pulse control unit 8 are input to the priority order determination / interruption hold control unit 22. The priority determination / interruption hold control unit 22 is also input to the processing mode designating signals from the processing mode designating registers 23a to 23g corresponding to the plurality of input / output request signals 101a to 101g, respectively. Control operations relating to the order and the input / output request suspension are performed, and the interrupt request signal 102 and the interrupt processing mode signal 103 are output and sent to the execution control unit 4.

FIG. 4 is an address map showing the structure of the macro service channel for designating the macro service processing mode. In the macro service mode of address N, the data transfer direction, word / byte distinction, etc. are designated, and N +
The storage address M of the transfer data is designated by the channel pointer of the first address. When the data is designated by word, the word data is stored in the addresses M and M + 1 as shown in the figure. The addresses on the RAM7 that should be set in advance are determined for the macro service channels corresponding to each input / output request. For the input / output requests for macro service processing, the macro service channels are set to these addresses. Is set.

Next, referring to FIGS. 5 (a), (b), (c) and (d) showing the timing chart of the PWM signal, the PWM
The control action on the signal output will be described.

In FIG. 2, a value corresponding to the PWM cycle T shown in FIG. 5 is set in the compare register 12, and the compare registers 13, 14, 15, 16, 17, and 18 are set to (t ₅
−t ₀ ), (t ₂ −t ₀ ), (t ₄ −t ₀ ), (t ₃ −t ₀ ), (t ₆ −
Values corresponding to the time of t ₀ ) and (t _z −t ₀ ) are set. As the designation of the interrupt processing form, 101a in FIG. 3 is specified.
Specifies the vector interrupt processing, and 101b to 101g specify the macro service processing, and the macro service channel is set to the determined address of the RAM 7, respectively.
Cycle T for word data of macro service channel
A value corresponding to the set / reset timing of the next cycle indicated by is set.

Next, when the counter 11 is started, at the time t ₁ , the SR flip-flop 21 is reset and at the same time an input / output request signal is generated, and the program currently being executed in the CPU is temporarily suspended, and PSW3 and The corresponding data set in the RAM 7 is transferred to the compare resister 18 without saving the PC 5. When this transfer is completed, the processing of the interrupted program continues and resumes. Such an operation is similarly executed at each of the times t _{1 to} t ₆ corresponding to each compare resister, and the PWM signals P 1 to P having the cycle T as one cycle.
3 is output from the SR flip-flops 19 to 21. Fifth
FIG. 5A shows the signal of the cycle T in the counter 11, and FIGS. 5B, 5C and 5C show the PWM signals P1, P2 and P3, respectively.

At the final time t ₀₁ of the cycle T, the match signal 101a in the compare register 12 is output, the counter 11 is initialized, the input / output request signal is also generated, and the vector interrupt processing is executed. In this vector interrupt process, the value corresponding to the set / reset timing required for the next PWM signal cycle is set in the word data storage address of each macro service channel.

By repeating the above operation, the desired PW
M signals P1, P2 and P3 are obtained. Therefore, as is apparent from the present embodiment, by using the macro service processing and the pulse control unit in combination, it becomes possible to control the timing of changing the PWM signal in real time, and save in the PSW and PC etc. No processing is required. Further, since the data setting process of the macro service channel replaces the buffer register, the next PWM signal can be set in advance, and the cycle of the PWM signal can be shortened.

〔The invention's effect〕

As described above in detail, the present invention, by operating the macro service process and the pulse control process in combination, the change timing of the PWM signal can be controlled in real time, and PSW, PC, etc. Since the save processing is unnecessary, there is an effect that the input / output processing is realized at high speed. In addition, the PWM cycle is shortened, it is easy to increase the frequency of the PWM signal, and it is not necessary to separately provide a dedicated LSI, and inexpensive and high-speed PWM signal control can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a pulse control unit included in the one embodiment, and FIG. 3 is an INTC (interruption) included in the one embodiment. Control unit), FIG. 4 is a diagram showing a macro service channel, FIG. 5 is a diagram showing a timing chart of a PWM signal, and FIG. 6 is a block of a pulse output circuit using a conventional microcomputer. Figure, 7th
FIG. 8 is a block diagram of a timer included in the conventional pulse output circuit, and FIG. 8 is a diagram showing a flowchart in conventional PWM control. In the figure, 1,24 …… REG (general-purpose register), 2,25 …… A
LU (arithmetic logic operation unit), 3,26 …… PSW (program status word), 4,27 …… Execution control unit, 5,28
...... PC (program counter), 6,29 …… ROM (read only memory), 7,30 …… RAM (random access memory), 8 …… pulse control unit, 9,32 …… INTC (interrupt control unit) , 10 ... Micro program ROM / sequencer, 11,34 ... Counter, 12-18, 35 ... Compare register, 19-21 ... SR flip-flop, 22 ... Priority determination / interruption hold control unit, 23a ~ 23g …… Processing mode specification register, 31 …… Timer, 33 …… Port.

Claims (1)

[Claims] 1. A central processing unit for storing a program and data, and a central processing unit for selectively executing processing based on a processing request (1) generated from a predetermined peripheral device and processing by a predetermined program. In a pulse output device formed by using a microcomputer, an interrupt control means for receiving the processing request (1) and controlling the processing priority of the microcomputer, a counting means for counting a predetermined periodic signal, and A coincidence signal generated by detecting the coincidence between the output of the counting means and its own set value is output, the counting means is initialized by the coincidence signal, and a predetermined value included in the processing request (1). Of the processing request (2) to the interrupt control means, and the coincidence signal generated by detecting the coincidence between the output of the counting means and each self-set value individually. 2K (K: integer of 2 or more) comparison means groups each of which outputs a predetermined processing request (3) included in the processing request (1) to the interrupt control means via the coincidence signal. And K flip-flops which are set or reset by the K combination pair outputs of the coincidence signals output from the comparison means group and which output a predetermined pulse width modulation signal, and pulse control means.
In addition, the microcomputer interrupts the execution of the processing by the program in the central processing unit in response to the processing request (1) and saves the processing information at the time of the interruption in another storage area, It has a control function of transferring the data set in the memory in advance to the comparison means group and sequentially outputting a plurality of the pulse width modulation signals for each individual cycle set in each comparison means group. Pulse output device characterized by.