JPH087791B2 - Video rate projection calculation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention outputs projection data of an image from a digital video signal at a video rate and allows a memory storing the data to be always read out. Is calculated and stored in one memory while the other memory can be read out from the outside.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image processing, and more particularly to a circuit that calculates projection data of an image at high speed.

Image projection, that is, the data of the horizontal sum of pixel values,
Used for image analysis, pattern recognition, etc., but nowadays
It is required to obtain the result as fast as possible, and it is required to be able to perform projection calculation that is processed in real time according to the video rate, that is, in accordance with the progress of the video signal, and to constantly read the result.

[Prior Art] Conventionally, as a technique for calculating the projection of an image, a video signal is frozen (frozen) and captured as a still image, and a projection result of the image is obtained. An example thereof is shown in FIG.

In this example, the digital video signal is stored in the single screen memory (frame memory), the microprocessor reads the image, and the projection result is calculated.

[Problems to be Solved by the Invention] In the conventional technology, since the processing speed is low, the projection is calculated by reading the data after storing the video signal in the memory once, but the frame memory is required. There is a drawback that it is present and a problem that the result is not output in real time.

The present invention is intended to provide a novel video rate projection calculation circuit that solves the above conventional problems.

[Means for Solving Problems] FIG. 1 shows a principle block diagram of a video rate projection calculation circuit of the present invention.

In the figure, reference numeral 1 is a coordinate generation circuit which receives a clock having a frequency at which one pixel is sent and calculates the coordinates of the current pixel.

Reference numeral 2 is an area setting register for setting an area from the outside.

Reference numeral 3 is a projection mask generation circuit that determines whether or not the current pixel is in the area to be projected.

Reference numeral 4 is a 1-line projection circuit that projects input pixels.

Reference numeral 5 denotes a memory selection generation circuit that selects a memory for the external memory selection signal after one screen is completed.

Reference numeral 6 denotes a memory address selection circuit which gives an external address or an address output from the coordinate generation circuit 1 to each memory according to the output of the memory selection generation circuit 5.

 Reference numerals 7 and 8 are memories for storing projection data.

9 is output from the memory selection and generation circuit 5 to the memory 7
Alternatively, it is an output data selection circuit for selecting the output of the memory 8.

[Operation] With the above configuration, first, the horizontal projection is calculated at the video rate by the pipeline processing, and two memories 7 and 8 are provided as memories for holding the projection result, and switching between them is performed by one screen of an image. By performing and synchronizing with the vertical synchronization signal which is a division between the two, the latest projection result can always be accessed without being aware of the fact that there are two memories.

[Examples] The present invention will be described more specifically with reference to Examples shown in Figs. 2 to 4.

FIG. 2 is a circuit configuration block diagram of an embodiment of the present invention.

In the figure, 11 is a counter (CTR), which uses the horizontal synchronizing signal as a clear input and the clock as a clock input, and outputs the current position coordinate of the pixel in the horizontal direction.

Reference numeral 12 is also a counter (CTR), which uses the vertical synchronizing signal as a clear input and the horizontal synchronizing signal as a clock input, and outputs the current position coordinate of the pixel in the vertical direction.

21,22,23,24 are registers (REG)
Is an external microprocessor (hereinafter abbreviated as MPU)
From the external MPU to the vertical projection start position, the register 23 also stores the horizontal projection end position from the external MPU, and the register 24 into the register 24. Stores the vertical projection end position from the external MPU.

Therefore, the registers 21 to 24 form an area setting circuit for the area to be projected.

Reference numeral 31 is a comparator (COMP), which outputs a high level when the output of the counter 11 becomes equal to or higher than the output of the register 21.
32 is also a comparator (COMP) and outputs a high level when the output of the counter 12 becomes equal to or higher than the output of the register 22.

33 and 34 are also comparators (COMP), but the comparator 33 outputs a high level while the output of the counter 11 is equal to or higher than the output of the register 23, and a low level when the output of the counter 11 is larger than the output of the register 23. Is output.

The comparator 34 outputs a high level while the output of the counter 12 is equal to or less than the output of the register 24, and the output of the counter 12 is the register.
Outputs low level when output exceeds 24.

An AND circuit 35 outputs a high level when all four inputs have a high level.

The comparators 31 to 34 and the AND circuit 35 constitute a projection mask generation circuit, and the fact that the output of the AND circuit 35 is at a high level means that the pixel coordinates are within the designated projection area.

41 is a register with a clear (REG), which uses the output of the AND circuit 35 as a clear input, the clock as a clock input, the digital video signal as a data input, and outputs “0” as the data when the output of the AND circuit 35 is at a low level. Output and AND circuit 35
When the output of is high, it outputs the data input.

An adder (ADD) 42 outputs the addition of the output of the register 41 and the output of the register 43.

43 is a register with clear (REG), which clears the data when the horizontal sync signal is low level, uses the clock as the clock input, and the output of the adder 42 as the data input.

Reference numeral 44 is also a register (REG), which uses the horizontal synchronizing signal as a clock input and captures data from the register 43 at the falling edge of the horizontal synchronizing signal. Therefore, the sum of the pixel values for each line of horizontal scanning is fetched, and the registers 41, 43, 44 and the adder 42 constitute a one-line projection calculation circuit.

Reference numeral 51 is a register (REG) that stores an external memory selection signal from the external MPU. That is, the register 51 outputs a state of selecting the memory 1 as, for example, a high level signal, and outputs a state of selecting the memory 2 as, for example, a low level signal. Then, the state is held until the next external memory selection signal is input.

52 is also a register (REG), which uses the vertical synchronizing signal as a clock input and the output of the register 51 as a data input to update the memory selection signal after the input of one screen is completed. That is, when the vertical synchronizing signal is input to the register 52, the register 52 is set to a memory selected state based on the output from the register 51, for example, by the rising of the vertical synchronizing signal, and the register is registered as described in the exclusive OR circuit described later. Outputs the same memory selection signal as the output of 51. Then, the state is held until the next vertical synchronizing signal is input.

Reference numeral 53 is an exclusive OR circuit (EOR), which receives the output of the register 51 and the output of the register 52 as input, and outputs read OK (low level signal) to the external MPU when the two inputs are the same. The registers 51 and 52 and the exclusive OR circuit 53 form a memory selection generation circuit. Since the external memory selection signal from the external MPU is processed in this manner, the memory to be read can be appropriately selected. In other words, if the memory to be read out is not switched and it is necessary to read it out repeatedly several times, it is effective. If the memory to be read out is switched and read out, the projection calculation result of the latest frame is read out. It is effective in some cases.

61 and 62 are selectors (SELs), both of which output the counter 12 and the address from the external MPU as data input, output of the register 52 as select input, and output the opposite input according to the output of the register 52. .

For example, when the output of the register 52 is high level, the output of the selector 61 is the external MPU address, the output of the selector 62 is the output of the counter 12, and when the output of the register 52 is low level, the output of the selector 61 is The output of the counter 12 and the output of the selector 62 become the external MPU address.

Reference numerals 70 and 80 denote memories (MEM1, MEM2) for storing projection data. The memory 70 uses the output of the selector 61 as an address input and the output of the register 44 as a data input, and when the output of the selector 61 is the output of the counter 12. Store data in memory,
When the output of the selector 61 is the external MPU address, the memory data is output.

The memory 80 is similar to the memory 70 except that the address input is the output of the selector 62, and outputs when the memory 70 stores and stores when the memory 70 outputs.

A selector 90 outputs the read data from the memory 70 or 80 by using the output of the memory 70 and the output of the memory 80 as data inputs and the output of the register 52 as selection inputs.

FIG. 3 is a time chart of the digital video signal in this embodiment.

This embodiment requires that the clock signal is synchronized with the input of each pixel of the digital video signal as shown in the figure.

FIG. 4 is a diagram showing a horizontal synchronizing signal in this embodiment.

As shown in the figure, the period of the horizontal synchronizing signal is 63.5 μs, which is the same as a normal TV signal.
The book has 30 frames / sec.

[Effects of the Invention] According to the present invention as described above, since projection calculation can be performed by pipeline processing, projection can be calculated without a frame memory, and the latest projection can be achieved by providing two memories. The result can always be accessed, and the effect of contributing to the efficiency and speedup of image processing is extremely large.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a circuit configuration block diagram of an embodiment of the present invention, FIG. 3 is a time chart of a video signal in an embodiment of the present invention, and FIG. FIG. 5 is a diagram showing a horizontal synchronizing signal in one embodiment, and FIG. 5 is a block diagram of a conventional example. In the drawing, 1 is a coordinate generation circuit, 2 is a region setting circuit, 3 is a projection mask generation circuit, 4 is a 1-line projection calculation circuit, 5 is a memory selection generation circuit, 6 is a memory address selection circuit, 7 and 8 are memories, 9 is an output data selection circuit, 11 and 12 are counters (CT
R), 21-24, 41, 43, 44, 51, 52 are registers (REG), 31-3
4 is a comparator (COMP), 35 is an AND circuit, 42 is an adder (AD
D), 53 are exclusive OR circuits (EOR), 61 and 62 are selectors (SEL), 70 and 80 are memories (MEM1, MEM2), and 90 is a selector (SEL).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Sato 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Yoshiyuki Ota 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 56) References JP-A 61-117673 (JP, A) JP-A 61-138330 (JP, A) JP-A 57-193853 (JP, A) JP-A 61-9768 (JP, A)

Claims (1)

[Claims] 1. A circuit for obtaining projection data, which is the horizontal sum of pixel values in a specified rectangular area in an image given in the form of a digital video signal, and a clock synchronized with an input pixel. A coordinate generation circuit (1) that calculates the position coordinates of the input pixel on the image by counting, and an area setting circuit (1) that holds the position coordinates of the start point and the end point of the area to be projected given from outside. 2), a projection mask generation circuit (3) that determines whether or not the input pixel is a pixel to be projected, from the output of the coordinate generation circuit (1) and the output of the area setting circuit (2), Video signal and the projection mask generation circuit (3)
1-line projection calculation circuit (4) for calculating the sum of the pixel values of the pixels to be projected for each 1-line
And two memories (7) and (8) for storing projection data
A signal for selecting the two memories (7 or 8) after the input of one screen is generated based on a vertical synchronization output synchronized with the input of one screen and a memory selection signal given from the outside, and A memory selection generation circuit (5) for permitting reading from a selected memory to the outside, and an output from the memory selection circuit (5), the address from the outside to one of the memories (7 or 8), A memory address selection circuit (6) for switching and giving an address of the output of the coordinate generation circuit (1) to the other memory (8 or 7)
And an output data selection circuit (9) for selecting either the output of the two memories (7) or (8) by the output of the memory selection generation circuit (5) Data is calculated to a video rate, one of the two memories is alternately used for storing projection data, and the other is used for reading from the outside. Corresponding to the read permission sent from the memory selection generation circuit (5),
A video rate projection calculation circuit for reading projection data in an arbitrary area of a memory used for reading, based on an address given by the outside.