JPH087949B2 - Writing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write circuit, and more particularly to a write circuit with improved data error detection during writing.

[Prior Art] Conventionally, in a magnetic recording device such as a magnetic disk device, writing of digital data to a recording medium has been performed as shown in FIG. In the data write schematic diagram shown in FIG. 4, the write data transferred from the computer 101 is in 1-byte units with a parity bit added. This write data is used as the parallel-serial converter 104 of the control device 102.
Is converted into 1-bit serial data excluding the parity bit and sent to the modulation circuit 105. The modulation circuit 105 converts these serial data into an RLL code word such as MFM. The converted data 5 is then transferred to the recording timing correction circuit 10
By 6, the correction for the pattern peak shift occurring at the time of data reading is performed. Write data after correction 7
Is a magnetic disk device via the data input / output circuits 42 and 110.
It is sent to 103 and is recorded on the recording medium through the read / write circuit 107 and the magnetic head 108.

On the other hand, at the time of data reading, the data recorded on the recording medium is read by the magnetic head 108 and the read / write circuit 107 and then sent to the read circuit 111 through the data input / output circuits 110 and 42. In the readout circuit 111, phase synchronization, data discrimination,
Processing such as code word inverse conversion and serial-parallel conversion is performed. The read data in 1-byte units is calculated by the computer 10.
It will be transferred to 1.

Here, the recording timing correction circuit 106 is known, for example, in Japanese Patent Laid-Open No. 59-77607. This is because the pattern peak shift that occurs during high density recording, that is, the magnetization reversal position of the data recorded on the recording medium shifts in the direction of the long magnetization reversal interval during reproduction. Therefore, as shown in FIG. 5, by comprising the shift register 1, the pattern identification circuit 2, and the timing correction circuit 3, the shift direction and the shift amount are identified, and the recording timing for the recording medium is determined accordingly. Is corrected so as to cancel the shift.

Further, the write operation of the magnetic disk device does not have the read-after-write function as in the magnetic tape device. For this reason, it is necessary to prevent erroneous data from being recorded due to the failure of the circuit where there is no parity bit.
Therefore, in the shift register 1 of the parallel-serial circuit 104, the modulation circuit 105, and the recording timing correction circuit 106, the number of "1" s of the input data and the output data is counted respectively as described in JP-A-61-68778. After the write operation is completed, "1"
It was detected whether the writing was done correctly by comparing the coincidence of the numbers.

[Problems to be solved by the invention]

The above-mentioned conventional technique is capable of detecting a write error due to a circuit failure or the like that has occurred in a parallel-serial circuit, a modulation circuit, or a shift register in a recording timing correction circuit.

However, write timing due to a failure in the pattern identification circuit and timing correction circuit that make up the recording timing correction circuit, a failure in the data input / output circuit, a break or short circuit in the write data cable, or a defective AC characteristic when integrated into an IC It was not possible to detect the writing error due to the deviation of the line. Further, since the failure itself cannot be detected, there is a problem that it is difficult to perform preventive maintenance by executing the diagnostic program and to investigate the cause of failure of the write circuit.

An object of the present invention is to provide a writing circuit capable of detecting a malfunction in the timing correction circuit and the data input / output circuit.

[Means for solving problems]

The above object is to provide a recording timing correction circuit having a timing correction means for changing the recording timing with respect to a recording medium, which has a shift register, a data input / output circuit for transferring recording data between the recording timing correction circuit and the recording medium, and this data. This is achieved by a write circuit consisting of a write compensation circuit that compares the output of the input / output circuit with the output of the shift register.

[Action]

One output of the flip-flop circuit that constitutes the shift register of the recording timing correction circuit is constantly compared with the read data output of the data input / output circuit at the time of writing, and the error timing is set in the error register using the clock timing set in the timing correction circuit. By setting it, the failure can be detected. The timing of each of the above signals is based on the data output, and the timing at which the output of the flip-flop with the same timing should be compared among the flip-flops forming the shift register is delayed in the clock timing for setting in the timing correction circuit. Determined by

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. still,
The same parts are designated by the same reference numerals.

FIG. 1 shows the configuration of a write circuit which is an embodiment of the present invention. This write circuit receives write data 5 as an input,
The shift register 1 that shifts the bits of the input write data 5 each time the clock 4 is applied, and the predetermined bit of the data input 5 set in the shift register 1 are detected, and the state of the detected bit ( "1" or "0")
By adopting the condition of, the pattern identification circuit 2 for identifying whether or not the write bit at the specific position is, for example, a pattern in which a pattern peak shift occurs, and recording of each bit based on the identification result of the pattern identification circuit 2. A timing correction circuit 3 for controlling the timing, and a data input / output circuit 42 for sending the write data output from the timing correction circuit 3 during writing to the magnetic disk device 103 and returning the write data to the write compensation circuit 8. And the data input 5 and data input / output circuit set in the shift register 1.
Write compensation circuit 8 for comparing with write data returned from 42
Can be roughly divided into The shift register 1 is composed of flip-flops (hereinafter referred to as FF) 12 to FF 18, and the pattern identification circuit 2 receives the bit state of the shift register 1 and outputs "1" for each recording timing according to the bit state. AND circuit combined with
It is composed of 24. Furthermore, the timing correction circuit 3
It is composed of delay elements 31 to 33 for changing the timing according to the output from the pattern identification circuit 2, FFs 36 to 39 and an OR circuit 45. In addition, the write compensation circuit 8
An exclusive OR circuit 35 which receives the bit state of the shift register 1 and the output state of the data input / output circuit 42,
The delay element 34, the AND circuit 25, and the FF 40 are included.

Next, the operation of the write circuit thus configured will be described with reference to FIGS. First, the data input 5 which is the output of the modulation circuit 105 is sequentially shifted from FF18 to FF12 at the timing of the clock 4. FF12 and FF15 are "1" and FF18
Is 0, the output of the AND circuit 21 is set in the FF 36 at the timing of the clock 6. Clock 6 is delay element 31
Through clocks 6a, 6b, whose timings are sequentially delayed,
Obtain 6c and 6d. Here, each value of the delay elements 31 to 33 is about 5 to 30% of the cycle T of the clock 4 and the clock 6. When the clock 6a is the normal timing N, the clock 6 is the early timing E, and the clocks 6b and 6c are the late timings L and LL, respectively. FF15 is "1", FF12
And when FF18 is "0", the output of AND circuit 22 is a clock.
It is set to FF37 at the timing of 6a. FF12, FF15 and F
When F18 is "1", the output of the AND circuit 23 is set to FF38 at the timing of the clock 6b. Also, FF15 and FF18
Is "1" and FF12 is "0", the output of the AND circuit 24 is set to FF39 at the timing of the clock 6c. Each FF36
The output of the FF 15 set to 39 through 39 becomes the input data 7 at the time of writing in the bidirectional data input / output circuit 42 through the OR circuit 45.

FIG. 2 shows the details of the data input / output circuit 42. At the time of writing, since the write control signal 44 becomes −V, the differential input data 7 which is good for the DRV (driver) becomes the write data 41 via Tr ₁ and Tr ₂ , and the write / read circuit 107. Through the recording medium 109. On the other hand, the write data 41 can obtain the read data output 43 at the time of writing via Tr ₃ and Tr ₄ . This read data output 43 is compared with the output of the FF 14 as an input of the exclusive OR circuit 35, and is set in the error register 40 through the AND circuit 25 at the timing of the clock 6d which is the output of the delay element 34. If the contents of the read data output 43 and the output of FF14 do not match at the timing of clock 6d, the error output that is the output of error register 40
10 is set. If this error output is set,
The write operation failure is reported to a higher-level model such as the computer 101. The error output 10 is held until the reset signal 9 is output.

〔The invention's effect〕

According to the present invention, it is possible to detect the write failure caused by the recording timing correction circuit and the write failure caused by the input / output circuit at the same time, so that the reliability of the write circuit can be greatly improved. You can Further, in the case of a write failure due to a disconnection or a short circuit of the write data cable, the relevant portion may be replaced and the like, so that the maintenance efficiency is excellent.

[Brief description of drawings]

1 is a block diagram showing a schematic configuration of a write circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of a data input / output circuit, and FIG. 3 is a document shown in FIG. FIG. 4 is a schematic diagram of data writing of a magnetic disk device of a conventional computer system, and FIG. 5 is a schematic diagram of a conventional writing circuit with a corrected recording timing. 1 ... shift register, 2 ... pattern identification circuit, 3 ...
... Timing correction circuit, 8 ... Write compensation circuit, 12 to 18,3
6-39 …… Flip-flop, 21-25 …… AND circuit, 3
1 to 34 …… Delay element, 35 …… Exclusive OR circuit, 4
0 ... Error register, 42 ... Data input / output circuit, 106 ...
... Recording timing correction circuit, 109 ... Recording medium.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noboru Sakurai 2880 Kozu, Odawara, Kanagawa Stock company Hitachi Odawara factory (56) References JP 61-68778 (JP, A) JP 50- 159937 (JP, A) JP-A-58-102315 (JP, A)

Claims (1)

[Claims] 1. A shift register for shifting a bit of input write data at a clock timing, and a shift pattern generated at the time of reproduction after recording is discriminated by a bit in the data set in the shift register. A shift pattern identifying circuit for outputting write data together with the written pattern, and a delay means for delaying the clock, and each of the write data based on the identified pattern by the clock output from the delay means. A timing correction circuit for controlling the output timing,
A bidirectional data input / output circuit that sends out the write data output from the timing correction circuit to the magnetic recording device at the time of writing and returns the write data, and a return write from the data input / output circuit Means for inputting and comparing the input data set in the shift register, the setting timing of which is substantially equal to the return write data of the data and the shift register, the error register in which the comparison result is set, and the timing A write compensating circuit having means for determining the timing at which the error register is set by delaying the clock output from the delay means of the correction circuit, the write circuit comprising: The data and the input data are always compared by the write compensation circuit, and when the comparison result does not match, Write circuit comparison result, characterized in that it is set in the error register.