JPH088236B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method for manufacturing a semiconductor device using a positive resist.

2. Description of the Related Art Methods for processing a film formed on a semiconductor substrate in a process of manufacturing a semiconductor device include dry etching and wet etching. 2. Description of the Related Art In recent years, dry etching, which enables highly accurate processing, is becoming the mainstream as semiconductor devices are made finer.

Hereinafter, a conventional method for manufacturing a semiconductor device in which dry etching of a film formed on a semiconductor substrate and subsequent resist formation are performed will be described.

In FIG. 3A, an NPN transistor before aluminum wiring is formed by the N ⁺ diffusion layer 8b and the P ⁺ diffusion layer 7c in a region surrounded by the P ⁺ diffusion layer 7a and the P ⁺ diffusion layer 7b. . P
^An N ⁺ diffusion layer 8a is formed on the left side of the ⁺ diffusion layer 7b.
Furthermore, the surface of the silicon substrate is covered with a thermal oxide film 2 (thickness of about 2000Å) formed by thermal oxidation, and then a PSG film 3 (thickness of about 2000Å) formed by the low pressure CVD method.
⁺ A part of the thermal oxide film 2 and the PSG film 3 on the diffusion layer 8a is opened by the steps of exposing / developing and etching the resist. After that, the silicon nitride film 4 is about 600 Å by low pressure CVD method.
Growing up. Further, a positive resist 5a (thickness: 1.3 μm) is formed on the silicon nitride film 4 above the opening on the N ⁺ diffusion layer 8a by exposure and development.

After that, the silicon nitride film 4 is subjected to CF ₄ + O ₂ gas plasma dry etching using the positive resist 5a as a mask for selective etching (FIG. 3B). Further, the positive resist 5a is removed by oxygen plasma etching (FIG. 3C), and then a pattern of the positive resist 5b is formed to open a contact window between the element and the aluminum wiring (FIG. 3D). Further, the PSG film 3 and the thermal oxide film 2 are wet-etched with a hydrofluoric acid-based chemical using the formed positive resist 5b as a selective etching mask (FIG. 3E). After that, the positive resist 5b is removed, the aluminum wirings 9a to 9e are formed, and the protective film 11 is formed in the final product (FIG. 3F).

In FIG. 3F, an NPN transistor is formed in a region surrounded by P ⁺ , diffusion layer 7a, and P ⁺ diffusion layer 7b, and aluminum wirings 9a, 9b, 9c are respectively collectors of the NPN transistor. It corresponds to an electrode, a base electrode, and an emitter electrode. Further, a capacitor using the silicon nitride film 4 as an interlayer insulating film is formed in the left side region of the P ⁺ diffusion layer 7b, and the aluminum wirings 9d and 9e are both electrodes of the capacitor.

However, according to the above-mentioned conventional method, when the silicon nitride film 4 is dry-etched by CF ₄ plasma, the altered layer 6 is formed on the surface of the PSG film 3 and the positive layer is formed by oxygen plasma etching. The altered layer 6 is not removed even by the step of removing the resist 5a. Therefore, when the positive resist 5b is continuously formed, the adhesive force of the positive resist 5b is reduced due to the influence of the altered layer 6, and when the positive resist 5b is used as a selective etching mask, the PSG film 3 and the thermal oxide film 2 are wet-etched. , Lateral spread during etching (hereinafter referred to as side etching) becomes large.

Therefore, in an extreme case, since the contact window to the N ⁺ diffusion layer has a large side etch, it spreads to the adjacent P-type diffusion layer and the transistor characteristics cannot be obtained. Furthermore, if the contact window becomes larger than the aluminum wiring due to the large side etch, the aluminum wiring cannot sufficiently cover the contact window,
The transistor characteristics deteriorate. In other words, the deteriorated layer formed at the time of dry etching has a drawback that the adhesive force of the resist which is subsequently performed is lowered and the selective etching using the resist cannot be performed with high accuracy.

The present invention solves the above-mentioned conventional problems, and provides a method for manufacturing a semiconductor device, which improves an altered layer of a semiconductor substrate surface after dry etching and improves the adhesion of a positive resist formed immediately after that. It is in.

Means for Solving the Problems In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention comprises a first insulating film formed on a semiconductor substrate and a second insulating film formed on the first insulating film. When forming a pattern with the film, a step of dry etching the second insulating film with a plasma containing CF ₄ gas using a positive resist formed at a predetermined position on the second insulating film as a mask, and thereafter, A step of etching the positive resist by about half with oxygen plasma, a step of thereafter treating the semiconductor substrate with fuming nitric acid, and wet-etching the positive resist remaining in the previous step without leaving, and then a new positive step on the semiconductor substrate. And applying a resist to form a pattern on the first insulating film.

Action With this configuration, when the second insulating film is etched by plasma etching using CF ₄ gas, an altered layer presumed to be a C-F polymer is generated, but after etching the positive resist by about half with oxygen plasma, Since the semiconductor substrate is treated with fuming nitric acid, the remaining positive resist and the deteriorated layer are removed at the same time, and the adhesion between the semiconductor substrate and the resist can be improved during the subsequent resist formation.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to FIG. 1 by one example.

In FIG. 1A, an NPN transistor before aluminum wiring is formed by the N ⁺ diffusion layer 8b and the P ⁺ diffusion layer 7c in a region surrounded by the P ⁺ diffusion layer 7a and the P ⁺ diffusion layer 7b. P ⁺
An N ⁺ diffusion layer 8a is formed on the left side of the diffusion layer 7b. More silicon substrate surface, the thermal oxide thermal oxide film 2 formed by (a thickness of about 2000Å), then, are covered by the PSG film 3 having a thickness of approximately 2000Å which is formed by low pressure CVD, N ⁺ A part of the thermal oxide film 2 and the PSG film 3 on the diffusion layer 8a is opened by the steps of exposing / developing and etching the resist. After that, the silicon nitride film 4 is grown by about 600Å by the low pressure CVD method. Further, a positive resist 5a (thickness: 1.3 μm) is formed on the silicon nitride film 4 on the opening on the N ⁺ diffusion layer 8a by exposure and development.
μm) is formed.

Then, the silicon nitride film 4 is subjected to CF ₄ + O ₂ gas plasma dry etching using the positive resist 5a as a mask for selective etching. However, the silicon nitride film 4
When CF ₄ + O ₂ gas plasma dry etching is performed, PSG
The altered layer 6 which is presumed to be a C-F polymer is formed on the membrane 3 (Fig. 3B). Up to this point, it is the same as the conventional example, but thereafter, even if about half the positive resist 5a is removed by oxygen plasma etching, the altered layer 6 is not removed (FIG. 3C). However, after that, fuming nitric acid treatment
After about 30 minutes, the remaining positive resist 5a is removed and, at the same time, the altered layer 6 is improved (FIG. 1D). In the fuming nitric acid treatment used here, a method of immersing a silicon wafer in a bath in which fuming nitric acid was circulated and filtered through a filter for about 30 minutes was applied. A method of immersing the silicon substrate in the three baths every 10 minutes may be applied.

Then, a pattern of the positive resist 5b is formed to open a contact window with the aluminum wiring of the device (FIG. 1E). Further, the PSG film 3 and the thermal oxide film 2 are wet-etched with a hydrofluoric acid-based chemical using the formed positive resist 5b as a selective etching mask (FIG. 1F).
After that, the positive resist 5b is removed to remove the aluminum wiring 9a.
~ 9e is formed, and the protective film 11 is formed on the final product (first
Fig. G).

In FIG. 1G, an NPN transistor is formed in a region surrounded by the P ⁺ diffusion layer 7a and the P ⁺ diffusion layer 7b, and the aluminum wirings 9a, 9b and 9c are respectively the collector electrode of the NPN transistor, It corresponds to the base electrode and the emitter electrode. Further, a capacitor using the silicon nitride film 4 as an interlayer insulating film is formed in the left side region of the P ⁺ diffusion layer 7b, and the aluminum wirings 9d and 9e are both electrodes of the capacitor.

As described above, according to the present embodiment, fuming nitric acid is used in the resist removing step after the dry etching of the silicon nitride film 4 when the capacitor capacitance using the silicon nitride film as the insulating film is formed after the NPN transistor is formed. By adding the treatment, it becomes possible to improve the altered layer 6 on the PSG film formed at the time of dry etching of the silicon nitride film 4, and therefore, the positive resist 5b to be subsequently performed.
The adhesive force of the positive resist 5b at the time of formation is improved, and the PSG film 3
Therefore, high-precision processing of the thermal oxide film 2 is possible. for that reason,
The contact window to the N ⁺ diffusion layer spreads to other diffusion layers, and the problem that the contact window becomes too wide to cover the contact window with aluminum wiring is significantly reduced. The tolerance of the mask alignment error at the time of forming the window also becomes large.

The effects of this embodiment are shown in FIGS. 2A and 2B. Fig. 2A
Shows the cross-sectional shape and dimensions of the opening. The horizontal axis of FIG. 2B shows the sample name. For the conventional method (a, b, c) and the present embodiment (d, e, f) and three silicon substrates,
The measurement was carried out every two points on the substrate. The vertical axis is the size of the opening after wet etching, and the opening length above the opening is
l ₁ and the length of the opening at the bottom of the opening are shown as l ₂ . Also,
The resist opening dimension l is 3.6 μm.

It is clear from FIG. 2B that the opening size (both l ₁ and l ₂ ) of this embodiment is closer to the resist opening size, that is, the side etching is smaller than that of the conventional example. The bottom dimension of the opening l ₂ has a large effect on the transistor characteristics.
However, for the resist opening dimension 1 of 3.6 μm,
In the prior art opening lower dimension l ₂ is 4.4 [mu] m, in the present embodiment has an opening lower size 4.0 .mu.m, side etching (l ₂ -
l) is 0.8 μm in the conventional example and 0.4 μm in this example,
In this example, since the adhesiveness of the resist was improved, the side etch could be reduced to 50% of that in the conventional example.

In this example, a thermal oxide film, P
The example of forming the SG film and the silicon nitride film in this order has been described, but it does not have to be a three-layer structure of a thermal oxide film, a PSG film, and a silicon nitride film, and other materials (for example, NSG) are also the same. The effect of can be obtained.

Further, in the present example, fuming nitric acid treatment was used for the purpose of both resist removal and improvement of the deteriorated layer, but it is not particularly required to be combined with resist removal, and it is possible to improve the deteriorated layer alone. May be used for

EFFECTS OF THE INVENTION According to the present invention, when the second insulating film is etched by plasma etching using CF ₄ gas, an altered layer presumed to be a C—F polymer is produced, but the positive resist is halved by oxygen plasma. After etching, the semiconductor substrate is treated with fuming nitric acid, so that the remaining positive resist and the altered layer can be removed at the same time, and the adhesion of the resist that is subsequently formed can be improved. Can be realized.

[Brief description of drawings]

1A to 1G are process cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a characteristic diagram comparing the effects of the present invention and a conventional example, and FIGS. FIG. 6 is a process sectional view of a method for manufacturing a semiconductor device. 1 ... Silicon substrate, 2 ... Thermal oxide film, 3 ... PSG film,
4 ... Silicon nitride film, 5a, 5b ... Positive resist, 6 ...
Altered layer, 7a, 7b, 7c …… P ⁺ diffusion layer, 8a, 8b …… N ⁺ diffusion layer, 9
a-9e …… Aluminum wiring, 10 …… Epitaxial layer, 11 …… Protective film.

Claims (1)

[Claims] 1. A first insulating film formed on a semiconductor substrate,
Further, in patterning the second insulating film formed on the second insulating film, the positive resist formed at a predetermined position on the second insulating film is used as a mask, and the second resist is formed by the plasma containing CF ₄ gas. A step of dry-etching the insulating film, then a step of etching the positive resist by about half with oxygen plasma, and thereafter, the semiconductor substrate is treated with fuming nitric acid, and the positive resist left in the previous step is wet-etched without remaining. A method of manufacturing a semiconductor device, comprising: a step of applying a new positive resist to the semiconductor substrate and then pattern-forming the first insulating film.