JPH088342B2 - Semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high integration technology of a semiconductor integrated circuit device having a stacked capacitor.

[Prior Art] In recent years, in order to meet the demand for microelectronics in industrial and consumer equipment, VLSI (Very Large Scale Integrated Circuit), which is a larger scale LSI (Large Scale Integrated Circuit), has been developed.
It is put to practical use. Especially in the semiconductor memory device,
The storage capacity has increased about 1000 times in the last 10 years. The progress of such high integration has been realized by reducing the size of the unit memory element forming the semiconductor memory device as much as possible by mainly using the means of proportional reduction.

A dynamic random access memory (DRAM) will be described below as an example of such a semiconductor integrated circuit device. DRAM holds a signal as an electric charge stored in a capacitor. Since the accumulated charge decreases due to leakage, DR
A periodic refresh operation is required in AM. In DRAM, it is possible to access target information with a constant access time regardless of the storage location.

In DRAM, the memory cell area will inevitably decrease with miniaturization. The amount of charges that can be accumulated in the memory cell region decreases with the decrease in the area of the memory cells having the same structure. With the progress of miniaturization, the amount of charge stored in the memory cell has become extremely small, and the reliability has been remarkably reduced due to a soft error or the like.

As measures against this, various attempts have been made to improve the storage capacity of the memory cell. One of such improving means is disclosed in Japanese Patent Publication No. 61-55258. The invention disclosed in this publication relates to a memory cell having a stacked capacitor. FIG. 15 is a sectional view showing the structure of an example of a memory cell provided with the above-mentioned stacked capacitor formed on a silicon substrate. FIG. 16 is a circuit diagram of a memory cell corresponding to FIG. Reference numerals common to FIGS. 15 and 16 indicate the same or corresponding portions. The names given to those corresponding parts are the same.

Referring to FIG. 15 and FIG. 16, this memory cell is an N-channel MOS (M-MOS) formed on the main surface of P-type semiconductor substrate 7.
(etal-Oxide Semiconductor) transistor 11 and a stacked capacitor 15 connected to the drain of transistor 11 and formed on the main surface of P-type semiconductor substrate 7. An interlayer insulating film 22 is formed on the memory cell, and a bit line 8 made of polysilicon or metal is formed thereon.

The N-channel transistor 11 is formed on the main surface of the P-type semiconductor substrate 7 with N ⁺ impurity regions 5 formed at intervals from each other.
a and 5b, and a transfer gate 4 formed on the main surface between impurity regions 5a and 5b via a gate oxide film. The stacked capacitor 15 is an impurity region
The storage node 1 made of polysilicon or the like formed so as to be connected to the 5b via the contact hole 18.
And a thin dielectric film 3 formed on the storage node 1.
And a cell plate 2 formed of polysilicon on the dielectric film 3 to cover the storage node 1. The stacked capacitor 15 is formed so as to cover the transistor 11 and the element isolation region 6.

Bit line 8 is connected to impurity region 5a through contact hole 9 formed in interlayer insulating film 22. This memory cell is different from other memory cells including the impurity region 5c, etc.
It is isolated by an element isolation region 6 made of a thick oxide film. The transfer gate 4 is connected to the word line 10.

Writing of information to this memory cell is performed as follows. A high-level (hereinafter simply referred to as "H") or low-level (hereinafter simply referred to as "L") potential according to the information to be written is applied to the bit line 8. Word line 10
Is activated, the potential of the transfer gate 4 becomes "H", and the transistor 11 is turned on. Stacked capacitors
The charge corresponding to the potential of the bit line 8 is accumulated in 15. The bit line 8 is inactivated and the potential of the transfer gate 4 becomes "L". The transistor 11 is turned off, and the accumulated charge remains in the stacked capacitor 15.

In the memory cell using the stacked capacitor, the stacked capacitor 15 can be formed so as to cover the transfer gate 4 and the element isolation region 6.
Therefore, even if the memory cell area is reduced, a certain amount of storage capacity can be secured.

In the following, a conventional 3-transistor DRAM cell is described. After that, the application of the above-mentioned stacked capacitor to the three-transistor DRAM is described.

FIG. 17 is a circuit diagram showing an example of a memory cell of a 3-transistor DRAM. Referring to FIG. 17, this memory cell has a write select line 110, a read select line 120, and a write data line 10.
8. Connected to the read data line 121. This memory cell includes three N-channel MOS transistors 11, 12, 122.

Transistor 11 includes a gate 4 connected to write select line 110 and a source connected to write data line 108.
Transistor 12 includes a storage gate 14 connected to the drain of transistor 11 and a drain connected to ground line 123. Transistor 122 includes a gate connected to read select line 120, a drain connected to the source of transistor 12, and a source connected to read data line 121.

The operation of the 3-transistor DRAM shown in FIG. 17 is described below. In writing data, the write data line 108
"H" or "L" corresponding to the data to be written in the cell
Is applied. The potential of "H" is applied to the write selection line 110. The potential of the transfer gate 4 of the transistor 11 becomes "H", and the transistor 11 is turned on. The charge corresponding to the potential of the write data line 108 is stored in the storage gate 14 of the transistor 12.

The transistor 11 is turned off by setting the potential of the write selection line 110 to “L”. The charge corresponding to the write data remains in the storage gate 14, and the writing is completed.

The data is held in the gate capacitance of the storage gate 14 as accumulated charges. Therefore, this RAM cell is a dynamic type and requires a refresh operation.

In the DRAM cell of FIG. 17, electric charges are stored in the capacitance of the storage gate 14 of the transistor 12 as data as described above. Since the storage gate 14 is capacitively coupled to the drain or source of the transistor 12, the potential of the storage gate 14 is easily affected by the potential fluctuation of the drain or source. Since the accumulated charge is small with only the gate capacitance,
Data may be destroyed due to a soft error or the like. Even in the data reading, the reliability of the operation is low because the read potential difference is small. In addition, since the capacity is small, it is necessary to repeat the refresh operation frequently.

In order to increase the storage capacity, it is effective to add a capacitor to the memory cell. FIG. 18 is a circuit diagram of a DRAM cell in which a capacitor 15 is added to the DRAM cell of FIG. First
The circuit shown in FIG. 18 is the same as that shown in FIG. 17 except for the added capacitor 15. FIG. 19 is an enlarged circuit diagram of the rectangular portion A shown by the dotted line in FIG. FIG. 20 is a sectional view showing the structure of a semiconductor integrated circuit device corresponding to FIG. Common symbols in FIGS. 19 and 20 indicate the same or corresponding portions.

Referring to FIG. 19 and FIG. 20, the circuit A is an N-channel transistor 11 formed on the main surface of a P-type semiconductor substrate 7.
And a capacitor connected to the drain of transistor 11
15, a transistor 12 formed in a region on the main surface of the semiconductor substrate 7 separated from the transistor 11 and the capacitor 15 by the element isolation region 6, and a drain for connecting the drain of the transistor 11 and the gate of the transistor 12 to each other. And a wiring 16 made of polysilicon or metal.

The transistor 11 has a gate oxide on the main surface of the semiconductor substrate 7 in a region between the N ⁺ impurity regions 5a and 5b formed on the main surface of the semiconductor substrate 7 and spaced from each other and the impurity regions 5a and 5b. And a transfer gate 4 made of polysilicon formed across the film.

The capacitor 15 has a contact hole on the impurity region 5b.
A storage node 1 made of polysilicon formed by being connected via 18, a thin dielectric film 3 formed on the storage node 1, and a polysilicon film on the dielectric film 3 so as to cover the storage node 1. And the formed cell plate 2. The impurity region 5b is formed between the transfer gate 4 and the element isolation region 6.

The transistor 12 is the semiconductor substrate 7 separated by the element isolation region 6 from the region where the transistor 11 is formed.
Spaced apart from each other in the region on the main surface of N ⁺
Impurity regions 5c and 5d and storage gate 14 formed on the main surface of semiconductor substrate 7 between impurity regions 5c and 5d with a gate oxide film therebetween are included.

An interlayer insulating film 22 is formed on the memory cell, and the write data line 10 made of polysilicon or metal is formed on the interlayer insulating film 22.
8 are formed. The wiring 16 is connected to the impurity region 5b by a contact hole 17a formed in the interlayer insulating film 22, and is connected to the storage gate 14 by a contact hole 17b. Write data line 108 is connected to impurity region 5a through contact hole 9 formed in interlayer insulating film 22.

The operation of the memory cell of the above-described 3-transistor DRAM is the same as that of the memory cell of the above-described 3-transistor DRAM having no capacitor. Therefore, detailed description thereof will not be repeated. The improvement in this device is that the storage capacitor of the memory cell is significantly increased because the stacked capacitor 15 is provided in the memory cell. As a result, the data retention capacity of the memory cell and the reliability during reading can be improved.

In the following, in the above-mentioned stacked capacitor,
Applications to semiconductor integrated circuit devices other than DRAM are described.
Dynamic CAM with stacked capacitor (C
ontent Addressable Memory). FIG. 21 is a schematic block diagram of a general CAM. Referring to FIG. 21, the CAM is composed of a CAM array 1000 as a storage area having an array of CAM cells which are unit storage elements, and a C
Data written to AM array 1000 or CAM array 1
For comparing one of the n word lines of the CAM array 1000 in response to an externally applied address signal and an m-bit data register 3000 whose data to be compared with the memory contents of 000 is externally applied. Address decoder 2000
A match line sense amplifier 1100 for amplifying a signal appearing on a match line provided for each word of CAM at the time of data search, a search result register 1200 for storing the output of the match line sense amplifier 1100, and a search And an address encoder 1300 for outputting the storage address of the stored data.

Since the CAM array 1000 is defined by m bit lines and n word lines, the CAM array 1000 can store binary data of n words × m bits.

FIG. 22 is a diagram schematically showing the arrangement of CAM cells in the CAM array 1000. Referring to FIG. 22, CAM array 1000
Are a plurality of bit lines 8a and inverted bit lines 8b that are alternately arranged in the horizontal direction and extend in the vertical direction, and a plurality of word lines 10 and match lines 19 that are alternately arranged in the vertical direction and extend in the horizontal direction.
A pair of bit line pairs 8a and 8b, a pair of word lines 10 and a match line 19
Bit line pairs 8 provided in each of the areas surrounded by
a, 8b, word line 10, and CAM cell 20 connected to match line 19. A match line sense amplifier 1100 is connected to the end of the match line 19.

An outline of the operation of the CAM will be described with reference to FIGS. 21 and 22. In writing, the following operations are sequentially performed.

(1) Write data (m bit width) is input to the data register 3000.

(2) The data in the data register 3000 is the CAM array 1000.
Are applied to all bit line pairs 8a and 8b.

(3) An external address signal (log ₂ n bit width) is input to the address decoder 2000, the address is decoded, and the corresponding word line is selected.

(4) The potential of "H" is applied to the corresponding word line 10. The data on each bit line pair 8a, 8b is written to each corresponding CAM cell 20 connected to the selected word line 10.

(5) The potential of the word line 10 is lowered to "L" again.

With the above, writing of data to the CAM is completed. A specific method of storing data in the CAM 20 will be described later.

The search operation is one of the important functions of CAM. In the search operation, the data previously stored in the CAM array 1000 is collated with the search data provided to the data register 3000, and the address of the matched data is output from the address encoder sensor 1300. The search operation includes the following steps.

(1) Search data (m-bit width) is input to the data register 3000.

(2) The data in the data register 3000 is the CAM array 1000.
Are applied to all bit line pairs 8a and 8b.

(3) In n words of the CAM array 1000, the stored data of each word is compared with the search data provided to the bit line pair 8a, 8b. The result of the comparison is the match line 19
Is output to

(4) The search result output to the match line 19 of each word is
The match line sense amplifier 1100 amplifies.

(5) The search result amplified by the match line sense amplifier 1100 is written in the search result register 1200 corresponding to each word. At this time, only the register corresponding to the word in which the stored data and the search data match is set.

(6) In response to the output of the search result register 1200, the address encoder 1300 outputs the address corresponding to the word in which the stored data and the search data match.

Since the read operation in CAM is not common,
The description is omitted here.

As a dynamic type CAM, for example, "IEEE Journal
al of Solid-state Circuits '' (vol.SC-7, pp.36
6) has been proposed in. FIG. 23 is a circuit diagram of an example of such a CAM cell 20.

Referring to FIG. 23, this memory cell 20 has word line 1
0, bit line 8a, inverted bit line 8b, match line 19 are connected. The memory cell 20 includes five n-channel MOS transistors 11a, 11b, 12a, 12b and 13. Transistor 11
Gates 4a and 4b of a and 11b are both connected to the word line 10. Each source is connected to the bit line 8a and the inverted bit line 8b, respectively.

The storage gates 14a and 14b of the transistors 12a and 12b are connected to the drains of the transistors 11a and 11b, respectively. The sources are connected to the bit line 8a and the inverted bit line 8b, respectively. The source of the transistor 13 is connected to the drains of the transistors 12a and 12b via the node 21.

The gate and drain of transistor 13 are both match lines
Connected to 19. The transistor 13 functions as a diode.

In the following, the operation of writing data into the CAM cell 20 and collating the data stored in the CAM cell 20 will be described.

Write Operation (1) The data to be written in the cell is supplied to the bit line 8a and the inverted bit line 8b.

(2) The potential of the word line 10 is set to "H". As a result, the potentials of the transfer gates 4a and 4b of the transistors 11a and 11b become "H". The transistors 11a and 11b are turned on.

(3) Storage gates 14a and 14b of the transistors 12a and 12b
Then, the data corresponding to the potentials of the bit line pair 8a, 8b is written.

(4) The potential of the word line 10 is returned to "L". The transistors 11a and 11b are turned off.

(5) The stored data in the cell is held as accumulated charges in the gate capacitances of the accumulation gates 14a and 14b. Since the potentials of the bit line 8a and the inverted bit line 8b are changed complementarily, the signals stored in the storage gates 14a and 14b are complementary to each other. The CAM cell 20 is of a dynamic type and requires a refresh operation like the DRAM cell.

Matching operation Referring to FIGS. 23 and 25 to 30, the CAM cell 2 will be described below.
The matching operation at 0 is described. 25 to 27B,
The state where "H" data is stored in the storage gate 14a and "L" data is stored in the storage gate 14b is shown. 28 to 30 show the storage gate 14
The state where "L" is stored in a and "H" is stored in the storage gate 14b is shown.

(1) The bit line 8a and the inverted bit line 8b are precharged to "H".

(2) Matching line 19 is precharged to "H". Since the transistor 13 is turned on, the potential of the node 21 becomes “H”. The matching line 19 is brought into an electrically isolated state (floating state) from the others (see FIGS. 25 and 28).

(3) Search data is given to the bit line 8a and the inverted bit line 8b. As described above, the potentials applied to the bit line pairs 8a and 8b have complementary values.

(4) When the search data and the stored data match, the charge on the match line 19 is not discharged, and the potential remains at "H". In the case of a mismatch, the charge on match line 19 is a transistor
Discharge to the bit line 8a via 12a or to the inverted bit line 8b via the transistor 12b, and the potential of the match line 19 becomes "L". The reason for this will be described later.

(5) A plurality of CAM cells 20 are connected to one word line 10. The comparison is done over all word lines 10 and over all CAM cells 20.

If even one of the CAM cells connected to one word line 10 does not match the stored data with the collation data, the charge given to the match line 19 paired with that word line 10 is It is discharged to the bit line 8a or the inverted bit line 8b via the CAM cell. The potential of the match line 19 becomes "L".

When the stored data and the collation data match in all the CAM cells connected to one word line 10, the charges given to the match line 19 corresponding to the word line 10 are not discharged. As a result, the potential of the matching line 19 is kept at "H".

Therefore, by detecting the match line 19 remaining at "H", the word in which the data matching the search data is stored can be known.

The reason why the potential of the match line 19 stays at “H” only when the search data and the data stored in the CAM cell 20 match will be described below. As shown in FIG. 25, the case where the data “H” is stored in the storage gate 14a and the data “L” is stored in the storage gate 14b is taken as an example.

(1) When "H" is applied to the bit line 8a and "L" is applied to the inverted bit line 8b.

Referring to FIG. 26, the source and drain of transistor 12a have the same potential, and transistor 12a does not turn on. The storage gate 14a of the transistor 12b is "L", and the transistor 12b does not turn on. Therefore, the electric charge of the match line 19 does not flow anywhere, and its potential is kept at “H”.

(2) When "L" is applied to the bit line 8a and "H" is applied to the inverted bit line 8b.

Referring to FIG. 27A, storage gate 14 of transistor 12b
a is “H”, source is “L”, drain (node 21) is “H”
Therefore, the transistor 12a is turned on. The charge on match line 19 passes from node 21 through transistor 12a to bit line 8a.
Is pulled out. The potential of the match line 19 becomes "L" (27B
See figure).

As described above, the potential of the match line 19 remains “H” in the case of coincidence, while the potential becomes “L” in the case of disagreement.

On the contrary, a state in which "L" is stored in the storage gate 14a and "H" is stored in the storage gate 14b is shown in FIGS. 28 to 30. In this case, as shown in FIGS. 29A and 29B, when the stored data and the search data do not match, the transistor 12b is turned on and the charge on the match line 19 is extracted to the inverted bit line 8b. The potential becomes "L". On the other hand, as shown in FIG.
When the stored data and the search data match, the potential of the node 21, that is, the match line 19 remains at “H”.

Therefore, the potential of "H" appears on the match line 19 only when the data stored in the storage gates 14a and 14b and the data applied to the bit line pair 8a and 8b match. Since the storage data is stored in the storage gates 14a and 14b in the form of stored charges, it goes without saying that it is desirable that the amount of the stored charges is stable.

However, as in the case of the above-described 3-transistor DRAM cell, the storage gates 14a and 14b are capacitively coupled to the drain or the source. The potential is easily affected by the potential fluctuation of the drain or the source. Since the accumulated charge is small with only the gate capacitance, there is a risk of data destruction due to a soft error or the like. Since the read potential difference is small, the reliability also decreases when reading data. It is also necessary to repeat the refresh operation frequently.

As in the case of DRAM, it is effective to add a capacitor to the CAM cell in addition to the gate capacity in order to increase the storage capacity. FIG. 24 shows the capacitor 15a in the CAM cell 20 of FIG.
It is a circuit diagram of a CAM cell to which 15b is added. The CAM cell shown in FIG. 24 is the same as that shown in FIG. 23 except for the added capacitors 15a and 15b.

An associative memory cell circuit similar to this CAM cell is disclosed, for example, in Japanese Patent Laid-Open No. 62-267998. The circuit diagram of the rectangular portion B shown by the dotted line in FIG.
It is similar to the circuit diagram in the figure. Therefore, the sectional view showing the structure of the rectangular portion B is similar to FIG. However, the write data line 108 is replaced by the bit line 8a.

As is apparent from the above description, referring again to FIG. 20, when storage node 1 needs to be electrically conducted to storage gate 14 of MOS transistor 12, the following are required. That is, a connection wiring 16 for connecting the N ⁺ impurity region 5b connected to the storage node 1 and the storage gate 14, and a contact hole 17a for connecting the connection wiring 16 and the N ⁺ impurity region 5b are required. It is said that
Of course, the contact hole 17b for connecting the connection wiring 16 and the storage gate 14 is also required.

Not limited to the above case, generally, the capacitor is often electrically connected to the conductive layer other than the impurity region to which the capacitor is directly connected. FIG. 31 is a sectional view showing the structure of such an example circuit.

Referring to FIG. 31, N ⁺ impurity regions 5a, 5b and 5c are formed on P type semiconductor substrate 7. Impurity region 5a and impurity region 5b are separated by element isolation region 6b. Impurity region 5b and impurity region 5c are separated by element isolation region 6c. The impurity region 5a is isolated from other regions by the element isolation region 6a. The impurity region 5c is isolated from other regions by the element isolation region 6d.

A stacked capacitor 15 is formed on the impurity region 5a. Impurity region 5a and impurity region 5c are connected to each other through contact holes 17a and 17b by connection wiring 16 made of polysilicon, metal, or the like. The stacked capacitor 15 includes a storage node 1 connected to the impurity region 5a through a contact hole 18, a dielectric film 3 formed on the storage node 1, and a dielectric film 3
And a cell plate 2 formed of polysilicon or the like.

In the circuit described above, the stacked capacitor 15 is connected to the impurity region 5c via the connection wiring 16. In this case, contact holes 17a and 17b for connecting the connection wiring 16 to the impurity regions 5a and 5c are required.

[Problems to be Solved by the Invention] The conventional semiconductor integrated circuit device having a stacked capacitor is configured as described above, and is more effective for higher integration and reliability than a device without a capacitor. is there. However, as the degree of integration of semiconductor integrated circuit devices further increases, the following problems to be solved still exist.

For example, when electrically connecting a storage node to a conductive layer other than the diffusion region to which it is directly connected,
A wiring for connecting the diffusion region and the conductive layer and a contact hole for connecting the diffusion region and the wiring for connection are required. By providing the wiring for connection and the contact hole, the layout area of the semiconductor integrated circuit device inevitably increases, which not only hinders high integration but also causes a cost increase.

Stacked capacitors cannot be formed in the contact holes. Therefore, there is a limit in increasing the storage capacity of the stacked capacitor. This is also a factor that hinders high integration of the semiconductor integrated circuit device.

Further, by providing the contact hole for the connection wiring, the area of the diffusion region to which the storage node is connected is increased. PN between diffusion region and semiconductor substrate 7
The area of the junction is large, and the accumulated charges are likely to leak there, and the reliability of the operation is reduced.

The conventional semiconductor integrated circuit device having a stacked capacitor has the above-mentioned problems. Therefore, an object of the present invention is to provide a semiconductor integrated circuit device having a capacitive element, which can be highly integrated and can operate with high reliability.

[Means for Solving the Problem] A semiconductor integrated circuit device according to the present invention includes a semiconductor substrate having a main surface, a first conductive region formed on the main surface, and a first conductive region formed on the main surface. A second region formed to be spaced apart from the region and electrically connected to the first conductive region;
And a capacitive element connected to the first conductive region and the second conductive region. The capacitive element is connected to the first conductive region and the second conductive region, and includes a first conductive layer for electrically connecting the first conductive region and the second conductive region, and a first conductive layer. It includes a dielectric film formed on the conductive layer and a second conductive layer formed on the dielectric film.

[Operation] In the semiconductor integrated circuit device having the above-described configuration, the first conductive region and the second conductive region are electrically connected by the first conductive layer. The first conductive layer simultaneously forms a capacitive element with the dielectric film and the second conductive layer.
Since the first conductive layer, which is a part of the capacitor, is also used as the wiring, the wiring for independent connection becomes unnecessary. Moreover, at least one of the contact holes for connection, which is required when the independent wiring is provided, is unnecessary. The area of the first conductive region or the second conductive region can be reduced accordingly. Further, compared to the case where the independent wiring is provided, there are few obstacles when forming the capacitive element, and conversely, since the wiring portion can be used, a larger capacitive element can be formed. Therefore,
The amount of charges accumulated in the capacitor can be increased, and the area of the semiconductor integrated circuit device can be reduced.

[Embodiment] FIG. 1 shows a sectional view of a main portion of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 1 shows the structure of a portion corresponding to the circuit diagram shown in FIG. Therefore, the semiconductor integrated circuit device of this embodiment can be applied to the 3-transistor DRAM cell shown in FIG. 18 and the CAM cell shown in FIG. An example of the application will be described later with reference to the drawings.

Referring to FIG. 1, a semiconductor integrated circuit device according to the present invention includes a P-type semiconductor substrate 7 and an N-channel MOS formed on a main surface of semiconductor substrate 7 with element isolation regions 6 therebetween.
It includes transistors 11 and 12, and a stacked capacitor 15 that connects the gate of transistor 12 and transistor 11 and at the same time functions as a capacitive element. An interlayer insulating film 22 is formed on these semiconductor composites, and a bit line 8 made of polysilicon or metal is further formed thereon.

Transistor 11 includes N ⁺ impurity regions 5a and 5b formed at a distance from each other on one region on the main surface of semiconductor substrate 7 separated by element isolation region 6 and an impurity region.
The transfer gate 4 is formed on the region of the semiconductor substrate 7 between 5a and 5b via a gate insulating film.

Transistor 12 includes N ⁺ impurity regions 5c and 5d formed at a distance from each other on the other region on the main surface of semiconductor substrate 7 separated by element isolation region 6 and an impurity region.
A storage gate 14 formed via a gate insulating film is included on a region of semiconductor substrate 7 between 5c and 5d.

The stacked capacitor 15 is formed on the storage node 1 and the storage node 1 made of polysilicon or the like, which is connected to the impurity region 5b through the contact hole 18 and the storage gate 14 through the contact hole 17, respectively. It includes a thin dielectric film 3 and a cell plate 2 formed of polysilicon or the like on the dielectric film 3 so as to cover the storage node 1.

Impurity region 5a and bit line 8 are connected via a contact hole 9 formed in interlayer insulating film 22.

As described above, a circuit diagram corresponding to the semiconductor integrated circuit device shown in FIG. 1 is shown in FIG. Therefore, such a structure can be directly applied to a 3-transistor DRAM cell, a CAM cell, or the like. The operation of the circuit shown in FIG. 19 has already been described and will not be repeated here.

A characteristic of the structure shown in FIG. 1 is that the area of the charge storage portion of the stacked capacitor 15 is dramatically increased as compared with the conventional one, and nevertheless the integrated circuit device It is possible to reduce the area.

The storage node 1 is one electrode of the stacked capacitor 15 and at the same time plays a role as a connection wiring for connecting the impurity region 5b and the storage gate 14. The connection wiring 16 as shown in FIG. 20 is no longer necessary. The contact hole 17a for connecting the connection wiring 16 to the impurity region 5b is also unnecessary. The lateral area of the impurity region 5b can be reduced accordingly. Impurity region
Since the area of the PN junction at the interface between 5b and the semiconductor substrate 7 is also reduced, the leakage current from this portion is reduced. The charges accumulated in the storage node 1 are held more stably, and the operation reliability of the circuit having this structure is improved.

Since the connection wiring 16 is unnecessary, the following effects are also produced. Conventionally, even if an attempt is made to expand the charge storage portion of the stacked capacitor 15, the expansion is limited due to the existence of the connection wiring 16. However, in the semiconductor integrated circuit device of the present invention, there is no obstacle to expanding the charge storage region of the stacked capacitor 15. Therefore, as shown in FIG. 1, storage node 1 and cell plate 2 can be provided over transistor 11 and transistor 12, respectively. The area of the storage node 1 is dramatically increased as compared with the conventional one, and it becomes possible to secure a sufficient storage capacity even if the integration of the semiconductor integrated circuit device is further advanced.

FIG. 2 is a sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention. With reference to FIG. 2, this device has a P-type semiconductor substrate 7 and a main surface of the semiconductor substrate 7,
N ⁺ impurity regions 5a, 5b, 5c formed spaced apart from each other
And a stacked capacitor 15 connected to the impurity regions 5a and 5c.

An element isolation region 6b is provided between the impurity region 5a and the impurity region 5b. An element isolation region 6c is provided between the impurity region 5b and the impurity region 5c. Impurity region 5a is isolated from other regions by element isolation region 6a. The impurity region 5c is separated from the other regions by the element isolation region 6d.

The stacked capacitor 15 is connected to the impurity region 5a through the contact hole 18a and the contact hole 18b.
Storage node 1 connected to impurity region 5c through
And a thin dielectric film 3 formed on the storage node 1.
And a cell plate 2 formed on the dielectric film 3 so as to cover the storage node 1. An interlayer insulating film 22 is formed on these semiconductor composites.

In the device shown in FIG. 2, the impurity region 5a
And impurity region 5c are connected to each other by storage node 1. The impurity region 5b is the other impurity region 5a,
Insulated from 5c. As shown in FIG.
By connecting the two impurity regions 5a and 5c by the storage node 1 and forming the stacked capacitor 15 having the storage node 1 as one electrode, the area for forming the capacitor can be greatly saved.

By using the capacitive element having such a structure in the semiconductor integrated circuit device, it is possible to secure a large degree of integration of the semiconductor integrated circuit device and reliability of operation. Even in the case of a device in which the high integration has been conventionally sacrificed due to the need for a large-capacity capacitor, the high integration can be achieved by adopting the structure shown in FIG. Can proceed. As a result, it is possible to realize a significant cost reduction.

The semiconductor integrated circuit device shown in FIG. 2 is equivalent to the semiconductor integrated circuit device shown in FIG. The storage capacity of the stacked capacitor 15 itself is much larger than the conventional one, and the contact hole 17 for the connection wiring 16 is provided.
Since it is unnecessary to provide a, the area of the impurity region 5a can be reduced. The leakage current from the PN junction at the interface between the impurity region 5a and the semiconductor substrate 7 is also reduced, and the potential change of the storage node 1 is much smaller than that in the conventional case in combination with the dramatic increase in accumulated charges.

FIGS. 3A to 3D are side sectional views of the essential part showing the manufacturing procedure of the semiconductor integrated circuit device of the embodiment shown in FIG.
Referring to FIG. 3A, the impurity concentration is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-3
By selectively oxidizing the main surface of the P-type semiconductor substrate 7, the element isolation region 6 made of a thick oxide film (thickness of about 6000Å) is formed.

The gate oxide film of the N-channel MOS transistors 11 and 12 is formed on the active region where the element isolation region 6 is not formed to a film thickness of 200 Å.
Form a degree. Polysilicon is deposited to a film thickness of about 5000Å by the CVD (Chemical Vapor Deposition) method. The transfer gate 4 of the transistor 11 and the storage gate 14 of the transistor 12 are formed by dry etching the polysilicon layer using the resist as a mask. N ⁺ impurity regions 5a to 5d are formed by ion-implanting arsenic with a doping amount of about 1 × 10 ¹⁶ cm ^-2 .

Referring to FIG. 3B, an oxide film is deposited with a film thickness of about 5000Å by the CVD method. By performing dry etching on this oxide film, sidewalls 26 are left only at the edge portions of transfer gate 4 and storage gate 14. The oxide film 24 is deposited on the entire surface of the semiconductor composite by the CVD method to a film thickness of about 5000Å. Contact holes 17 and 18 are formed by dry etching the oxide film 24 using the resist as a mask.

Referring to FIG. 3C, a polysilicon layer is deposited with a film thickness of about 2000 Å by the CVD method. The storage node 1 is formed by dry etching this polysilicon layer using a resist as a mask. By depositing a nitride film having a film thickness of about 100Å on the storage node 1 by the CVD method, the dielectric film 3 of the stacked capacitor 15 is formed.
Is formed. 2000 Å on the dielectric film 3 by CVD method
A polysilicon layer is deposited with a film thickness of about 100 nm. Wet etching is performed using the polysilicon layer as a mask to form the cell plate 2, and thus the stacked capacitor 15 is formed.

Referring to FIG. 3D, a thick interlayer insulating film 22 is deposited on the stacked capacitor 15. For the interlayer insulating film 22,
By performing dry etching using the resist as a mask, contact hole 9 is formed on impurity region 5a. An AlSi alloy is vapor-deposited on the entire surface of the interlayer insulating film 22 by the sputtering method. Bit line 8 is formed by etching the deposited metal using a resist as a mask. A nitride film 25 for chip protection is formed thereon by a low temperature CVD method.

Through the above steps, the semiconductor integrated circuit device shown in FIG. 1 is manufactured.

FIG. 4A is a CAM when the technique of the semiconductor integrated circuit device of the present invention is applied to the CAM cell shown in the circuit diagram of FIG.
It is a schematic plan view of a cell. FIG. 4B is a schematic plan view showing the arrangement of elements in the left half of the CAM cell shown in FIG. 4A. FIG. 4C is an equivalent circuit diagram of the CAM cell of FIG. 4A. FIG. 5 is a sectional view taken along the line VV of FIG. 4A. FIG. 6 is a sectional view taken along line VI-VI in FIG. 4A. FIG. 7 is a sectional view taken along the line VII-VII in FIG. 4A.

Referring to FIGS. 4A to 7, the CAM cell as the third embodiment of the present invention has a bilaterally symmetrical planar shape. This C
In the AM cell, the active region 4 is formed on the P-type semiconductor substrate 7.
Element isolation regions 6 for defining 7 and 48 are formed. In the active region 48, the N ⁺ impurity regions 5a and 5b are respectively formed.
It is formed along the lateral direction in FIG. 4A. Active area
In N 47, N ⁺ impurity regions 5c, 5d, and 5e are formed along the vertical direction in FIG. 4A.

A word line 10 extending in the lateral direction is formed on the main surface of semiconductor substrate 7 in a region between impurity regions 5a and 5b with a gate oxide film therebetween. Word line shown in Figure 4A
10 'is a word line of another CAM cell adjacent to the upper side. A storage electrode 14a is formed on the active region 47 between the impurity region 5c and the impurity region 5d along the vertical direction in FIG. Between the impurity region 5d and the impurity region 5e on the active region 47, a gate electrode 34 having an inverted L-shaped planar shape is formed on the semiconductor substrate 7 via a gate oxide film.

Storage gate electrode 14a, gate electrode 34 and impurity region 5
A storage node 1 made of polysilicon is formed above b, 5c, 5d and 5e. Storage node 1
It is connected to the storage gate electrode 14a through the contact hole 17 and to the impurity region 5b through the contact hole 18. A cell plate 2 made of polysilicon is formed on the storage node 1 with a dielectric film 3 therebetween. The cell plate 2 is a CA of this semiconductor integrated circuit device.
It is formed so as to cover the entire surface where the M array is formed.

Above the edge of the active region 47 of the CAM cell, a matching line 19 made of polysilicon is formed extending in the lateral direction. The coincidence line 19 extends upward in the center of the CAM cell. A bit line 8a made of polysilicon is formed to extend vertically in the upper portion along the left edge of the CAM cell. A bit line 8a 'for connection extending from the bit line 8a toward the upper portion of the active region 48 is provided, and the connection bit line 8a' is connected to the impurity region 5a via the contact hole 32. There is. The cell plate 2 around the contact hole 32 is provided with an opening 32 for forming the contact hole 32.
In addition, the cell plate 2 is also used where necessary.
An opening for making a contact is formed in the.
The bit line 8a ′ is an active region through the contact hole 27.
It is connected to 47 impurity regions 5c.

The matching line 19 is connected to the active region through the contact hole 29.
It is connected to the central portion of 47, that is, the impurity region 5e.
Matching line 19 is also connected to gate electrode 34 via contact hole 28. In FIG. 4A, the right half of the CAM cell is symmetrical to the left half. However, a subscript “b” is added to each element in the right half instead of the subscript “a” of each element in the left half.

With particular reference to FIGS. 4B and 4C, an N-channel transistor 11a is formed below the word line 10. An N-channel transistor 12a is formed below the storage gate 14a. The N-channel transistor 13 is formed below the gate electrode 34.

Impurity region 5b, which is one terminal of transistor 11a, is connected to storage gate 14a of transistor 12a through contact hole 18, storage node 1, and contact hole 17. The sources of the transistor 12a and the transistor 13 are connected in the impurity region 5d. The gate electrode and drain of the transistor 13 are
The contact line 28, the impurity region 5e, and the contact hole 29 are connected to the matching line 19, respectively.

The storage node 1, the dielectric film 3, and the cell plate 2 form a stacked capacitor 15a. Therefore, the equivalent circuit diagram of the CAM cell shown in FIG. 4A is
It will be as shown in Figure 4C.

The equivalent circuit diagram of the CAM cell shown in FIG. 4C is equivalent to the circuit diagram of the CAM cell shown in FIG. The operation is as already described and will not be repeated here.

The characteristic point of this CAM cell is that the area of the storage node 1 is very large. This is made possible by providing the storage node 1 with a function as a wiring for connecting the transistor 11a and the storage gate 14a of the transistor 12a. That is, since it is not necessary to provide an independent connection wiring, the storage node 1 can be made very large.

Due to the larger area of the storage node 1,
The amount of charge stored in the storage node 1 has dramatically increased as compared with the case of the conventional stacked capacitor. CAM cell storage gate electrode 14a and capacitor 15a
The amount of electric charge stored in the semiconductor device is sufficiently large, and a semiconductor integrated circuit device having sufficiently high reliability can be obtained even if the degree of integration is further increased.

FIG. 8 shows a simplified circuit diagram of an analog multiplier as a fourth embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 9 is a circuit diagram showing the circuit diagram of FIG. 8 in more detail. Referring to FIG. 8, the analog multiplier is provided between the switch SW1 for connecting and disconnecting the input terminal T1 and the node NA in synchronization with the clock signal φ1 and between the node NA and the ground potential GND. , A switch SW2 for connecting and disconnecting in synchronization with the clock signal φ2, a capacitor C1 whose one electrode is connected to the node NA and whose other electrode is connected to the node NB, and which are provided between the node NB and the ground potential GND. , A switch SW3 for connecting and disconnecting in synchronization with the clock signal φ2, a capacitor C2 provided between the node NB and the ground potential GND, a positive input to the node NB, and a negative input to its own output. And a connected operational amplifier OP1. The operational amplifier OP1 is a voltage follower connection and outputs the potential of the node NB to the output Vout as it is.

The operation of the analog multiplier shown in FIG. 8 is described below. Figure 10 shows clock signals φ1 and φ2 and input terminals
FIG. 6 is a timing diagram showing the relationship between the input voltage Vin from T1 and the output Vout of the operational amplifier OP1. Referring to FIGS. 8 and 10, first, the clock signal φ2 becomes “H”, and the switch SW
2, SW3 turns on. As a result, the potential of the node NANB is
It becomes 0V. At this time, Vout is 0V. Then, the clock signal φ2 becomes "L". This allows the switches SW2, SW3
Turns off. Clock signal φ1 goes to "H", switch
SW1 turns on. Input voltage Vin is applied to node NA.
Due to the capacitive coupling of the capacitor C1, the potential of the node NB becomes
It changes to the value shown in the following formula.

Vin × C1 / (C1 + C2) (1) Since the operational amplifier OP1 is a voltage follower connection as described above, the potential of the node NB is directly output to Vout.

In the above analog multiplier, it is assumed that the capacitors C1 and C2 have the following relationships.

C1 = k × C2 (2) At this time, the relationship between Vin and Vout is as follows.

Vout = Vin × k / (k + 1) (3) As is apparent from the equation (3), by changing the value of k, the output voltage V obtained by multiplying the input voltage Vin by an arbitrary coefficient.
You can get out.

In the circuit diagram shown in FIG. 9, an N-channel transistor 35 is used as the switch SW1. An N-channel transistor 36 is used as the switch SW2. N-channel transistor 3 as the switch SW3
7 is used. The part surrounded by the alternate long and short dash line in FIG. 9 constitutes the operational amplifier OP1. Since the operational amplifier OP1 has no direct relation to the present invention, detailed description of its structure and operation is omitted. However, it should be noted that the operational amplifier OP1 includes the P-channel transistor 49, and its gate is connected to the node NB. The reference voltage Vref1 in the circuit diagram
Is used as a reference voltage for limiting the current flowing through the operational amplifier OP1.

Referring to FIG. 9, a circuit portion α shown by a dotted line includes transistors 37 and 49 and a capacitor C2, and has a configuration similar to that of circuit A shown in FIG. Therefore, the circuit portion α can be realized by the structure shown in the sectional view of FIG.

In the analog multiplier, capacitors C1, C2, and C3 require considerably large capacitance. Therefore, they also require a large area. By using the stacked capacitor according to the present invention that also serves as the connection wiring, the area occupied by the circuit portion α can be significantly reduced.

The technique of the semiconductor integrated circuit device according to the present invention can be applied to the circuit portion β of the operational amplifier OP1. The circuit part β is
N-channel transistor N1 and P-channel transistor
Includes P1 and capacitor C3. One electrode of the capacitor C3 is connected to one electrode of another N-channel transistor 50 included in the operational amplifier OP1.

The gate electrode of the N-channel transistor N1 is connected to one terminal of the P-channel transistor 49 and one terminal of the N-channel transistor 50. The drain of the N-channel transistor N1 is connected to the ground potential Vss, and the source is connected to the drain of the P-channel transistor P1.

The source of the P-channel transistor P1 is connected to the power supply voltage Vcc, and the reference voltage Vref1 is applied to the gate. The other electrode of the capacitor C3 is a P-channel transistor
It is connected to the drain of P1 and the source of the N-channel transistor N1. Output voltage from the connected portion of P-channel transistor P1 and N-channel transistor N1
You can get Vout.

The technology of the semiconductor integrated circuit device according to the present invention can also be applied to the circuit portion β. FIG. 11 is a plan view of this circuit portion when the circuit β is realized by applying the technique of the present invention. FIG. 12 is a sectional view taken along line XII-XII in FIG. FIG. 13 is a sectional view taken along line XIII-XIII in FIG. FIG. 14 is a sectional view taken along line XIV-XIV in FIG.

11 to 14, this semiconductor integrated circuit device includes a P-type semiconductor substrate 7, and the main surface of semiconductor substrate 7 is divided into two regions by N-type well 38 formed on semiconductor substrate 7. Is divided into

A high-concentration N ⁺ impurity region 46 is formed as a guard ring at the boundary between the N-type well 38 and a portion where the N-type well 38 is not formed. An element isolation region 6b is provided in a portion of the N-type well 38 adjacent to the N ⁺ impurity region 46. An element isolation region 6a is formed on the surface of the N-type well 38 at a predetermined distance from the element isolation region 6b, and an active region 39 is defined between the element isolation region 6a and the element isolation region 6b. A polysilicon wiring layer 43 to which a power supply voltage Vcc is applied is provided on the element isolation region 6a, a part of which is the active region 39.
Protruding above.

Two P-channel transistors P are provided on the active region 39.
1, P1 'is formed. A portion 43 ′ of the polysilicon wiring layer 43 protruding above the active region 39 is further an N ⁺ impurity region.
It extends above 46 and is connected to N ⁺ impurity region 46 by a contact hole. A polysilicon wiring layer 4 to which a reference voltage Vref1 is externally applied is provided on the element isolation region 6b.
1 is provided, and two projecting portions 45, 45 'are formed along both sides of the polysilicon wiring layer 43'.

The P-channel transistor P1 includes a P ⁺ impurity region 39a formed on the active region 39, a P ⁺ impurity region 39b formed between the impurity region 39a and the semiconductor substrate 7 between the impurity regions 39a and 39b. And a polysilicon wiring layer 45 formed via a gate oxide film. The polysilicon wiring layer 45 is the gate electrode of the P-channel transistor P1.

The P-channel transistor P1 'is formed on the semiconductor substrate 7 in the region between the P ⁺ impurity region 39c formed on the active region 39, the impurity region 39b, and the impurity regions 39b and 39c via the gate oxide film. And a polysilicon wiring layer 45 '.
The polysilicon wiring layer 45 'is the gate electrode of the transistor P1'.

On the surface of the main surface of the semiconductor substrate 7 other than the region where the N-type well 38 is formed, an element isolation region 6c formed along the boundary with the N-type well 38 and an element isolation region 6c. An element isolation region 6d formed at a distance to define the active region 40, two N-channel transistors N1 and N1 'formed on the active region 40, and the element isolation region 6d are disposed above the element isolation region 6d. Polysilicon wiring layer 44 connected to Vss
And a polysilicon wiring layer 42 which is provided on the element isolation region 6c and to which the output voltage V1 from the P-channel transistor 49 in FIG. 9 is input.

A part of the polysilicon wiring layer 44 projects above the active region 40 to form a polysilicon wiring layer 44 '. The polysilicon wiring layer 42 projects above the active region 40 along both sides of the polysilicon wiring layer 44 ', and the polysilicon wiring layers 51, 5 are formed.
Forming 1 '.

The N-channel transistor N1 includes an N ⁺ impurity region 40a formed on the active region 40, an N ⁺ impurity region 40b formed at a distance from the impurity region 40a, and a region between the impurity regions 40a and 40b. It includes a polysilicon wiring layer 51 formed on the semiconductor substrate 7 with a gate oxide film interposed therebetween. The polysilicon wiring layer 51 is the gate electrode of the transistor N1.

The N-channel transistor N1 'is formed on the semiconductor substrate 7 in a region between the N ⁺ impurity region 40c formed on the active region 40, the impurity region 40b, and the impurity regions 40b and 40c via a gate oxide film. And the polysilicon wiring layer 51 'is formed. The polysilicon wiring layer 51 'is the gate electrode of the transistor N1'. The polysilicon wiring layer 44 'is connected to the impurity region 40b by a contact hole. The polysilicon wiring layer 43 'is also connected to the impurity region 39b by a contact hole.

In this embodiment, the guard ring is provided only on the N-type well 38. However, N-type well
Guard rings may be similarly provided in regions other than 38.

A characteristic of this semiconductor integrated circuit device is that the capacitor C3 is used as a wiring for connecting the P ⁺ impurity regions 39a and 39c and the N ⁺ impurity regions 40a and 40b. The capacitor C3 is composed of transistors P1, P1 ', N
1. A storage node 1 made of polysilicon that covers P1, N1 ′ and is connected to P ⁺ impurity regions 39a and 39c and N ⁺ impurity regions 40a and 40c by contact holes, and a dielectric formed on the storage node 1. The body film 3 and the cell plate 2 formed on the dielectric film 3 so as to cover the storage node 1 are included. The storage node 1 serves as a wiring that connects the drains of the P-channel transistors P1 and P1 ′ and the sources of the N-channel transistors N1 and N1 ′.

Generally, it is desirable that the transistors P1, P1 ', N1, N1' have a large channel width in order to reduce the output impedance. Further, as described above, a large capacitance is required for the capacitor C3. for that reason,
When realizing the circuit part β, a considerably large area is required. However, as shown in the embodiment of the present invention, by using the storage node 1 as a wiring, it is possible to design the transistor and the stacked capacitor in an overlapping manner.

As shown in FIGS. 11 to 14, the storage node 1 should be designed to cover all of the P-channel transistors P1 and P1 'and N-channel transistors N1 and N1' to obtain a very large area. You can Therefore,
The channel width of each transistor can be made sufficiently large, and the charge storage capability of the capacitor can be sufficiently ensured. As is clear from the present embodiment, the semiconductor integrated circuit device according to the present invention realizes a semiconductor integrated circuit device which can achieve higher integration and which can be expected to operate with high reliability. can do.

It is considered that the gist of the idea of the present invention has been clarified by the above-described embodiment. However, the invention is not limited to the embodiments described above. INDUSTRIAL APPLICABILITY The present invention positively uses a conductor layer used as wiring as a capacitor, and can be applied to a wide variety of circuits that require a capacitor.

[Effects of the Invention] As apparent from the above description, in the semiconductor integrated circuit device according to the present invention, the first conductive region and the second conductive region are electrically connected by the first conductive layer. It The first conductive layer simultaneously forms a capacitive element together with the second conductive layer.

Since the first conductive layer which is a part of the capacitor is also used as a wiring, an independent connection wiring is not required, and the first conductive layer and the second conductive layer can be formed over a sufficiently large area. Is possible. The space required for providing independent wiring can also be omitted. Therefore, the amount of charge accumulated in the capacitor can be increased. Moreover, the area of the semiconductor integrated circuit device can be reduced. By increasing the amount of charge stored in the capacitor, the reliability of the operation of the semiconductor integrated circuit device using the capacitor is improved, and the semiconductor integrated circuit device can be further highly integrated.

That is, it is possible to provide a semiconductor integrated circuit device having a capacitive element which can be highly integrated and can operate with high reliability.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing a structure of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view of an essential part of a semiconductor integrated circuit device according to a second embodiment of the present invention. 3A to 3D are sectional views showing a manufacturing process of the semiconductor integrated circuit device shown in FIG. 1, and FIG. 4A is a part of a CAM cell of a third embodiment of the present invention. FIG. 4B is a broken plan view, FIG. 4B is a schematic plan view showing the arrangement of elements in the left half of FIG. 4A, and FIG. 4C is an equivalent circuit diagram of the CAM cell of FIG. 4A. 5 is a sectional view taken along line VV of FIG. 4A, FIG. 6 is a sectional view taken along line VI-VI of FIG. 4A, and FIG. 7 is taken along line VII-VII of FIG. 4A. FIG. 8 is a sectional view taken in the direction of the arrow, FIG. 8 is a simplified circuit diagram of the analog multiplier of the fourth embodiment of the present invention, and FIG. 9 is a schematic diagram of the analog multiplier shown in FIG. The details 10 is a timing diagram showing the operation of the analog multiplier shown in FIGS. 8 and 9, and FIG. 11 is an analog multiplier of the fourth embodiment of the present invention. FIG. 12 is a plan view showing an essential part of FIG. 12, FIG. 12 is a sectional view taken along line XII-XII in FIG. 11, and FIG. 13 is a sectional view taken along line XIII-XIII in FIG. 14 is a sectional view taken along the line XIV-XIV in FIG. 11, FIG. 15 is a sectional view showing the structure of a conventional DRAM cell, and FIG. 16 is an equivalent circuit diagram of the conventional DRAM cell. Yes, FIG. 17 is an equivalent circuit diagram of a three-transistor DRAM cell, FIG. 18 is an equivalent circuit diagram of a three-transistor DRAM cell having a capacitor, and FIG. 19 is a circuit diagram of the circuit shown in FIG. 20 is an enlarged circuit diagram of a main part, FIG. 20 is a cross-sectional view of a conventional semiconductor integrated circuit device corresponding to the circuit diagram shown in FIG. 19, and FIG. 21 is a CAM. FIG. 22 is a block diagram, FIG. 22 is a schematic plan view showing the arrangement of CAM cells in a CAM array, FIG. 23 is an equivalent circuit diagram of the CAM cells, and FIG. 24 is a CAM cell having a capacitor. FIG. 25 is an equivalent circuit diagram, FIGS. 25 to 30 are schematic diagrams showing the operation of the CAM cell, and FIG. 31 is a sectional view of a conventional semiconductor integrated circuit device. In the drawing, 1 is a storage node, 2 is a cell plate, 3 is a dielectric film, 4, 4a and 4b are transfer gates, 7 is a P-type semiconductor substrate, 8 and 8a are bit lines, 8b is an inverted bit line, 10
Is a word line, 11, 11a, 11b, 12, 12a, 12b, 13 are N-channel transistors, 14, 14a, 14b are storage gates, 15, 15
a, 15b are stacked capacitors, 19 is a matching line, 20 is CAM
Represents a cell. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 11/34 352 Z

Claims (1)

[Claims] 1. A semiconductor substrate having a main surface, a first conductive region formed on the main surface, a first conductive region formed on the main surface with a space between the first conductive region, and A second conductive region to be electrically connected to the first conductive region; and a capacitive element connected to the first conductive region and the second conductive region, wherein the capacitive element is the first conductive region. A first conductive layer for electrically connecting the conductive region and the second conductive region, a dielectric film formed on the first conductive layer, and a dielectric film formed on the dielectric film. And a second conductive layer.