JPH088494B2 - Code conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is used for transmission of pulse signals. In particular, it relates to a code conversion method for converting an input code into a code suitable for transmission.

[Summary] The present invention is an mBnB code conversion method for converting an input m (m is a natural number) bit code into a code of n = m + 1 bits, and two types of mBnB code conversion are performed by inserting identification bits. Then, by selecting and transmitting a code suitable for transmission, a conversion correspondence table between the transmission side and the reception side is not required, and high-speed and low power consumption code conversion is performed with a simple circuit configuration.

[Conventional technology]

A code for converting an m-bit code into an n-bit is called an mBnB code and is used as a code for a PCM communication line, especially for an optical PCM communication line. Of these, the 5B6B code is often used for practical purposes.

In the conventional mBnB code, in general, a specific code combination is selected from the output codes of n = m + 1 bits for the input code of m bits and made to correspond thereto. That is, there are 2 ^m combinations of input codes, and 2 ⁿ = 2 for this 2 ^m combinations.
The code suitable for the transmission condition is selected and used from the ^{m + 1} combinations of n-bit codes. The transmission conditions are selected based on the fact that the mark rate of the code is close to 1/2, the same code continuity is small, etc. In order to approach these conditions, two sets of n bits are set for an m-bit code. In some cases, the signs of the bits are made to correspond.

[Problems to be solved by the invention]

In such a conventional code conversion for converting m bits to n bits, an n-bit code corresponding to an m-bit code has no logical conversion rule between the codes, so that from m bits to n bits and n bits. To m bits conversion,
Since it is necessary to prepare a conversion correspondence table in advance, and the circuit configuration for this is complicated, low power consumption and high speed have been hindered.

It is an object of the present invention to provide a code conversion method that does not require a conversion correspondence table on the transmitting side and the receiving side.

[Means for solving problems]

According to the code conversion method of the present invention, the input side receives m
(M is a natural number) n = m + 1 suitable for transmitting a bit code
In the code conversion method, which is provided with mBnB code conversion means for converting into a bit code, and the receiving side is provided with means for converting the above n = m + 1 bit code into the original m bit code,
On the transmitting side, a bit at a predetermined position of the m-bit code is converted into a complementary code, a bit indicating that the complementary code conversion has been performed is inserted into a specific bit, and a first n-bit code is output. And a second code conversion means for outputting a second n-bit code by inserting a bit indicating that complementary code conversion has not been performed into the specific bit, and the first code conversion means. For the n-bit code and the second n-bit code, there are provided means for comparing the numbers of adjacent codes which are different codes, and means for selecting and outputting the n-bit code having the larger number, The side is provided with means for performing code conversion by two different logics based on the value of the specific bit.

[Work]

The code conversion system of the present invention has logical regularity in conversion from m bits to n bits or vice versa.

In the code conversion method of the present invention, two n-bit codes are generated, and one of them is selected and transmitted. Half of the specific position of the input m-bit code or an integer bit before and after the half number is converted into a complementary code, and 1 bit indicating "yes" of the complementary code conversion is added and converted into a first n = m + 1 bit code. . Also,
A second n-bit code is obtained by adding 1 bit indicating "none" of complementary code conversion to the input m-bit code. Among these two n-bit codes, the number of code change points is compared, and the n-bit code with many change points is output. On the receiving side, one bit indicating the presence / absence of complementary sign conversion is detected from n bits, and other m bits are directly output when there is no complementary sign conversion, and among the m bits when there is complementary sign conversion. The bits that have been subjected to complementary sign conversion are returned to the original and output.

〔Example〕

FIG. 1 shows a block diagram of a transmitting side code converter according to an embodiment of the present invention.

The m-bit parallel conversion circuit 11 is connected to the non-conversion circuit 12 and the complementary code conversion circuit 13. The non-conversion circuit 12 and the complementary code conversion circuit 13 are connected to the change point number comparison circuit 14. Further, one of the output of the non-conversion circuit 12 and the output of the complementary code conversion circuit 13
It is output to the receiving side via the switch circuit 15 connected to the change point number comparison circuit 14.

The m-bit parallel conversion circuit 11 parallel-converts the input serial code A into m-bit units. The non-conversion circuit 12 inserts a bit indicating that the complementary code conversion is not performed at a specific position of the code A ′ output from the m-bit parallel conversion circuit 11, and n =
The code B of m + 1 bits is output. Complementary sign conversion circuit 13
Indicates that the bit at the predetermined position of the code A ′ and the bit at the predetermined position of the code A ′ are used as complementary codes, and that the non-conversion circuit 12 has performed the code conversion at the same position as the position where the bit is inserted. Insert a bit. As a result, the code C of n = m + 1 bits is output. The number of bits to convert to a complementary code is
When m is an even number, it is half, and when m is an odd number, it is an integer value before and after that half.

The non-conversion circuit 12 and the complementary code conversion circuit 13 further determine whether adjacent bits of the code generated by themselves are complementary codes or the same code, and output the numbers D and E of different codes to the change point number comparison circuit 14, respectively. To do. The change point comparison circuit 14 is a switch circuit 15
Is controlled to select the code B or C having a large number of change points and send it as the code G to the receiving side. If the number of change points is the same, it is determined in advance that either the code B or C is selected or alternately transmitted.

 FIG. 2 shows a block diagram of the receiving side code converter.

The n-bit parallel conversion circuit 21 is connected to the complementary code conversion circuit 22. The complementary code conversion circuit 22 is connected to the m-bit serial conversion circuit 23.

The n-bit parallel conversion circuit 21 parallel-converts the input code G code-converted to n bits on the transmission side and outputs a parallel code in n-bit units. The complementary code conversion circuit 22 indicates that the bit at the specific position of the parallel code output from the n-bit parallel conversion circuit 21 indicates the presence or absence of the complementary code conversion. Therefore, the polarity of this bit causes the complementary code conversion of the bit at the predetermined position. It is determined whether or not there is a conversion operation, and an m-bit parallel code is output. The m-bit serial conversion circuit converts this parallel code into a serial code A and outputs it.

FIG. 3 is a diagram showing an example of 5B6B code conversion on the transmission side.

The 5-bit original codes a _{1 to} a ₅ to be transmitted are converted into two 6-bit codes. One is a 6-bit code in which “1” is inserted between the second bit a ₂ and the third bit a ₃ of the original code and the complementary code conversion is not performed. On the other hand, complementary code conversion is performed on the first bit a ₁ and the fourth bit a ₄ bits of the original code, and “0” is inserted between the second bit a ₂ and the third bit a _3. . These two 6-bit codes are
A bit having a different number of adjacent bits, that is, a bit having a large number of change points is selected and output as the converted output codes b _{1 to} b ₆ .

 FIG. 4 shows code conversion on the receiving side.

Of the received 6-bit codes b _{1 to} b ₆ , the third bit b ₃
Is a bit indicating the presence or absence of conversion. Therefore, the original codes a _{1 to} a ₅ are obtained by taking the exclusive OR of the first bit b ₁ and the fifth bit b ₅ with the third bit b ₃ .

The table shows the correspondence of 5B6B code conversion. In this table, the 6-bit non-conversion code and the 6-bit conversion code for the 5-bit original code and the number of change points thereof are shown, and the 6-bit code that is selectively output is indicated by a circle.

In the above embodiments, the complementary code positions are described as b ₁ and b ₅ , and the bit indicating the presence or absence of complementary code insertion is described as b ₃ , but these positions and the number of bits are the same in the present invention regardless of how they are determined. Can be carried out.

〔The invention's effect〕

As described above, the code conversion method of the present invention is based on mBnB
By performing code conversion based on logical regularity,
Since the circuit configuration is simpler than that of the code conversion circuit in the conventional method, there is an effect that high speed and low power consumption can be achieved. Further, in the present invention, since there is a bit that is not directly related to the complementary code conversion, by using this irrelevant bit position as the sync pulse position or the service signal insertion position, it is possible to determine the code without converting the code. It is possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a transmitting side code converter according to an embodiment of the present invention. FIG. 2 is a block diagram of the receiving side code converter according to the embodiment of the present invention. FIG. 3 is a diagram showing an example of 5B6B code conversion on the transmission side. FIG. 4 is a diagram showing an example of code conversion on the receiving side. 11 …… m-bit parallel conversion circuit, 12 …… No conversion circuit, 13…
Complementary code conversion circuit, 14 ... Change point comparison circuit, 15 ... Switch circuit, 21 ... n-bit parallel conversion circuit, 22 ... Complementary code conversion circuit, 23 ... m-bit serial conversion circuit.

Claims (1)

[Claims] 1. Inputting m (m is a natural number) on the transmitting side
An mBnB code conversion means for converting a bit code into an n = m + 1 bit code suitable for transmission is provided, and the receiving side is provided with a means for converting the n = m + 1 bit code into an original m-bit code. In the code conversion method, the transmitting side converts a bit at a predetermined position of the m-bit code into a complementary code, inserts a bit indicating that the complementary code conversion has been performed into a specific bit, and inserts a bit. And a second code converting means for outputting a second n-bit code by inserting a bit indicating that complementary code conversion has not been performed into the specific bit. A means for comparing the number of adjacent codes having different codes for the first n-bit code and the second n-bit code, and means for selecting and outputting the n-bit code having the larger number. And with the above reception The code conversion method is characterized in that the side is provided with means for performing code conversion by two different logics based on the value of the specific bit.