JPH088696B2 - SCH detection device - Google Patents

Description

TECHNICAL FIELD The present invention is suitable for equipment that handles composite video signals and that obtains the phase relationship (SCH) between H.SYNC and subcarrier signals and uses SCH information. There is.

2. Description of the Related Art Currently, in a broadcast VTR, the SCH of an input video signal is measured for the purpose of managing color humming. This SCH measurement method is performed in an analog circuit, and for example, a charge pump circuit is used to obtain SCH information using the phase relationship between the input video signal and the color subcarrier phase-synchronized with the burst signal of the input video signal as an analog voltage. ing. Furthermore, for convenience of displaying this SCH information on a display tube, storing it as useful information, and processing it, A / D
Digital SCH information is performed using a converter.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention By the way, as a request for equipment, downsizing of equipment,
There is no adjustment and high reliability.
It is necessary to digitize the detection circuit. In addition, it is necessary to realize a circuit configuration suitable for digitalization and also a circuit configuration suitable for a digital integrated circuit.

Particularly, in the gate array and standard cell of the digital integrated circuit in the CMOS process, the gate delay characteristic is greatly influenced by the power supply voltage, the environmental temperature and the electric load.

Means for Solving the Problems The present invention provides a sync separation means for extracting a horizontal sync signal from a composite video signal, a clock reproduction means for creating a sync clock phase-synchronized with a color subcarrier in the composite video signal, and a reference time. A pulse generating means for generating a pulse signal having a width of T, and a first for selectively outputting one of two input signals
The second selecting means, the delay means for delaying the output of the first selecting means by connecting N stages of delay units having the minimum unit delay time, and the output of each delay unit are respectively used as clock inputs, A plurality of latch means each of which uses the output of the selection means as a data input, an encoding means for encoding the outputs of the plurality of latch means, and an encoding when both the first and second selection means select the output of the pulse generation means. A first storage means for storing the output of the means, and a second storage means for storing the output of the encoding means when the output of the sync separation means and the output of the clock recovery means are respectively selected by the first storage means A SCH detection device comprising storage means and division means for dividing the output of the second storage means by the output of the first storage means to obtain SCH information. A horizontal sync signal for extracting a horizontal sync signal from the signal; a clock reproducing means for creating a sync clock phase-synchronized with the color subcarrier in the composite video signal; a delay stage number measuring means, a phase difference extracting means, and a dividing means. The delay stage number measuring means delays the pulse signal by connecting the pulse generating means for generating the pulse signal having the width of the reference time T and the first delay unit having the minimum unit delay time in N stages. A first plurality of latch means for respectively inputting outputs of the delay means and each of the first delay units as clock inputs and pulse signals for data input respectively; and a first encoding means for encoding outputs of the first plurality of latch means. The first delay unit measures the number of stages of the first delay unit, which is required to obtain the delay time of the reference time T. The phase difference extracting means clocks the output of each of the second delay units and the second delay means for delaying the output of the sync separating means by cascade-connecting the second delay units having the minimum unit delay time in N stages. It is composed of a second plurality of latch means which receives the outputs of the clock reproducing means as data inputs and a second encoding means which encodes the outputs of the second plurality of latch means. The phase relation is measured, and the dividing means is characterized by dividing the output of the phase extracting means by the output of the delay stage number measuring means to obtain SCH information.
It is a CH detection device.

Function The present invention includes delay means configured by connecting N stages of delay units having a minimum unit delay time in cascade connection, and a plurality of latch means associated with each delay unit,
As an example, the horizontal synchronizing signal in the input video signal is input to the first stage of the delay unit of the delaying means by using the encoding means for encoding the outputs of the plurality of latch means, and the color sub-synchronization synchronized with the burst signal in the input video signal is performed. The carrier wave is input as data to all the latch means, and the horizontal synchronizing signals sequentially delayed by the respective delay units are input as latch clocks to the latch means associated with the respective delay units, and the encoding means directs the delay unit from the first stage to the latter stage. Then, the output of the latch means is inspected, and the step value of the delay unit is measured at the place where a difference from the output of the previous latch means appears for the first time. In order to obtain the phase relation information and to correct the delay variation of the delay means, the delay having the minimum unit delay time As an example, a reference time is obtained by using delay means constituted by connecting units in N stages in cascade connection, a plurality of latch means associated with each delay unit, and an encode means for encoding outputs of the plurality of latch means. A pulse signal having a width of T is input to the first stage of the delay unit of the delay unit and is input to all the latch units as data, and the pulse signals sequentially delayed of each delay unit are input to the latch units associated with each. It is input as a latch clock, and the encoding unit inspects the output of the latch unit in the direction from the first stage to the latter stage of the delay unit, and measures the stage value of the delay unit at the place where the difference from the output of the previous latch unit appears for the first time. By doing so, the number of stages of the delay unit for obtaining the delay of the reference time T (delay time of the delay means Obtaining the inverse), the division means, by dividing the number of stages of delay units for obtaining the delay of the phase relation information reference time T, automatically compensate the delay variation of the delay means, always,
A SCH detection circuit having a digital circuit configuration for obtaining stable SCH information is realized.

First Embodiment A first embodiment of the present invention will be described with reference to FIG. A pulse generator 1 is used to measure the delay time of the delay line, and generates a pulse having a reference time width T based on a clock from a crystal oscillator, for example. 2 is a composite video signal input terminal, 31 and 32 are switches, 41, 42, 43, ..., 4n are non-inverter gates (delay units), 5 is a delay line (delay means) composed of delay units, 71, 72,…, 7n
Is a latch circuit, 8 is an encoder circuit, 131 and 132 are registers, 14 is a divider, 15 is a SCH information output terminal, 6 is a delay time composed of a pulse generator 1, a delay line 5, a latch circuit group 7, and an encoder 8. A measuring device 16 is a phase difference extracting circuit including a delay line 5, a latch circuit group 7 and an encoder 8,
Reference numeral 17 is a sync clock regenerator that creates twice the color subcarrier that is phase-synchronized with the burst signal of the composite video signal, and 18 is a horizontal sync detector that extracts the horizontal sync signal from the composite video signal.

The encoder circuit 8 inspects the output of the latch circuits 71 to 7n in the direction from the first stage to the rear stage of the delay units 41 to 4n, and determines the number of stages of the delay units 41 to 4n at the place where the difference between the output of the previous latch circuit and the first stage appears. Is a circuit for measuring.

Here, the operation of the delay time measuring device 6 will be described with reference to FIGS.
This will be described with reference to FIG. The switches 31 and 32 are connected to the side a at the time of measuring the delay time, and the pulse signal S0 from the pulse generator 1 having the reference time width T for measuring the delay time is supplied to the delay unit 41 of the first stage and the DATA of all the latch circuit groups 7. Supply to the input. As shown in FIG. 2A, as the number of stages of the delay unit 4 becomes deeper, the pulse signals S1, S2, S3, S4, ..., Sn of the output of the delay unit 4 become time-delayed pulses. .

In FIG. 2, T is a quadruple subcarrier signal (4F
(sc) is one clock cycle width, and the delay amount per stage of the delay unit is T / 4.

When the original pulse signal S0 is latched at the rising edge of the time-delayed pulse signal obtained by the delay units 41-4n in each latch circuit 71-7n, the pulse signal in FIG.
When latching with S1, S2, S3, S4, H level is obtained as a latch result, and when latching with pulses S5, S6, ..., Sn,
The latch result becomes L level. That is, the results of the latch circuits 71, 72, 73, 74 in FIG. 1 are at the H level, so that the results of the latch circuits 75, ..., 7n in the subsequent stage are at the L level.

Further, the result obtained by the latch circuit group 7 is supplied to the encoder circuit 8.
Parity encoder (S in the general-purpose TTL-IC shown in Fig. 4
N74LS148) consists of single or subordinate connection. In the figure, D1, D2, ..., D8 are terminals D of the encoder circuit 8 in FIG.
, D8, corresponding to D1, D2, ... In FIG. 4 in order from the output of the latch circuit 71 in the first stage. Also, A0 (LSB), A1, and A2 in FIG. 4 correspond to the output A (reference time delay stage number) of the encoder circuit 8 in FIG. 1, and are stored in the register 131 as a plurality of bits of data. When the latch result of FIG. 2 is input to the input terminals D1, D2, D3, D4, ... of FIG. 4, FUNCTION TABL also shown in FIG.
Based on E, the result of A = 4 (A2 = “H”, A1 = “L”, A0 = “L”) is stored in the register 131.

As a result, A forms a delay of the reference time width T,
This means that it is necessary to connect four delay units in cascade.

Next, the operation of the phase difference extractor 16 will be described with reference to FIGS.
This will be described with reference to the drawings. The switches 31 and 32 are connected to the side b at the time of extracting the phase difference, input the horizontal synchronizing signal S0 ′ from the horizontal synchronizing detector 18 to the delay unit 41 of the first stage, and double the color from the synchronizing clock regenerator 17. The subcarrier (2Fsc) signal is supplied to the DATA inputs of all the latch circuits 71 to 7n. As shown in FIG. 2B, as the number of stages of the delay units 41 to 4n becomes deeper, the pulse signals S1, S2, S3, S4, ... Becomes

Here, when the input horizontal synchronizing signal is at the timing shown by the solid arrow in FIG.
When the 2Fsc signal is latched at the rising edge of the time-delayed pulse signal obtained by the delay units 41 to 4n at 7n, when latched by the pulses S1, S2, S3, S4, the H level is obtained as the latch result, and the pulse When latched by S5, S6, ..., Sn, the latch result becomes L level. That is, the results of the latch circuits 71, 72, 73, 74 in FIG. 1 are at the H level, and the results of the latch circuits 75, ..., 7n in the subsequent stage are at the L level.

Further, the result obtained by the latch circuit group 7 is supplied to the encoder circuit 8, and by the same operation as the above description, based on FUNCTION TABLE shown in FIG.
The result of "H", A1 = "L", A0 = "L") is output and stored in the register 132.

The result A represents the magnitude of the phase difference between the horizontal synchronizing signals S0 'and 2Fsc (phase difference X shown in FIG. 2B).

After that, the divider 14 divides the contents of the register 132 (phase difference information) by the contents of the register 131 (reference time delay stage number). Here, the division result 1 = 4/4 is obtained, and the SCH size is obtained. Is output as 1.

Next, when the input horizontal synchronizing signal is at the timing of the broken line arrow shown in FIG. 2B, each of the latch circuits 71 to 7n
When the 2Fsc signal is latched at the rising edge of the time-delayed pulse signal obtained by the delay units 41 to 4n, when latched by the pulses S1 and S2, the H level is obtained as the latch result, and the pulses S3, S4, ... , L, the result of latching is L level. That is, the results of the latch circuits 71, 72 in FIG. 1 are at the H level, and the results of the latch circuits 73, ..., 7n in the subsequent stage are at the L level.

Further, the result obtained by the latch circuit group 7 is supplied to the encoder circuit 8, and by the same operation as described above, A = 2 (A = 2 based on FUNCTION TABLE also shown in FIG. 4).
(A2 = "L", A1 = "H", A0 = "L") is output,
Stored in register 132.

The result A represents the magnitude of the phase difference between the horizontal synchronizing signals S0 and 2Fsc (phase difference Y shown in FIG. 2B).

After this, the divider 14 divides the contents of the register 132 (phase difference information) by the contents of the register 131 (reference time delay stage number), and here the division result 0.5 = 2/4 is obtained,
0.5 is output as the size of.

In this way, SCH information according to the magnitude of the phase difference between the horizontal synchronizing signals S0 'and 2Fsc is obtained. Now, the operation when the delay amount per stage of the delay unit becomes T / 2 will be described.

The operation of the delay time measuring device 6 will be described with reference to FIG.

When the original pulse signal S0 is latched at the rising edge of the time-delayed pulse signal obtained by the delay units 41-4n in the respective latch circuits 71-7n, the pulse signals shown in FIG.
When latched by S1 and S2, H level is obtained as a latch result, and when latched by pulses S3, S4, ..., Sn, the latch result becomes L level. That is, the latch circuits 71 and 7 of FIG.
The result of 2 is H level, and the latch circuit 7 in the latter stage
The result of 3, ..., 7n becomes L level.

Further, the result obtained by the latch circuit group 7 is supplied to the encoder circuit 8, and by the same operation as described above, based on FUNCTION TABLE shown in FIG. 4, A = 2 (A2 =
The result of “L”, A1 = “H”, A0 = “L”) is stored in the register 131.

As a result, A forms a delay of the reference time width T,
This means that it is necessary to connect the delay units in two stages.

Next, the operation of the phase difference extractor 16 will be described with reference to FIG. Here, when the input horizontal synchronizing signal is at the timing shown by the solid arrow in FIG. 3B, the time-delayed pulse signals obtained by the delay units 41 to 4n in the respective latch circuits 71 to 7n are displayed. When the 2Fsc signal is latched at the rising edge, an H level is obtained as a latch result when latched by the pulses S1 and S2, and an L level is latched when latched by the pulses S3 and S4. That is, the results of the latch circuits 71 and 72 in FIG.
The result of 3,74 becomes L level.

Further, the result obtained by the latch circuit group 7 is supplied to the encoder circuit 8, and by the same operation as described above, based on FUNCTION TABLE shown in FIG. 4, A = 2 (A2 =
The result of "L", A1 = "H", A0 = "L") is output and stored in the register 132.

The result A represents the magnitude of the phase difference between the horizontal synchronizing signals S0 'and 2Fsc (phase difference X shown in FIG. 3B).

After this, the divider 14 divides the contents of the register 132 (phase difference information) by the contents of the register 131 (reference time delay stage number), and here the division result 1 = 2/2 is obtained, and the SCH size is obtained. Is output as 1.

Next, when the input horizontal synchronizing signal is at the timing of the broken line arrow shown in FIG. 3B, each of the latch circuits 71 to 7n
When the 2Fsc signal is latched at the rising edge of the pulse signal delayed by the delay unit 4 at, the H level is obtained as the latch result when latched by the pulse S1, and when latched by the pulse S2, S3, The result is L level. That is, the result of the latch circuit 71 in FIG. 1 is at the H level, and the results of the latch circuits 72 and 73 at the subsequent stages are at the L level.

Further, the result obtained by the latch circuit group 7 is supplied to the encoder circuit 8, and by the same operation as described above, based on FUNCTION TABLE shown in FIG. 4, A = 1 (A2 =
The result of “L”, A1 = “L”, A0 = “H”) is output and stored in the register 132.

The result A represents the magnitude of the phase difference between the horizontal synchronizing signals S0 and 2Fsc (phase difference Y shown in FIG. 2B).

After that, the divider 14 divides the contents of the register 132 (phase difference information) by the contents of the register 131 (reference time delay stage number), and here the division result 0.5 = 1/2 is obtained,
0.5 is output as the size of.

In this way, even if the delay amount per stage of the delay unit changes, the SCH corresponding to the magnitude of the phase difference between the horizontal synchronizing signals S0 'and 2Fsc remains the same value as that obtained in FIG. Information is obtained.

Next, the second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to the drawings. Components having the same functions as those in the first embodiment (FIG. 1) are designated by the same symbols or the same symbols with an apostrophe (').

The second embodiment is a delay time measuring device 6 and a phase difference extracting circuit.
16 configured with different hardware. Further, the data of the latch circuit groups 7 and 7'used in the delay time measuring device 6 and the phase difference extracting circuit 16 and the signal of the latch clock are arranged to have an inverse relationship to that of FIG. That is, the latch circuit
The output of each delay unit 41 to 4n and 41 'to 4n' as a data input of 71 to 7n and 71 'to 7n' is latched.
The 2Fsc signals from the pulse generator 1 and the synchronous clock regenerator 17 are input as the latch clock inputs of 71 to 7n and 71 'to 7n'. Further, the inverted output of the latch circuit group 7'is supplied to the encoder circuit 8 '.

Now, the operation of the delay time measuring device 6 will be described with reference to FIG.

When the time-delayed pulse signals obtained by the delay units 41 to 4n in the respective latch circuits 71 to 7n are latched at the falling edge of the original pulse signal S0, the pulse signals shown in FIG.
When S1, S2, S3 are latched, H level is obtained as a latch result, and when the pulses S4, ..., SN are latched, the latch result is L level. That is, the latch circuits 71, 72 of FIG.
The result of 73 is H level, and the latch circuit of the latter stage than this
The result of 74, ..., 7n is L level.

Further, the result obtained by the latch circuit group 7 is supplied to the encoder circuit 8, and by the same operation as described above, based on FUNCTION TABLE shown in FIG. 4, A = 3 (A2 =
The result of "L", A1 = "H", A0 = "H") is obtained and supplied to the divider 14.

As a result, A forms a delay of the reference time width T,
This means that it is necessary to connect the delay units in three stages.

Next, the operation of the phase difference extractor 16 will be described with reference to FIG. Here, the horizontal sync signal (H.SYN
When C) is the timing shown by the solid arrow in FIG. 6, the delay units 41 'to 4n' are connected by the latch circuits 71 'to 7n'.
By latching the 2Fsc signal obtained by delaying various times at the rising edge of the horizontal sync signal (H.SYNC), pulses S1 and S
When L2 and S3 are latched, the H level is obtained as the inversion of the latch result, and when the pulses S4 and S5 are latched, the inversion of the latch result is the L level. That is, the latch circuit of FIG.
The results of 71 ', 72' and 73 'are H level, and the latch circuit 7
The results of 4'and 75 'are L level.

Further, the result obtained by the latch circuit group 7'is supplied to the encoder circuit 8 ', and by the same operation as that described above, A = 3 (A2
The result of "L", A1 = "H", A0 = "H") is output to the divider 14.

The result A represents the magnitude of the phase difference between the horizontal synchronizing signals S0 'and 2Fsc (phase difference X shown in FIG. 6B).

Thereafter, the divider 14 outputs the output of the encoder 8 '(phase difference information) to the output of the encoder 8 (reference time delay stage number).
Is divided by, and here the division result 1 = 3/3 is obtained, and SCH
1 is output as the size of. This is the same as the result when the horizontal synchronizing signal S0 'is at the timing indicated by the solid arrow in FIG.

Next, when the input horizontal synchronizing signal (H.SYNC) is at the timing shown by the broken line arrow in FIG. 6B, the delay units 41'-4n 'in the latch circuits 71'-7n' are used. The time-delayed 2Fsc signal is applied to the horizontal sync signal (H.SYN
When latched at the rising edge of C), when the pulse S1 is latched, the H level is obtained as the inversion of the latch result, and when the pulses S4, ..., S5 are latched, the inversion of the latch result is L
It becomes a level. That is, the result of the latch circuit 71 'in FIG. 1 is H level, and the result of the latch circuits 74', ..., 75 'is L level.
It becomes a level.

Further, the result obtained by the latch circuit group 7'is supplied to the encoder circuit 8 ', and by the same operation as that described above, based on FUNCTION TABLE shown in FIG.
The result of “= L”, A1 = “L”, A0 = “H”) is output to the divider 14.

The result A represents the magnitude of the phase difference between the horizontal synchronizing signals S0 'and 2Fsc (phase difference Y shown in FIG. 6B).

Thereafter, the divider 14 outputs the output of the encoder 8 '(phase difference information) to the output of the encoder 8 (reference time delay stage number).
Is divided by, and here the division result 0.3 = 1/3, SC
0.3 is output as the size of H. This is slightly different from the result 0.5 when the horizontal synchronizing signal S0 'is at the timing indicated by the solid line arrow in FIG. 3, but the difference is negligible when the delay amount of the delay unit is small as in an actual device. Expected to approach, highly accurate
SCH detection is possible.

Furthermore, the following configuration is also conceivable as the third embodiment of the present invention (not shown).

If the delay amounts of the delay units 41 to 4n and 41 'to 4n' constituting the delay lines 5 and 5'used in the present invention are always stable even when the power supply voltage, the environmental temperature, etc. are changed, the delay unit shown in FIG. The delay time measuring device 6 is not necessary and can be omitted. Along with this, the divider 14 becomes unnecessary and the output of the encoder 8'is output to the SCH information output terminal 15 as it is. This is because the necessity of the divider 14 and the delay time measuring device 6 is to correct the delay time variation of the delay unit.

According to the present invention, the SCH detection circuit, which is a conventional analog circuit, can realize a circuit configuration suitable for digitization, and at the same time, can have a circuit configuration suitable for configuring a digital integrated circuit. The miniaturization, no adjustment, and high reliability were achieved.

Further, in the present invention, the SCH is configured by using the delay line configured by the cascade connection of the delay units having the minimum unit delay time.
Although the detection circuit was configured, a circuit that measures the delay time of the delay line is provided by itself, the delay time of the delay unit is measured every moment, and the SCH detection value is corrected based on the measured delay time -Even if the delay time of the delay unit changes due to environmental temperature fluctuations, etc., a stable SCH detection is always possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a SCH detection device according to the first embodiment of the present invention, FIGS. 2 and 3 are timing charts of the SCH detection device, and FIG. 4 is a detail of an encoder circuit used in the embodiment of the present invention. FIG. 5 is a block diagram of the SCH detecting device according to the second embodiment of the present invention, and FIG. 6 is a timing chart of the SCH detecting device. 1 ... Pulse generator (pulse generation means), 2 ... Composite video signal input terminal, 5 ... Delay line (delay means), 6 ... Delay time measuring device (delay stage number measuring means), 7 ... Latch circuit Group (latch means), 8 ... Encoder circuit (encoding means), 14 ... Divider (division means), 16 ... Phase difference extractor (phase difference extraction means), 17 ... Synchronous clock regenerator (clock regeneration) Means), 18 ... Horizontal sync detector (sync separation means), 31 ... Switch (second selection means), 32 ...
Switch (first selection means), 41-4n, 41'-4n '...
Delay unit, 131 ... Register (first storage means), 132 ... Register (second storage means).

Claims (6)

[Claims] 1. A sync separating means for extracting a horizontal sync signal from a composite video signal, a clock reproducing means for creating a sync clock phase-synchronized with a color subcarrier in the composite video signal, and a width of a reference time T. The pulse generating means for generating a pulse signal, the first and second selecting means for selectively outputting one of the two input signals, and the delay unit having the minimum unit delay time are cascade-connected in N stages to provide the first signal. Delay means for delaying the output of the selecting means, a plurality of latch means for respectively using the outputs of the respective delay units as clock inputs and the outputs of the second selecting means for data input, and a plurality of latch means of the plurality of latch means. Encoding means for encoding an output, and storing the output of the encoding means when both the first and second selecting means select the output of the pulse generating means A second storage means for storing the output of the encoding means when the output of the synchronization separation means and the output of the clock recovery means are respectively selected by the first storage means and the first and second selection means. SCH including means and division means for dividing the output of the second storage means by the output of the first storage means to obtain SCH information.
Detection device. 2. A sync separating means for extracting a horizontal sync signal from a composite video signal, a clock reproducing means for creating a sync clock phase-synchronized with a color subcarrier in the composite video signal, and having a width of a reference time T. The pulse generating means for generating a pulse signal, the first and second selecting means for selectively outputting one of the two input signals, and the delay unit having the minimum unit delay time are cascade-connected in N stages to provide the first signal. Delay means for delaying the output of the selecting means, a plurality of latch means for respectively using the outputs of the respective delay units as data inputs and the outputs of the second selecting means as clock inputs, and a plurality of latch means of the plurality of latch means. Encoding means for encoding an output, and storing the output of the encoding means when both the first and second selecting means select the output of the pulse generating means A first storage means for storing the output of the encoding means when the output of the clock reproducing means and the output of the synchronization separating means are respectively selected by the first storing means and the second storing means. SCH including means and division means for dividing the output of the second storage means by the output of the first storage means to obtain SCH information.
Detection device. 3. A sync separating means for extracting a horizontal sync signal from the composite video signal, a clock reproducing means for creating a sync clock phase-synchronized with a color subcarrier in the composite video signal, a delay stage number measuring means and a phase difference. The delay stage number measuring means includes an extracting means and a dividing means, the pulse generating means for generating a pulse signal having a width of the reference time T, and the first delay unit having a minimum unit delay time N
First delay means for delaying the pulse signal in a cascade connection, and first plurality of latch means for respectively using the outputs of the first delay units as clock inputs and the pulse signals as data inputs , The number of stages of the first delay unit which is constituted by first encoding means for encoding the outputs of the first plurality of latch means, and which the first delay means needs to obtain the delay time of the reference time T. And the phase difference extraction means sets the second delay unit having the minimum unit delay time to N
A second stage-slave connection for delaying the output of the sync separation means
Of the second delay unit, the outputs of the second delay units as clock inputs, and the outputs of the clock recovery unit as data inputs, and the second plurality of latch units. A second encoding unit that encodes an output, measures the phase relationship between the horizontal synchronizing signal and the synchronizing clock, and the dividing unit outputs the output of the phase extracting unit to the output of the delay stage number measuring unit. An SCH detection device characterized by obtaining SCH information by dividing by. 4. A sync separating means for extracting a horizontal sync signal from the composite video signal, a clock reproducing means for creating a sync clock phase-synchronized with a color subcarrier in the composite video signal, a delay stage number measuring means and a phase difference. The delay stage number measuring means includes an extracting means and a dividing means, the pulse generating means for generating a pulse signal having a width of the reference time T, and the first delay unit having a minimum unit delay time N
First delay means for delaying the pulse signal in a cascade connection, and first plurality of latch means for respectively using the outputs of the first delay units as clock inputs and the pulse signals as data inputs , The number of stages of the first delay unit which is constituted by first encoding means for encoding the outputs of the first plurality of latch means, and which the first delay means needs to obtain the delay time of the reference time T. And the phase difference extraction means sets the second delay unit having the minimum unit delay time to N
A second stage-slave connection for delaying the output of the sync separation means
Of the second delay unit, the outputs of the second delay units as data inputs, and the outputs of the clock recovery unit as clock inputs, and the second plurality of latch units. A second encoding unit that encodes an output, measures the phase relationship between the horizontal synchronizing signal and the synchronizing clock, and the dividing unit outputs the output of the phase extracting unit to the output of the delay stage number measuring unit. An SCH detection device characterized by obtaining SCH information by dividing by. 5. A sync separating means for extracting a horizontal sync signal from the composite video signal, a clock reproducing means for creating a sync clock phase-synchronized with a color subcarrier in the composite video signal, a delay stage number measuring means and a phase difference. The delay stage number measuring means includes an extracting means and a dividing means, the pulse generating means for generating a pulse signal having a width of the reference time T, and the first delay unit having a minimum unit delay time N
First delay means for delaying the pulse signal in a cascade connection, and first plurality of latch means for receiving outputs of the first delay units as data inputs and the pulse signals as clock inputs, respectively. , The number of stages of the first delay unit which is constituted by first encoding means for encoding the outputs of the first plurality of latch means, and which the first delay means needs to obtain the delay time of the reference time T. And the phase difference extraction means sets the second delay unit having the minimum unit delay time to N
A second stage-slave connection for delaying the output of the sync separation means
Of the second delay unit, the outputs of the second delay units as clock inputs, and the outputs of the clock recovery unit as data inputs, and the second plurality of latch units. A second encoding unit that encodes an output, measures the phase relationship between the horizontal synchronizing signal and the synchronizing clock, and the dividing unit outputs the output of the phase extracting unit to the output of the delay stage number measuring unit. An SCH detection device characterized by obtaining SCH information by dividing by. 6. A sync separating means for extracting a horizontal sync signal from the composite video signal, a clock reproducing means for creating a sync clock phase-synchronized with a color subcarrier in the composite video signal, a delay stage number measuring means and a phase difference. The delay stage number measuring means includes an extracting means and a dividing means, the pulse generating means for generating a pulse signal having a width of the reference time T, and the first delay unit having a minimum unit delay time N
First delay means for delaying the pulse signal in a cascade connection, and first plurality of latch means for receiving outputs of the first delay units as data inputs and the pulse signals as clock inputs, respectively. , The number of stages of the first delay unit which is constituted by first encoding means for encoding the outputs of the first plurality of latch means, and which the first delay means needs to obtain the delay time of the reference time T. And the phase difference extraction means sets the second delay unit having the minimum unit delay time to N
A second stage-slave connection for delaying the output of the sync separation means
Of the second delay unit, the outputs of the second delay units as data inputs, and the outputs of the clock recovery unit as clock inputs, and the second plurality of latch units. A second encoding unit that encodes an output, measures the phase relationship between the horizontal synchronizing signal and the synchronizing clock, and the dividing unit outputs the output of the phase extracting unit to the output of the delay stage number measuring unit. An SCH detection device characterized by obtaining SCH information by dividing by.