JPH09102870A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the configuration of a so-called composite device having functions of a copying machine and a printer or the like altogether. SOLUTION: Image data received via an image reader 401 in the copying mode are multi-value image data, and smoothing processing or edge emphasis or the like is conducted via each of processing sections 402-404. On the other hand, the image data received via a printer interface 601 are multi-value image data or binary image data. In the case of the former data, the processing sections 402-404 for the copying mode are used via a selector 602. On the other hand, in the case of the latter data, processing sections 603, 604 for binary image data are used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus having a function of a copying machine, a printer or the like, which is suitable for use in a so-called multifunction machine.

[0002]

2. Description of the Related Art A copying machine, a printer or the like which uses an electrophotographic process is provided with an image processing device for performing smoothing processing for smoothing a peripheral portion of an image and processing for enhancing an edge of the peripheral portion. . Image data to be processed by these image processing devices are roughly classified into multi-valued image data and binary image data, and an optimum smoothing method, edge enhancement method, etc. are selected according to the attributes of the supplied image data. There must be.

Therefore, the conventional printer is provided with two systems of image processing functions for multi-valued image data and binary image data, and one of them is selected. These plural image processing functions may be realized on separate hardware or may be realized on common hardware. On the other hand, in a copying machine, only multi-valued image data may be assumed as the image data input from the scanner.

[0004]

By the way, in recent years, multi-function machines having functions such as a copying machine and a printer have become widespread. When realizing a copy function and a printer function in a multifunction machine, an image processing function for binary print data,
It is necessary to have an image processing function for multi-valued print data and an image processing function for a copying function. However, in the conventional multi-function peripheral, since the latter two functions are realized by separate circuits, there is a problem that the image processing apparatus becomes large and the multi-function peripheral becomes expensive. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image processing apparatus that has a wealth of functions and can be realized at low cost.

[0005]

In order to solve the above-mentioned problems, according to the structure of claim 1, the pixel value of the pixel of interest of the image data and the pixel values of the peripheral pixels of the pixel of interest are used for the purpose. Based on a first signal generating means for outputting a first signal designating a dot type and a dot size relating to the target pixel, the pixel value of the target pixel and the pixel values of peripheral pixels around the target pixel. A second signal generating means for outputting a second signal for designating a dot type and a dot size relating to the pixel of interest, and the first or second signal according to an attribute of the image data. It is characterized by comprising an output selection means for selecting one of the two and an output control means for generating a display signal for outputting the image data based on the signal selected by the output selection means.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the output control means generates an analog signal having a level according to a designated dot size. An analog signal generating means and a pattern signal selecting means for selecting any pattern signal from a plurality of pattern signals according to a designated dot type are provided, and the selected pattern signal and the analog signal are provided. The display signal is generated based on a comparison result, and the output selection unit selects the first signal when the image data is multi-valued image data, while the image data is a binary image. In the case of data, the second signal is selected.

According to a third aspect of the present invention, in the image processing apparatus according to the second aspect, a document image reading unit that reads a document image, a print data receiving unit that receives print data, and the document image. One of the output signal of the reading means and the print data is used as the first signal.
Input selection means for supplying the print data to the second signal generation means regardless of the selection state of the input selection means. To do.

Further, in the structure according to the fourth aspect, the multivalued image data is converted based on the binarization means for converting the multivalued image data into the binary image data and the attribute of the multivalued image data. Alternatively, it is characterized by comprising an output selection means for selecting one of the binary image data and an output control means for outputting the image data selected by the output selection means.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

[Configuration of Embodiment] A. Overall Configuration of Embodiment Next, with reference to FIG. 1, an overall configuration of a multifunction peripheral according to a first embodiment of the present invention will be described. In the figure, reference numeral 401 denotes an image reading device, which reads a document and outputs the result as image data. This image data is multi-valued image data of “256” gradation represented by values of “0” to “255”. A printer interface 601 receives print data supplied from a host computer (not shown).

This print data is multi-valued image data or binary image data of "256" gradation. If the print data is binary image data, the pixel value is "0".
Alternatively, it is expressed by “255”. A selector 602 selects one of the image data output from the image reading device 401 or the printer interface 601 based on the input select signal INSEL. The input select signal INSEL becomes “0” when the image reading device 401 should be selected, and becomes “1” when the printer interface 601 should be selected.
An input gradation correction unit 402 corrects the gradation of the selected image data.

Reference numeral 409 denotes a CPU, which outputs a type detection signal STYPE for designating an image type based on area data designated by an input device such as a digitizer.
Reference numeral 403 denotes an edge correction processing unit, which is an input gradation correction unit 40.
Processing such as edge enhancement is applied to the image data corrected in 2, and the result is output as image data CD0.
Further, the edge correction processing unit 403 determines that the waveform control signal ATB
1 (details will be described later) is output. Reference numeral 404 is an output gradation correction unit that corrects the output gradation of the image data CD0.
The result is output as image data CD1.

Next, reference numeral 603 is a binary edge determination unit,
It is determined whether or not the pixel of interest of the print data forms an edge of the binary image data, and the result is output as a binary edge determination signal EGH. This binary edge determination signal EG
H is "1" when the edge of the binary image data is detected,
It is a signal which becomes "0" in other cases. Also, 60
A binary smoothing processing unit 4 performs smoothing processing assuming that the print data is binary image data. Then, the binary smoothing processing unit 604
Smoothed (multi-valued) image data C
D2 and the waveform control signal ATB2 are output.

A decoder circuit 605 outputs the logical sum of the input select signal INSEL and the binary edge determination signal EGH as the output select signal OUTSEL. That is, the output select signal OUTSEL is “1” when the printer interface 601 is selected by the input select signal INSEL and the binary edge determination unit 603 detects the edge of the binary image data.
Otherwise, it becomes "0".

Next, 606 and 607 are selectors,
When the output select signal OUTSEL is "0", the image data CD1 and the waveform control signal ATB1 are selected,
If it is "1", the image data CD2, the waveform control signal A
TB2 is selected, and the selected signals are output as image data CD,
The waveform control signal ATB is output. Reference numeral 405 denotes a waveform control screen generation unit, which performs pulse width modulation on the image data CD by comparing the screen signal (triangular wave) with the image data CD.

An image output device 406 controls the blinking state of the laser diode by the pulse width modulation signal output from the waveform control screen generator 405, and outputs an image on paper by a well-known electrophotographic process. That is, dots having a size corresponding to the image data CD are output. A control device 408 controls each of the above-described components. An operation / display panel 407 is appropriately operated by the user to set an operation mode and the like of the multifunction peripheral.

Among the above-mentioned components, those having a code number of "600" or more are optional. That is,
The component for outputting the print data will be provided only to the user who needs it. When the option is not attached, the image data output from the image reading device 401 is directly supplied to the input gradation correction unit 402. Similarly, the image data CD1 as the image data CD and the waveform control signal ATB1 as the signal ATB are directly supplied to the waveform control screen generation unit 405. Hereinafter, the detailed configuration of the main part of the above-described configuration will be described.

A. Waveform Control Screen Generation Unit 405 Next, the configuration of the waveform control screen generation unit 405 will be described with reference to FIG. In the figure, 160 is a D / A conversion circuit, which converts the image data CD into an analog signal and outputs it. Further, 161 is a pattern generation unit, which has a dp of 200 dp.
The pattern signal S which is a triangular wave having a cycle corresponding to i
Output _A. Further, 162 is another pattern generator, which outputs a pattern signal S _B which is a triangular wave having a “180 °” phase difference with respect to the pattern signal S _A. Also, 1
Reference numeral 63 is also a pattern generator, which outputs a pattern signal S _C which is a triangular wave having a cycle corresponding to 400 dips.

Reference numeral 164 denotes a selector, which selects one of the pattern signals S _A , S _B and S _C as the waveform control signal ATB.
Select based on Reference numeral 165 denotes a comparator, which compares the image data CD converted into an analog signal with the selected pattern signal, and is "1" when the former level is equal to or higher than the latter level, and "0" otherwise. The pulse width modulation signal that becomes "" is output.

Here, "3" types of pattern signals S _A ,
The technique of switching between S _B and S _C is conventionally known, and the reason will be briefly described with reference to FIG. First, the image data CD is shown in FIG.
When the pulse width modulation signal is generated using only the pattern signal S _{A in the} case of the multi-valued image data as shown in FIG. 5, the image is cut off as shown in FIG. There will be problems.

Therefore, as shown in FIG. 3C, by selecting one of the pattern signals S _A and S _B so that the image is not traced, "two-line blur" can be prevented. In this way, as the 200 dpi signal, "18
Two lines of signals with different 0 ° phase should be used.
An example of the case where the pulse width modulation signal is generated by using only the pattern signal S _{C of} 400 dip is shown in FIG.

In this figure, the image appears to be cut off at the edges at both ends, but in reality, the narrow blank area is filled in due to the reproduction characteristics of the electrophotographic process, and no cutout occurs in the output image. Furthermore, the resolution of the output image can be increased by using the pattern signal S _{C of} 400 dip. However, if only the pattern signal S _C is used, the problem that the reproducibility of the gradation is deteriorated occurs.
Therefore, depending on the state of the image, etc., 200 dpi and 4
Select a suitable pattern signal from 00 dip,
This should change the type of dots to be output. The above is the pattern signals S _A , S _B , S _{C of} “3” types.
This is the reason for switching and using.

When a 200 dpi pattern signal is to be used, the waveform control signal ATB does not directly instruct the distinction between the pattern signals S _A and S _B , but the "right edge", "left edge" or "no edge". Command. "
Therefore, the selector 164 selects one of the pattern signals S _A and S _B based on the instructed edge direction (or presence / absence of an edge) and the phase of the pattern signals S _A and S _B at that time. become.

By the way, the pattern generators 161, 162
As a specific configuration, a configuration in which the pattern generation units 161 and 162 are realized by independent pulse oscillators and both are phase-locked to maintain a phase difference of “180 °” can be considered. However, in such a configuration, two pulse oscillators and PL
The L circuit is required, and the device is expensive. Therefore, a configuration is generally adopted in which only one is configured as an independent pulse oscillator and the other is realized as a subtractor that subtracts the pulse voltage from a DC voltage.

Here, if the pattern generator 161 is an independent pulse oscillator and the pattern signal S _A has an ideal waveform, as a result, the pattern signal S _B also has an ideal waveform. become. However, a pulse oscillator that generates a sufficiently accurate triangular wave is expensive, and it is technically possible to use such a pulse oscillator, but it is not feasible.

That is, since the pattern generator 161 is realized by a circuit as simple as possible, the pattern signal S
_A will have distortion when compared to an ideal triangular wave. Further, the distortion in the direction opposite to the distortion is the pattern signal S _B.
Will also occur. As a result, even if the level of the image data CD is constant, a density difference occurs depending on which of the pattern signals S _A and S _B is used. This also applies to the pattern signal S _C.
Here, FIG. 11A shows an example of screen characteristics which differ depending on the pattern signals S _A , S _B and S _C.

A. Output gradation correction unit 404 Next, the output gradation correction unit 404 will be described. The output gradation correction unit 404 is provided in the preceding stage of the waveform control screen generation unit 405, and compensates for the above-mentioned difference in screen characteristics. That is, the output gradation correction unit 404 is provided with tables corresponding to the pattern signals S _A , S _B , and S _C , respectively, and almost the same output image density Dout is obtained for the same density of the image data CD0. Thus, the density of the image data CD1 is set. An example of the characteristics of this table is shown in FIG.

By the way, in the present embodiment, various parameters are changed according to the type of the input image (character, photograph, character + photograph, or map). Therefore, the output gradation correction unit 404 is provided with “12” types of tables corresponding to “4” types of input images and “3” types of pattern signals. Then, the gradation correction control signal MTSE
A table to be used is selected based on L.

A. Binary Edge Determination Unit 603 Next, the configuration of the binary edge determination unit 603 will be described with reference to FIG. In the figure, reference numerals 280 and 281 denote FIFO buffers, which delay the print data by one line in the main scanning direction and output it. Therefore, the print data for “3” lines is obtained by the input data and output data of the FIFO buffer 280 and the output data of the FIFO buffer 281.

282 is a 3 × 3 matrix circuit,
It is configured by arranging "9" flip-flops of "8" bits in 3 rows and 3 columns (coordinate values: (0,0) to (2,2)).
Next, 284 is a “255” judgment / counter, which is 3 ×
“255” among the pixel values in the 3 matrix circuit 282
If there is one having the value of, the coordinate value is output. Also, 285 is a “0” judgment / counter, which is 3 ×
If there is a pixel value of "0" among the pixel values in the 3-matrix circuit 282, the coordinate value is output.

Next, 286 is a logic circuit,
Based on the coordinate values output from the “5” determination / counter 284 and the “0” determination / counter 285, it is determined whether or not there is a binary edge in the 3 × 3 matrix, and the binary edge representing the result. The determination signal EGH is output. That is, the logic circuit 286 determines whether or not there are two pixels adjacent to each other in the main scanning direction or the sub-scanning direction and having the pixel values of "255" and "0", and if they are present, "1".
If there is not, it is set to “0”, and the binary edge determination signal E
Set GH.

Next, reference numeral 283 is a comparator, and the pixel of interest (pixel of coordinate value (1,1) in the 3 × 3 matrix) is "25.
It is determined whether or not it is equal to "5", and when it is equal to "1",
When they are not equal, the binary edge signal PD0 which becomes "0" is output. By the way, as described above, the image data supplied from the printer interface 601 to the binary edge determination unit 603 is the multivalued image data of “256” gradation or the pixel value of “0” or “255”. It is the binary image data that it has.

When the former multi-valued image data is supplied to the binary edge determination unit 603, the binary edge signal PD0 becomes a signal having no meaning. On the other hand, when the latter binary image data is supplied, the binary edge signal PD0 indicates that the binary image data has a general format (binary image data in which a pixel value is represented by "0" or "1"). ) Will be converted to.

A. Binary Smoothing Processing Unit 604 Next, the configuration of the binary smoothing processing unit 604 is shown in FIG.
This will be described with reference to FIG. In the figure, reference numeral 290 is a FIFO buffer, which delays and outputs the binary edge signal PD0 over "8" times by one line in the main scanning direction. Therefore, the undelayed binary edge signal PD0 itself,
Based on each output signal of the FIFO buffer 290, the binary edge signal PD0 for "9" lines is obtained.

Numeral 291 is a windowing circuit, in which "81" flip-flops of "1" bit are arranged in 9 rows and 9 columns.
9 matrices (coordinate values: (0,0) to (8,8)) are formed. Reference numeral 292 is a logic circuit, which multi-values the pixel value of interest (coordinate values: (4,4) to (8,8)) based on the output signal (each value of the 9 × 9 matrix) of the windowing circuit 291. The multivalued image data CD2 and the waveform control signal ATB2 are output.

Here, the binary smoothing processing unit 604.
FIG. 15 shows an example of the smoothing process by the. Same figure
(a) is the binary edge signal PD0 input to the binary smoothing processing unit 604, and FIG.
D2 is shown. The image data CD2 is obtained by converting the binary edge signal PD0 into a multi-valued image so that the edge portion has an intermediate density. Further, FIG. 7C shows a pulse width modulation signal generated by the waveform control screen generation unit 405 based on the image data CD2 and the waveform control signal ATB2.

In FIG. 7C, the lighting timing of the laser diode in the intermediate density portion is set to the right or the center of each pixel area. The former is because "200 dpi right justification" is commanded by the waveform control signal ATB2, and the latter is because "400 dip" is commanded. Such image data C
As a specific method of outputting D2 and the waveform control signal ATB2, for example, the technique disclosed in Japanese Patent Application Laid-Open No. 4-186486, Japanese Patent Application Laid-Open No. 5-6438, or Japanese Patent Application Laid-Open No. 5-46002 may be used. .

B. Edge Correction Processing Unit 403 Next, the outline of the edge correction processing unit 403 will be described with reference to FIG. In the figure, reference numeral 410 denotes a matrix circuit, which generates a 5 × 5 matrix centered on the target pixel based on the image data input through the selector 602. 420 is a spatial digital filter circuit,
By the linear filtering process for 5 matrices,
The edge is emphasized.

Reference numeral 430 is an edge detection filter circuit,
Efficient addition and subtraction is performed on each value of the 5 × 5 matrix to generate data to be supplied to the circuit in the subsequent stage. 450,
Reference numerals 460 and 500 denote an edge strength determination circuit, an edge direction detection circuit, and an edge direction determination logic circuit,
The waveform control signal ATB1 is generated. Reference numeral 510 is a TRC tag generation look-up table, which is based on the waveform control signal ATB1 and the like and is used for gradation correction control signal MTSE.
L is output.

Reference numeral 480 is a non-linear filter circuit, which performs sharper edge enhancement on the image data output from the spatial digital filter circuit 420. The edge enhancement in the non-linear filter circuit 480 is performed by the filter switching signal FCX output from the edge strength determination circuit 450.
Is controlled by ON / OFF. Hereinafter, each unit of the edge correction processing unit 403 will be described in detail.

B-1. Matrix Circuit 410 and the Like Next, the configuration of the matrix circuit 410 and the like will be described with reference to FIG. In the figure, the matrix circuit 410 is configured by arranging flip-flops of “8” bits in a 5 × 5 matrix. These flip-flops are represented in alphabetical order by the symbols A to Y from right to left in the figure and from top to bottom. Also, the output signals of these flip-flops ("8" bits x "25" lines)
Is called a matrix signal MTX.

The flip-flops E, J, O, T, and Y in the leftmost column on the 5 × 5 matrix are adjacent to each other in the image data in the sub-scanning direction in synchronization with a predetermined clock signal “5”.
The pixel density signals CDI0 to CDI4 are supplied. These density signals represent the density of each pixel by "256" gradation ("8" bits). The supplied concentration signal is latched in flip-flops E, J, O, T and Y. The contents latched in each flip-flop before that are shifted to the right in the figure. Here, the pixel related to the flip-flop M is a target pixel to be processed such as edge enhancement.

Reference numeral 10 denotes a CPU bus controller, which writes necessary data in various registers described later based on a control signal supplied from the control device 408.
A timing controller 11 outputs various control signals based on the supplied clock signal and the like.

B-2. Edge Detection Filter 430 Next, the configuration of the edge detection filter circuit 430 will be described with reference to FIG. In the figure, 21 to 28 and 33 to 44 are adders, and 29 to 32 and 45 to 48 are subtractors. The adder 21 adds the output signals of the flip-flops G, H and I, the adder 22 adds the output signals of the flip-flops Q, R and S, and the subtracter 29 adds the latter addition result to the latter addition result x1. The result x2 is subtracted and the subtraction result e5 is output.

Here, the significance of such calculation will be described. First, assume a 3 × 3 matrix centered on a pixel of interest inside a 5 × 5 matrix. The above calculation is 3 ×
The difference in intensity between the first row (top row) and the third row (bottom row) of the three matrices is obtained. This is an index for determining whether the pixel of interest tends to form the upper edge or the lower edge.

Similarly, the adder 23 adds the output signals of the flip-flops G, L, and Q, the adder 24 adds the output signals of the flip-flops I, N, and S, and the subtractor 30 adds the former addition. The latter addition result y2 is subtracted from the result y1 and the subtraction result e6 is output. The subtraction result e6 serves as an index for determining whether the target pixel tends to form the left edge or the right edge.

Next, the adders 25 to 28 and 33 to 44 are
The addition result of the output signals for each row and column of the 5 × 5 matrix is output. Here, the addition result of the first row to the fifth row is c
1 to c5, 1st to 5th columns (column numbers are counted from the right side in the matrix circuit 410 of FIG. 1), addition results of r1 to
r5. The adders 33 to 38 correspond to odd-numbered rows and odd-numbered columns, and the output signals of the “5” flip-flops belonging to the corresponding rows or columns are added as they are to obtain each addition result.

On the other hand, adders 25 to 28 correspond to even rows and even columns. For these adders, first add 3 × 3
Addition results x1, x2, y obtained for the matrix
The addition result is obtained by diverting 1, y2. For example, in the adder 25, the output signals of the flip-flops F and J are further summed with respect to the addition result x1 (the sum of the output signals of the flip-flops G, H, and I), and the result of the second row is added. The addition result c2 is obtained.

This is one of the features of this embodiment. That is, in the present embodiment, the addition result in the 5 × 5 matrix can be obtained by diverting the addition result in the 3 × 3 matrix. As a result, the latter calculation processing amount can be reduced, and the calculation can be performed at high speed using a simple circuit.

Next, the adder 41 adds the addition results c1 and c2 and outputs the addition result c7. That is, the addition result c7 is the sum of the pixel densities of all the pixels located above the row (third row) to which the pixel of interest belongs in the 5 × 5 matrix. Similarly, the adder 42 adds the addition results c4 and c5 and outputs the addition result c8. That is, the addition result c8
Is the sum of the pixel densities of all the pixels located below the row (third row) to which the pixel of interest belongs. Next, the subtractor 47 outputs the difference between both addition results c7 and c8.

Here, the subtraction result of the subtractor 47 is 5 × 5.
The amount is proportional to the average value of the density gradient in the column direction of the matrix, that is, the sub-scanning direction. Therefore, this subtraction result is referred to as "first-order differential value e3 in the sub-scanning direction". In addition, the adder 43,
44 and the subtractor 48, the addition result r of each column
The same calculation as that described above is performed on 1, r2, r4, and r5, and the subtraction result of the subtractor 48 becomes an amount proportional to the average value of the density gradient in the row direction, that is, the main scanning direction. Therefore, this subtraction result is referred to as "first-order differential value e4 in the main scanning direction".

Next, the adder 39 outputs the addition results c1 and c5.
The respective values of "1/2" are added and the addition result c6 is output. Then, the subtractor 45 subtracts the addition result c6 from the addition result c3 of the third row and outputs the result. In other words, the subtractor 45 weights “−1/2”, “1”, and “−1/2” to the addition results c1, c3, and c5, respectively, and then adds them. Is output. Since "1/2" of various values can be obtained by simply ignoring the least significant bit of the value, it is not necessary to provide a division circuit, a shift circuit, or the like.

Now, the subtraction result in the subtractor 45 becomes "0" when the density gradient in the sub-scanning direction is constant,
If the concentration gradient changes, the value will depend on the amount of change. That is, the value output from the subtractor 45 is 5 ×
5 is a value proportional to the gradient of the density gradient in the sub-scanning direction within the matrix. Therefore, this value is called "second-order differential value e1 in the sub-scanning direction". Further, in the adder 40 and the subtractor 46, the same calculation is performed on the addition results r1, r3, r5 of each column, and the subtractor 46 produces a value proportional to the gradient of the density gradient in the main scanning direction. Become. Therefore, this value is called "second-order differential value e2 in the main scanning direction".

Next, the subtractor 31 determines the flip-flops A and Y from the pixel value of interest (the output signal of the flip-flop M).
"1/2" of each output signal of is subtracted. This value is a value corresponding to the second-order differential value of the density along a diagonal line rising to the right (a line passing through the flip-flops A and Y) passing through the pixel of interest. Therefore, this value is referred to as "second-order differential value DI1 in tilt direction". Similarly, the subtractor 32 subtracts "1/2" of each output signal of the flip-flops E and U from the target pixel value.
Therefore, the result of this subtraction is "the second-order differential value DI2 in the tilt direction".
Call.

B-3. Edge Strength Determining Circuit 450 and Edge Direction Detection Circuit 460 In FIG. 5, reference numerals 60 to 67 are absolute value circuits, which output the absolute values of the above-mentioned calculation results e1 to e6, DI1 and DI2. Further, the absolute value circuit 65 outputs the sign of the subtraction result e6 as the sign signal e6s. Reference numeral 70 denotes a comparator, which is the absolute value of the second-order differential value e1 in the sub-scanning direction and the second-order differential value e1 in the main scanning direction.
The magnitude relationship with the absolute value of the differential value e2 is compared. Reference numeral 71 denotes a selector, which outputs the larger value (hereinafter, referred to as value max (| e1 |, | e2 |)) based on the comparison result.

Next, reference numeral 80 denotes a threshold value register, which stores "4" types of threshold value ETH1 corresponding to the type of the original image (character, photograph, character + photograph, and map). Then, based on the type command signal STYPE '(details will be described later), any one of these "4" types of threshold value ETH1 is selected and output. 100 is a comparator, and the value max
The comparison result FC1 which is "1" when (| e1 |, | e2 |) is equal to or greater than the threshold value ETH1 and which is "0" otherwise.
Is output.

Reference numeral 81 is a threshold value register, which is "4".
The threshold value ETH2 of the type is stored. The selector 91 and the comparator 101 are the selector 90 and the comparator 100.
Is configured similarly to. Therefore, the comparator 101 outputs “1” when the value max (| e1 |, | e2 |) is equal to or greater than the threshold value ETH2, and otherwise outputs “0” as the comparison result W.
Output C1.

Further, the comparator 72, the selector 73, the threshold registers 82 and 83, the selectors 92 and 93, and the comparator 1
The part consisting of 02 and 103 has the same structure as the above-mentioned part. Therefore, the comparator 102 has the sub-scanning direction 1
Absolute value of the differential value e3 and the primary differential value e4 in the main scanning direction
The larger of the absolute values of (the value max (| e3
, | E4 |)) is greater than or equal to the threshold value ETH3, the comparison result FC2 that is "1" is output. Similarly, the comparator 103 determines that the value max (| e3 |, | e4 |) is the threshold value ETH.
When it is 4 or more, the comparison result WC2 which becomes "1" is output.

Further, the portion composed of the comparator 74, the selector 75, the threshold value register 84, the selector 94 and the comparator 104 is also similarly constructed. Therefore, the comparator 102
Is the larger of the absolute value of the subtraction result e5 and the absolute value of the subtraction result e6 (hereinafter, the value max (| e5 |, | e6
The comparison result WC3 that becomes "1" is output when the value of () is greater than or equal to the threshold value ETH5.

Further, the portion composed of the comparator 77, the selector 78, the threshold value register 86, the selector 96 and the comparator 107 is similarly configured. Therefore, the comparator 107
Is the larger of the absolute value of the tilt direction second-order differential value DI1 and the absolute value of the tilt direction second-order differential value DI2 (hereinafter,
The value max (called | DI1 |, | DI2 |) is the threshold ETH
When it is 7 or more, the comparison result FWC1 which becomes "1" is output.

Next, 76 is an adder for subtracting the result e
The average value of the absolute values of 5 and e6 (average value e7) is output.
Further, 95 is a selector, which is a type command signal STYP
The threshold value ETH6 is selected and output based on E '. The subtractor 108 subtracts the threshold value ETH6 from the average value e7,
It is output as the threshold value e8. Reference numerals 105 and 106 are comparators, which compare the absolute values of the subtraction results e5 and e6 with the threshold value e8, and become "1" when the corresponding subtraction result is greater than or equal to the threshold value e8, and "1" otherwise. The comparison results MI2 and MI3 which are 0 "are output.

Here, the significance of the comparison results MI2 and MI3 will be described. First, as described above, the subtraction result e5 is an index for determining whether the target pixel in the 3 × 3 matrix tends to form the upper edge or the lower edge. Therefore, the absolute value indicates the strength of the tendency that the target pixel forms an edge (upper and lower edges) in the main scanning direction. Similarly, the subtraction result e6 indicates the strength of the tendency that the target pixel forms an edge (left and right edge) in the sub-scanning direction.

Therefore, the edge direction can be discriminated by the values of the comparison results MI2 and MI3. That is, when the comparison results MI2 and MI3 are "1" and "0", the target pixel has a strong tendency to form an edge in the main scanning direction, and when the comparison results MI2 and MI3 are "0" and "1", the edge in the sub-scanning direction. Will tend to be strong. Further, when these values are "0", "0" or "1", "1", the tendency that the pixel of interest constitutes an edge in the main scanning direction and the sub scanning direction is similar. The subtraction results e5, e
When the absolute values of 6 are close to each other (the difference between them is ± | ETH
6 | or less), the comparison results MI2 and MI3 become "0", "0" or "1", "1". Which of these is used is based on the sign (+ or −) of the threshold value ETH6.

B-4. Edge direction determination logic circuit 50
0 and TRC tag generation lookup table 510 In FIG. 6, 120 is an OR circuit, and the comparison result FC
The logical sum of 1, FC2 and FWC1 is calculated, and the result is output as the filter switching signal FCX. The use of the filter switching signal FCX will be described later. 142 is O
The R circuit calculates the logical sum of the comparison results WC1 to WC3 and FWC1 and outputs the result as an edge presence / absence determination signal MI1.

Reference numerals 144 and 145 are registers, which store four kinds of values which can be candidates for the waveform control signal ATB1. Then, the edge decision logic multiplexer 14
3 is an edge presence / absence determination signal MI1, comparison results MI2, M
When I3 and the sign signal e6s are supplied, one of the values stored in the registers 144 and 145 is selected and output based on the table below.

[0065]

[Table 1]

In Table 1, the edge presence / absence determination signal MI1
Is "0" (when no edge is detected)
, The waveform control signal ATB1 is set to "00" so that a single triangular wave of 200 dpi is selected regardless of other signals. Further, the edge presence / absence determination signal MI1 is "1".
And the comparison result MI3 is “0” (when the tendency to form an edge in the sub-scanning direction is weak), 400 di
In order to select the triangular wave of p, the waveform control signal ATB1 is set to "1".
1 "is set.

In other cases, the waveform control signal ATB1 is set to "01" or "10" so that the right or left alignment is performed. The waveform control signal ATB1 is delayed by the delay circuit 146 for timing adjustment.
Is delayed by a predetermined time (time designated by the register 147) via the waveform control screen generation unit 405.
Supplied to

Next, 121 to 136 are registers,
The "16" types of data that are candidates for the gradation correction control signal MTSEL are stored. 137 is an output gradation correction logic
A multiplexer, which is the data of "2" bits supplied through the selector 140 and the waveform control signal ATB.
Data of a total of "4" bits including 1 ("2" bits) is used as a selection signal, and any one of the above "16" types of data is selected, and the selected data is the gradation correction control signal M.
Output as TSEL.

This gradation correction control signal MTSEL is delayed by a predetermined time (time designated by the register 139) via the delay circuit 138, and the output gradation correction unit 404.
Supplied to The selector 140 described above is supplied with the type command signal STYPE ′ and another signal (STRC), and based on the contents of the tag control register 141,
One of them is supplied to the output gradation correction logic multiplexer 137. In a normal use state, the contents of the tag control register 141 are set so that the type command signal STYPE 'is selected.

B-5. Spatial Digital Filter Circuit 420 Next, the configuration of the spatial digital filter circuit 420 will be described with reference to FIG. In the figure, reference numeral 265 denotes a type command register, which is a type (character,
"2" bit data representing a photograph, a character + a photograph, or a map) is written. This data is supplied to one end of the selector 266. Also, at the other end of the selector 266,
"2" bit type detection signal STYP from CPU 409
E is supplied.

The selector 266 selects one of the content of the type command register 265 or the type detection signal STYPE based on the data stored in the register 267, and outputs the selected signal as the type command signal STYPE '. Next, reference numerals 260 to 264 are addition circuits. The adder circuit 260 adds the output signals of the flip-flops A, E, U, and Y in the matrix signal MTX, and adds the result S1.
Is output.

Similarly, the adder circuit 261 adds the output signals of the flip-flops B, D, F, J, P, T, V, and X and outputs the addition result S2. The adder circuit 262 outputs the flip-flops C and K. , O, W output signals are added to add result S
3 and the adder circuit 263 outputs the flip-flop G,
The output signals of I, Q and S are added and the addition result S3 is output, and the adder circuit 264 outputs the flip-flops H, L, N and R.
Output signals are added and the addition result S5 is output.

Reference numerals 170 to 175 denote registers, which have a coefficient g.
Memorize 1 to g6. These coefficients g1 to g6 are stored for each "4" type corresponding to the document type. 180 ~
A selector 185 selects and outputs the coefficients g1 to g6 corresponding to the type command signal STYPE '. 19
Reference numerals 0 to 195 denote multiplication circuits, which multiply the addition results S1 to S5 and the target pixel value dM by the selected coefficients g1 to g6, respectively, and output multiplication results S1 'to S5'.

Next, 200 to 205 are registers,
The shift amounts SG1 to SG6 are stored respectively. These shift amounts SG1 to SG6 are also stored for each “4” type corresponding to the image type. Reference numerals 210 to 215 denote selectors, which are shift amounts SG1 to S corresponding to the type command signal STYPE '.
G6 is selected and output. Reference numerals 220 to 225 denote shift circuits, which shift the multiplication results S1 'to S5' by the number of digits designated by the shift amounts SG1 to SG6, respectively.
It is output as 1 "to S5".

Reference numeral 226 denotes an adder circuit, which is the multiplication result S1 ″.
.About.S5 "are added and the result is output as a corrected target pixel value dM '. That is, the corrected target pixel value dM' is shown in Table 2 below for each value of the 5.times.5 matrix forming the matrix signal MTX. It is the result of multiplying and summing products.

[0076]

[Table 2]

In Table 2, H1 to H6 are weighting coefficients. In the present embodiment, signals multiplied by the same weighting coefficient in the matrix signal MTX are added in advance by the adder circuits 260 to 264. As a result, the number of multiplications is reduced, and it is possible to reduce the size of the circuit and speed up the operation. By the way, the weighting coefficient Hn
(However, n = 1, 2, ..., 6) is equal to “gn × 2 ^SGn ”. In other words, in the present embodiment, the operation of multiplying the addition results S1 to S5 by the weighting factors H1 to H6 is a two-step operation including the multiplication in the multiplication circuits 190 to 195 and the shift operation in the shift circuits 220 to 225. It will be executed separately.

As a result, in this embodiment, the number of digits of the multiplicands in the multiplication circuits 190 to 195 can be made uniform, and the multiplication circuits 190 to 195 can be realized as a fixed-point type multiplier. Since the fixed-point type multiplier can be made faster than the floating-point type multiplier, in the present embodiment, it is possible to calculate the modified pixel value of interest dM ′ at a higher speed.

Here, the weighting factors H1 to H6 are set so as to emphasize the edge of the target pixel value dM. For example, when the target pixel value dM changes in a mountain shape with respect to the coordinate value x in the main scanning direction as shown by the characteristic A1 in FIG.
The corrected target pixel value dM ′ is high in the vicinity of the mountain-shaped top portion and is low in the skirt portion, as indicated by the characteristic A2 in FIG.

Here, the spatial digital filter circuit 420
An example of the filtering characteristics of is described briefly. First, the spatial digital filter circuit 420 is set so that the gain becomes “0 dB” when the spatial frequency is “0” so as not to change the macroscopic image density. Then, a region where the spatial frequency is slightly higher (for example, 100
At about (dpi), the gain exceeds “0 dB” because edge enhancement is performed. However, at a higher spatial frequency (for example, 200 dpi or more), the gain becomes a value less than “0 dB” to prevent moire. That is, the spatial digital filter circuit 420 has band emphasis type filter characteristics.

B-6. Non-Linear Filter Circuit 480 Next, the configuration of the non-linear filter circuit 480 will be described with reference to FIG. In the figure, reference numerals 240 to 243 are flip-flops, which have a target pixel value dM and a modified target pixel value dM ′.
In order to match the timing of, the target pixel value dM is delayed and output. A subtraction circuit 244 subtracts the delayed target pixel value dM from the corrected target pixel value dM ′ and outputs the subtraction result “dM′−dM”. The result of this subtraction is as shown by the characteristic A3 in the example of FIG.

Considering this subtraction result "dM'-dM" as the second filtering result for the target pixel value dM, the frequency characteristic thereof will be examined. As described above, the corrected target pixel value dM ′ when the spatial frequency is “0” is equal to the target pixel value dM, and in such a case, the subtraction result “dM ′”
-DM "becomes" 0 ". That is, the gain is "-∞"
become.

Further, at a high spatial frequency (area attenuated to prevent moire), the subtraction result "dM'-
Since "dM" is less than "0", the gain is also "-".
∞ ”. Then, the gain becomes a finite value in the intermediate portion between them (the area where the edge enhancement is performed). In other words, the subtraction result "dM'-dM" is obtained by extracting the frequency component of the intermediate portion of the target pixel value dM.

As described above, the spatial digital filter circuit 4
20 and the subtraction circuit 244 are combined to realize the characteristics of the bandpass filter. Next, reference numeral 245 is a register which stores "4" types of constants em_p corresponding to the image types. A selector 246 is a type command signal ST
Based on YPE ', a corresponding constant em_p is selected and output.

Reference numeral 247 is a multiplier, and the subtraction result "d
M′−dM ”is multiplied by the selected constant em_p, and the multiplication result is output as the correction amount dMX. That is, the correction amount dMX is, for example, as shown by the characteristic A4 in FIG. Next, 248 and 249 are registers, which store predetermined threshold values th_p and th_m, respectively. Reference numeral 250 denotes a comparator, which is the subtraction result "dM'-dM".
Is equal to or greater than the threshold th_p, a "1" signal is output, and in other cases, a "0" signal is output.

On the other hand, the comparator 251 outputs the subtraction result "dM '.
"-DM" is equal to or less than the threshold value th_m, a "1" signal,
In other cases, the "0" signal is output. Reference numeral 252 denotes a selector which, when supplied with the sign bit of the subtraction result “dM′−dM”, selects and outputs one of the output signals of the comparators 250 and 251 in response thereto. That is, the selector 252 selects the output signal of the comparator 250 when the subtraction result “dM′−dM” is “0” or more, and selects the output signal of the comparator 251 when it is less than “0”.

Reference numeral 254 denotes a selector, which is a control device 408.
Control signal MMS. Based on CNT, one of the target pixel value dM and the modified target pixel value dM ′ is selected and output. A selector 253 is a selector 2
When the output signal of 52 is "1", the correction amount dMX,
If it is "0", the value "0" is selected and output. 25
An adder 5 adds the signals selected by the selectors 253 and 254 and outputs the addition result dM1.

Next, the operation of the parts from the subtraction circuit 244 to the adder 255 will be described with reference to FIGS. In the selector 254, the corrected target pixel value d
It is assumed that M'is selected. In the section (a) of the figure, since the subtraction result “dM′−dM” is less than “0” in the section where the coordinate value x is less than the coordinate value x ₁₁ , the selector 252 outputs the output of the comparator 251. The signal is selected. Here, the subtraction result “dM′−dM” is the threshold value th_m.
Since it is not the following, the comparator 2
The “0” signal is supplied from 51 to the selector 253.

Therefore, the selector 253 has "0".
Is selected and supplied to one input terminal of the adder 255. On the other hand, the corrected target pixel value dM ′ is supplied to the other input end via the selector 254. Therefore, the addition result dM1 becomes equal to the corrected target pixel value dM '. Next, the coordinate value x is x ₁₁
In the section of up to x ₁₂ , the subtraction result “dM′−dM” becomes less than or equal to the threshold value th_m, so the “1” signal is supplied from the comparator 251 to the selector 253 via the selector 252.

As a result, from the multiplier 247 to the selector 2
The correction amount dMX is supplied to the adder 255 via 53. Here, since the correction amount dMX is a negative value, FIG.
As shown in (b), the addition result dM1 is the corrected target pixel value d
It is lower than M '. After that, when the subtraction result “dM′−dM” exceeds the threshold value th_m at the coordinate value x ₁₂ , the comparator 251 outputs the “0” signal again, so the selector 253 selects the value “0” and the addition result. dM1
Becomes equal to the corrected pixel value of interest dM '.

After that, when the coordinate value x becomes substantially the intermediate value between x ₁₂ and x ₁₃ , the sign of the subtraction result "dM'-dM" is changed to positive, and the selector 252 selects the output signal of the comparator 250. It However, since the subtraction result is less than the threshold value th_p at this point, the comparator 250 outputs the “0” signal. Therefore, the addition result dM1
Then becomes equal to the correction amount dMX.

Next, in the section where the coordinate value x is x ₁₃ ,
Since the subtraction result “dM′−dM” becomes equal to or larger than the threshold value th_p, the “1” signal is supplied from the comparator 250 to the selector 253 via the selector 252.
The correction amount dMX is supplied to the adder 255 via. Here, since the correction amount dMX is a positive value, the addition result dM1 becomes higher than the correction target pixel value dM ′ as shown in FIG. 12B.

After that, the addition result dM1 changes in the reverse order of the above operation. That is, the coordinate value x is x ₁₄ ~x enter the addition result to ₁₅ sections of dM1 is equal to the modified target pixel value dM ', result of addition to fall in the interval x ₁₅ ~x ₁₆ dM1
Is lower than the modified pixel value of interest dM '. Although the above-described operation has been described in the case where the corrected target pixel value dM ′ is selected by the selector 254, the same operation is performed even when the target pixel value dM is selected.

In FIG. 12 (b), the corrected target pixel value dM '
And the addition result dM1 are compared, there is a tendency to emphasize the edge (a tendency to increase the height near the mountain top and lower the foot portion).
It is understood that is stronger in the addition result dM1. That is, in the present embodiment, by adding a small number of circuits (the portion of the subtraction circuit 244 to the adder 255) to the general linear spatial digital filter circuit 420, the linear spatial digital filter circuit is extremely effective. It becomes possible to perform sharp edge enhancement that was not possible.

Returning to FIG. 8, reference numerals 230 to 232 are flip-flops, which sequentially delay the corrected target pixel value dM '. The output signals of the flip-flops 230 and 231 are added in the adder 233. A register 234 stores a predetermined constant (for example, "0.25"). The multiplier 236 multiplies the addition result by the constant and outputs the result. Further, the register 235 stores another constant (for example, “0.5”).

The output signal of the flip-flop 231 is supplied to the multiplier 237, where it is multiplied by the other constants. The multiplication results of the multipliers 236 and 237 are added in the adder 238, and the result is output as the addition result dM2. Therefore, the addition result dM2 is a smoothed version of the modified pixel value of interest dM '. A selector 256 selects one of the addition results dM1 and dM2 based on the filter switching signal FCX (see FIG. 6) and outputs the selected result as image data CD0.

That is, the comparison results FC1, FC2, FW
When any one of C1 becomes "1" (when an edge is detected), the filter switching signal FCX becomes "1". As a result, the addition result dM1 is selected, and the result of the sharp edge enhancement is output as the image data CD0. On the other hand, when the filter switching signal FCX is "0", the addition result dM2 in which the edges are slightly emphasized with respect to the target pixel value dM is output as the image data CD0.

[Operation of Embodiment] A. Copy Mode When the user performs a predetermined operation (for example, pressing a copy start button) on the operation / display panel 407, the operation mode of the multifunction peripheral is set to the copy mode, and the input select signal INSEL is set to "0". As a result, the output select signal OUTSEL is also set to "0". Next, when the content of the original is read by the image reading device 401, the image data is supplied to the edge correction processing unit 403 via the selector 602 and the input gradation correction unit 402.
At that time, the CPU 409 outputs a type detection signal STYPE indicating the type of the original image.

If there is no edge in the 5 × 5 matrix in the matrix circuit 410, the comparison result WC1
˜WC3 and FWC1 (see FIG. 5) are all “0”, so that the edge presence / absence determination signal MI1 is also “0”. As a result, the waveform control signal ATB1 is fixed to "00", and the selector 164 of the waveform control screen generation unit 405 selects the pattern signal S _A.

Next, when a strong edge occurs to some extent along the main scanning direction or the sub-scanning direction within the 5 × 5 matrix, any one of the comparison results WC1 to WC3 becomes "1", and the edge presence / absence determination signal MI1. Also becomes "1". Therefore, as shown in Table 1, the waveform control signal ATB1 is selected based on the comparison results MI2 and MI3. This allows
In the waveform control screen generator 405 (see FIG. 9), the pattern signals S _A , S _B and S _C are appropriately switched,
A triangular wave is selected according to the edge direction.

However, the comparison results FC1, FC2, FWC
If the edge is not strong enough to cause any one of "1" to become "1", the filter switching signal FCX becomes "0". As a result, in the selector 256 (see FIG. 8), the addition result dM2 with the edge slightly emphasized is selected as the image data CD0 and supplied to the waveform control screen generation unit 405.

On the other hand, in the output gradation correction logic multiplexer 137, the gradation correction control signal MTSEL corresponding to the pattern signal is selected. This allows
In the output gradation correction unit 404, screen characteristics corresponding to the pattern signals S _A , S _B , and S _C are added to the image data CD0, and the result is output as the image data CD1. The waveform control screen generator 405 generates a pulse width modulation signal based on the image data CD1 and the waveform control signal ATB1. As a result, in the image output device 406, an image with slightly enhanced edges is output on a sheet.

Next, in the 5 × 5 matrix, in the main scanning direction,
When a stronger edge occurs along the sub-scanning direction or the tilt direction, one of the comparison results FC1, FC2, FWC1 becomes "1", and the filter switching signal FCX also becomes "1". As a result, in the selector 256, the addition result dM1 in which the edge is considerably emphasized is selected as the image data CD0, and the waveform control screen generation unit 4
05. As a result, the output gradation correction unit 40
4, through the waveform control screen generation unit 405 and the image output device 406, an image with considerably emphasized edges is output to the paper.

B. Print mode Host computer to printer interface 6
When the print data is supplied to 01, the operation mode of the multifunction peripheral is set to the print mode and the input select signal I
NSEL is set to "1". As a result, the supplied print data is supplied to both the binary edge determination unit 603 and the input gradation correction unit 402, and the smoothing processing is performed in parallel on both.

When the print data is multi-valued image data, the binary edge determination signal EGH is generally used.
Becomes "0". Thereby, the selectors 606 and 607
In this case, the image data CD1 and the waveform control signal AT
B1 is selected. That is, in such a case, the image data CD2 and the waveform control signal ATB2 are ignored, and the same processing as that described in the copy mode is executed.

On the other hand, when the binary image data is supplied as the print data, the binary edge determination signal EGH becomes "1".
And the output select signal OUTSEL also becomes "1". As a result, the image data CD2 and the waveform control signal ATB2, which are the result of the binary smoothing process, are transferred to the waveform control screen generator 4 via the selectors 606 and 607.
05. As a result, the image that has been subjected to the smoothing processing suitable for the binary image data is output by the image output device 40.
6 is output.

Here, the print data may be a mixture of binary image data and multi-valued image data. For example, it is an image in which a photograph and characters are combined, an image in which characters are appropriately shaded, and the like. When such print data is supplied, the 3 × 3 matrix circuit 282 (see FIG.
3), the selectors 606 and 607 are switched for each pixel, and smoothing processing suitable for each part is performed.

Even if the print data is multi-valued image data, it cannot be denied that pixels having pixel values of "0" and "255" are adjacent to each other. In such a case, it is determined that the print data is binary image data even though the print data is multivalued image data, and the smoothing process for the binary image data is performed on the multivalued image data. However, such a situation is unlikely to occur, and the effect on the entire image is insignificant.

[Modification] The present invention is not limited to the above-described embodiment, and various modifications can be made, for example, as follows. In the above-described embodiment, the determination as to whether the print data is binary image data or multi-valued image data is performed by determining pixel values of “255” and “0” that are adjacent in the main scanning direction or the sub scanning direction. It has been done based on whether there are two pixels having. However, such a determination may be made based on other conditions. For example, a 3 × 3 matrix circuit 2
It may be determined that the image data is binary image data only when “255” and “0” both exist as pixel values in 82 and no other pixel values exist.

In the above-described embodiment, an example in which the present invention is applied to a monochrome multifunction peripheral has been described. However, the present invention is applied to each primary color (cyan, magenta, yellow, black), so that the present invention is executed. It goes without saying that it can be applied to.

In the above embodiment, the addition target dM2 is obtained by performing the filtering process on the corrected target pixel value dM '.
However, the corrected target pixel value dM ′ may be directly supplied to the selector 256 instead of the addition result dM2.

[0112]

As described above, according to the inventions according to claims 1 to 3, one of the first and second signals is selected according to the attribute of the image data, so that the same attribute is set. It is not necessary to provide a plurality of signal generating means corresponding to the image data that it has. Further, in the configuration according to claim 4, one of the multivalued image data and the binary image data is selected based on the attribute of the multivalued image data. Therefore, in any case, it is possible to realize abundant functions with an inexpensive structure.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a multifunction peripheral according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an edge correction processing unit 403.

FIG. 3 is a block diagram of a matrix circuit 410 and the like.

FIG. 4 is a block diagram of an edge detection filter circuit 430.

FIG. 5 is a block diagram of an edge strength determination circuit 450 and an edge direction detection circuit 460.

FIG. 6 is an edge direction determination logic circuit 500 and T.
5 is a block diagram of an RC tag generation lookup table 510. FIG.

7 is a block diagram of a spatial digital filter circuit 420. FIG.

FIG. 8 is a block diagram of a non-linear filter circuit 480.

9 is a block diagram of a waveform control screen generator 405. FIG.

FIG. 10 is an explanatory diagram of image data smoothing processing.

FIG. 11 is a diagram showing correction characteristics of an output gradation correction unit 404.

FIG. 12 is an operation explanatory diagram of the non-linear filter circuit 480.

FIG. 13 is a block diagram of a binary edge determination unit 603.

FIG. 14 is a block diagram of a binary smoothing processing unit 604.

15 is an operation explanatory diagram of the binary smoothing processing unit 604. FIG.

[Explanation of symbols]

401 image reading device (original image reading means) 403 edge correction processing section (first signal generation means) 405 waveform control screen generation section (output control means) 601 printer interface (input selection means) 604 binary smoothing processing section (Second signal generating means) 606, 607 Selector (output selecting means) 283 Comparator (binarizing means)

Claims (4)

[Claims] 1. A first signal for designating a dot type and a dot size of the pixel of interest based on the pixel value of the pixel of interest of the image data and the pixel values of peripheral pixels of the pixel of interest. A second signal for designating a dot type and a dot size relating to the pixel of interest based on a pixel value of the pixel of interest and a pixel value of peripheral pixels of the pixel of interest. Second signal generating means for outputting the first or second signal generating means according to the attribute of the image data.
Output selection means for selecting one of the signals, and output control means for generating a display signal for outputting the image data based on the signal selected by the output selection means. Image processing device. 2. The output control means includes an analog signal generating means for generating an analog signal having a level according to a size of a designated dot, and a plurality of pattern signals according to a type of the designated dot. From the pattern signal selecting means for selecting any of the pattern signals from, to generate the display signal based on the comparison result of the selected pattern signal and the analog signal, the output selecting means, When the image data is multi-valued image data, the first signal is selected, and when the image data is binary image data, the second signal is selected. The image processing apparatus according to claim 1. 3. An original image reading means for reading an original image, a print data receiving means for receiving print data, one of an output signal of the original image reading means and the print data, and the first signal generating means. 3. The input selection means for supplying the print data to the second signal generation means, wherein the print data reception means supplies the print data to the second signal generation means regardless of the selection state of the input selection means. The image processing device described. 4. A binarization unit for converting multi-valued image data into binary image data, and one of the multi-valued image data or the binary image data is selected based on an attribute of the multi-valued image data. An image processing apparatus, comprising: an output selecting unit that outputs the image data and an output control unit that outputs the image data selected by the output selecting unit.