JPH09107033A - Layout design method and apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the design of a chip having a small layout area which meets required path propagation time by computing the shiftable lengths of block outside pins within required signal propagation time and making a block layout giving these lengths as a degree of freedom. SOLUTION: For a required signal propagation time stored in a propagation time restriction memory 106, a propagation time analyzer 107 computes the propagation time margin of the signal propagation time between paths and stores it in a propagation time margin memory 108. It converts this margin into an inter-block wiring length to compute the margin of the inter-block wiring. Based on this margin, a block pin shiftable length processor 109 compute the block outside pin shiftable length and stores it in a block pin shiftable length memory 110. In-block layout part 111 makes layout in a block on account of the block outside pin movable length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit design method, and more particularly to layout design.

[0002]

2. Description of the Related Art In recent years, due to the progress of microfabrication technology, the high degree of integration of semiconductors has led to an increase in the number of logic elements mounted on one chip and an increase in the signal propagation time delay (wiring delay) due to wiring. Is also causing.

In order to solve the problem of wiring delay, conventionally, a method of designing a logic circuit by predicting the wiring delay by performing floorplan processing has been used.

FIG. 5 is a processing flow chart showing an example of logic design using conventional floorplan processing.

In FIG. 5, 501 to 507 are processing steps, 501 is a step of dividing a logic circuit into a plurality of blocks, 502 is a step of deciding external pin positions of the blocks and wiring between blocks, and 503 is a step. A step of obtaining all wiring load resistance values based on a wiring route between blocks and a wiring load resistance value list according to the number of wiring branches inside the block, and 504, the step 503.
A step of calculating the signal propagation time between the storage elements based on the pre-wiring load resistance value obtained in step S5 and comparing the signal propagation time with the required signal propagation time. Reference numeral 505 denotes a drive logic element for keeping the signal propagation time within the required time. A step of exchanging a block having a higher driving capability, a step 506 of re-estimating the block size of the block including the logic element exchanged in the step 505, and a step of re-adjusting the block arrangement position according to the change of the block size, Reference numeral 507 is a step for performing layout within a block.

Next, the processing flow will be described with reference to the processing flow chart of FIG. First, in step 501, the logic circuit is divided into a plurality of blocks, and blocks having strong connection relationships are arranged at adjacent positions in the chip while predicting the block size.

Next, in step 502, the external pin positions of the blocks are determined so that the total wiring length between the blocks is shortened, and wiring between the blocks is performed.

In step 503, the wiring load resistance values obtained from the wiring results are used between the blocks, and the wiring load resistance values depending on the number of wiring branches are used in the blocks to determine the distance between the signal storage elements.
Calculate the wiring load resistance value for each (hereinafter referred to as the path).

In step 504, the signal propagation time between the paths is calculated, and it is checked whether or not there is a path that takes more time than the required signal propagation time. If there is, step 505.
If no, go to step 507.

If there is, in step 505, the drive logic element related to the path is replaced with a drive logic element having a high drive capability so as to be within the required signal propagation time.

If not, for the block including the logic circuit changed in step 506, the block size is re-predicted, the block arrangement position is readjusted, and the process is repeated from step 502.

In step 507, the layout within the block is performed so that the block external pin positions determined in step 502 are not changed.

In such a conventional method, since the external pin position of the block is determined before laying out the inside of the block, the degree of freedom when laying out inside the block is lowered and the layout size is increased as a result. .

In order to solve this problem, step 5
If the block external pin position is released before 07, the signal propagation time between the paths will be different between the step 504 and the step after the end of step 507. For this reason, it is necessary to reset the total wiring load resistance value between the blocks to a large value at the stage of step 503 and to use a large signal propagation time at step 504. This is because if the signal propagation time in step 504 is smaller than the signal propagation time after step 507, there is a possibility that a path that does not satisfy the signal propagation time required after step 507 may occur.
If this occurs, it will be necessary to redesign and the design period will increase.

However, in this method, since all the signal propagation times are predicted to be large, step 505 is unnecessarily executed, and a logic circuit having a driving capacity higher than necessary can be obtained. Generally, as the driving capability increases, the area of the logic element increases, resulting in an unnecessarily large layout area.

The problem as described above is that the block external pins are uniformly treated and not individually treated, such as whether all external pin positions of the block are determined at the time of logic design.

[0017]

In the conventional method as described above, there is a problem that the chip area becomes unnecessarily large if it is designed so as to satisfy the required signal propagation time.
Also, in order to reduce the chip area, step 50
Release the block pin position before step 7 to increase the degree of freedom in layout and risk redesigning after step 507. Use this in the current design environment where there is not enough time for design. I can't.

The present invention solves the problems of the conventional method as described above. When checking whether the signal propagation time is within the required signal propagation time, is there a margin for the signal propagation time? By processing each of the external pins of the block to increase the degree of freedom in layout by increasing the movable amount of the external pin position of the block for the block external pin related to the path with a large margin value, An object of the present invention is to enable the design of a chip with a small layout area that satisfies the required propagation time of paths without designing.

[0019]

In order to achieve this object, according to the present invention, a circuit storage unit for storing a logic circuit and a wiring load resistance storing a list of wiring load resistance values according to the number of wiring branches. A model storage unit, a propagation time constraint storage unit that stores a signal propagation time required between signal storage elements, and a logic circuit stored in the circuit storage unit are divided and arranged into a plurality of blocks, and each block is externally arranged. A floor plan section for temporarily deciding pin positions to perform wiring between blocks, an inter block inter-block wiring result determined by the floor plan section, and an inside block are stored in the wiring load resistance model storage section. Based on the wiring load resistance value list, a wiring load resistance calculation unit that calculates the load resistance value of the wiring for each signal storage element, and for each signal storage element calculated by the wiring load resistance calculation unit. A wiring load resistance storage unit that stores a line load resistance value, and a signal propagation time between signal storage elements is calculated based on the wiring load resistance value stored in the wiring load resistance storage unit, and the result is the propagation time constraint. A propagation time analysis unit that calculates a margin value of the signal propagation time compared with the required signal propagation time stored in the storage unit, and a signal propagation time for each signal storage element obtained by the propagation time analysis unit Based on the margin value of the signal propagation time stored in the propagation time margin value storage unit and the propagation time margin value storage unit,
A block pin movable amount calculation unit that calculates the movable amount of the external pin of each block for each signal storage element related to the wiring between blocks, and the external pin movement of the block calculated by the block pin movable amount calculation unit A configuration of a block pin movable amount storage unit that stores the amount, and an intra-block layout unit that lays out each block in consideration of the movable amount of the external pin of the block stored in the block pin movable amount storage unit have.

With this configuration, it is possible to perform the in-block layout by providing the block external pin positions with a degree of freedom within a range that satisfies the required signal propagation time.
Therefore, it is possible to perform the layout having the smallest area and satisfying the required signal propagation time.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a first embodiment of the present invention. In FIG. 1, 10
Reference numeral 1 denotes a logic circuit storage unit that stores a logic circuit. Reference numeral 102 denotes a block in which a logic circuit stored in the logic circuit 101 is divided into a plurality of blocks and arranged in a chip, and then a layout position of a block external pin is provisionally determined. A floor plan unit for inter-wiring, 103 is a wiring load resistance model storage unit that stores a list of wiring load resistance values according to the number of wiring branches, and 104 is for each block based on the inter-block wiring result and for each block. Is a wiring load resistance calculation unit that calculates the wiring load resistance value for each path based on the wiring load list stored in the wiring load model storage unit 103, and 105 is for each path calculated by the wiring load resistance calculation unit 104. , A wiring load resistance value storage unit for storing the wiring load resistance value, and a propagation time constraint storage unit 106 for storing the signal propagation time required between paths,
Reference numeral 107 calculates the signal propagation time based on the wiring load resistance value for each path stored in the wiring load resistance value storage unit 105, and the required signal propagation stored in the propagation time constraint storage unit 106 of the calculation result. A propagation time analysis unit for calculating a margin value with respect to time, 108 is a propagation time margin value storage unit for storing the margin value of the signal propagation time calculated by the propagation time analysis unit 107, and 109 is stored in the propagation time margin value storage unit 108. Based on the margin value of the signal propagation time for each path between, for each path involved in inter-block wiring, the block pin movable amount calculation unit that calculates the external pin movable amount of each block,
110 is a block pin movable amount storage unit that stores the external pin movable amount of the block calculated by the block pin movable amount calculation unit 109, and 111 is an external pin of the block stored in the block pin movable amount storage unit 110. This is an intra-block layout unit that lays out the inside of the block in consideration of the movable amount.

FIG. 2 is a processing flow chart showing the processing flow of the layout design apparatus of FIG. In FIG. 2, 2
01 to 203 are processing steps, and 201 is a propagation time margin value for calculating the propagation time margin value of the signal propagation time between the paths with respect to the required signal propagation time stored in the propagation time constraint storage unit 106. Step 202 of storing in the storage unit 108, Step 202 of converting the margin value of the signal propagation time stored in the propagation time storage unit 108 into the inter-block wiring length, and calculating the margin length of the inter-block wiring, 20
Step 3 is a step of calculating the external pin movable amount of the block based on the margin value of the inter-block wiring length calculated in step 202. Further, 501 to 507 are similar to the steps of FIG. 5 used in the description of the prior art.

The process flow of this embodiment will be described below with reference to FIG. 1 and along the process flow diagram of FIG.

First, in step 501, the circuit storage unit 101
Divide the logic circuit stored in to multiple blocks,
While predicting the block size, blocks having a strong connection relationship are arranged at adjacent positions.

Next, in step 502, the external pin positions of the blocks are determined so that the total wiring length between the blocks is shortened, and wiring between the blocks is performed.

In step 503, a list of wiring load resistance values obtained from the wiring results is used between blocks, and a list of wiring load resistance values depending on the number of wiring branches stored in the wiring load resistance model storage unit 111 is used in each block. Then, the total wiring load resistance value is calculated and stored in the wiring load resistance value storage unit 105.

In step 504, the signal propagation time between the paths is calculated, and it is checked whether or not there is a path that takes longer than the required signal propagation time. If there is, a step 505 is performed.
If not, go to step 201.

If there is a path longer than the required signal propagation time, in step 505, the drive logic element related to the path is exchanged with one having a high driving capability so that the path is within the required signal propagation time. Subsequently, with respect to the block including the logic circuit changed in step 506, the block size is re-estimated, the block arrangement position is readjusted, and step 502 is performed again.

When all the buses satisfy the required signal propagation time, it is checked in step 201 for each inter-block wiring whether or not there is a path shorter than the required signal propagation time, and the path exists. In this case, the propagation time difference from the required signal propagation time is set as the margin value of the signal propagation time,
It is stored in the propagation time margin value storage unit 107. Zero is stored in the propagation time margin value storage unit 107 for a path having no margin value for the signal propagation time.

Next, the margin value of the signal propagation time relating to the inter-block wiring stored in the propagation time margin value storage unit 107 in step 202 is converted into the margin length of the inter-block wiring. The formula for calculating the margin length of this inter-block wiring is (Equation 1)
Shown in

[0032]

(Equation 1)

In (Equation 1), T is the signal propagation time and I
Is the propagation time of the logic element in the no-load state (a constant value for each logic element), f is the propagation delay function depending on the wiring load value (this is C), g is the wiring load value (C) and the wiring resistance It is a propagation delay function that depends on the value (this is R).

Here, the wiring load value (C) and the wiring resistance value (R) are respectively functions P of the wiring length (L).
Since it can be expressed by (L) and Q (L), the signal propagation time (T) can be expressed by the wiring length (L) as in (Equation 2).

[0035]

(Equation 2)

Therefore, the margin value of the signal propagation time is set to Ts.
In this case, if the wiring margin length is Ls, the inverse function of (Equation 2) is obtained and Ls is calculated from Ts.

Next, in step 203, the movable amount of the block pin is calculated using the margin value (Ls) of the inter-block wiring, and stored in the block pin movable amount storage unit 109.

FIG. 3 is a diagram for explaining the processing of step 203 in detail. FIG. 3A is a diagram showing an example of a floor plan in which wiring between blocks is performed.
FIG. 3B shows the external output pin 3 of the block in FIG.
FIG. 5 is a diagram for explaining in more detail 05.

In FIG. 3A, 301 to 303 are blocks, 304 and 306 are input external pins of the blocks, 3
Reference numeral 05 is an output external pin of the block, 307 to 309 are movable amounts of the external pin of the block, 310 is an inter-block wiring, and in FIG. 3B, 311 is a margin length of the inter-block wiring 310 with respect to one block external pin. Numeral 312 is the external pin position of the block where the margin length of the inter-block wiring 310 is zero, 313 is the external pin movable amount of the block when the inter-block wiring 310 is long, and 314 is the block with the shortest inter-block wiring. The external pin position 315 is the external pin movable amount of the block when the inter-block wiring 310 becomes short.

FIG. 4 is a processing flow chart showing the processing of step 203 in more detail. In FIG.
Reference numeral 8 is a processing step.

The calculation method of step 203 will be described below with reference to FIG. 3 along with the process flow chart of FIG.

First, in step 401, the step 2
In order to evenly allocate the margin length of the inter-block wiring 310 calculated in 02 (this value is Ls) to the two block external pins, divide Ls by 2 and leave the margin of the inter-block wiring 310 for one block external pin. Calculate the length 311 (this value is Lsp).

Next, in step 402, the output external pin 30
5 and its pin and block external pin 3 with the longest wiring route
Select the two block external pins 04. If there are only two block external pins connected to the inter-block wiring, select the two block external pins at both ends of the wiring.

Next, at step 403, at step 40
With respect to the two block external pins selected in 2, moved by (Lsp) from the position of the block external pin 305 (this value is Pd) in the direction in which the inter-block wiring length becomes longer (the direction of the arrow 311). The range (Pd) up to the external pin position 312 of the block (this position is Pw)
~ Pw) is the amount of movement of the block external pin 305 313
(This value is M).

Next, in step 404, it is examined whether or not there is an external pin position 314 (where this position is Pb) of the block in which the inter-block wiring length is shortened. If it exists, the process proceeds to step 405 and does not exist. If step 4
Proceed to 06.

At step 405, the movable amount (M) of the block external pin 305 is defined by adding (Pb to Pw) the range up to the block pin position 314 (Pb) where the inter-block wiring length is shortened.

Up to this stage, the movable amounts (M1, M2) for the two block external pins 304, 305 are set.
307 and 308 can be determined.

In step 406, it is checked whether or not there are three or more block external pins connected to the inter-block wiring. If yes, the process proceeds to step 407.
Proceed to 08.

In step 407, if the block external pin 306 of the movable amount not selected in step 402 has an external pin position that does not lengthen the inter-block wiring with the output external pin 305, the range 309 is blocked. External pin movable amount (denoted as M3).

In step 408, the external pin movable amount (M1, M2, M3) of the block is stored in the block pin movable amount storage unit 109.

Since it is possible to calculate the movable amount of the block external pin in the processing of step 203, finally in step 507, the inside of the block is laid out based on the movable amount of the block external pin position.

It is generally known that, in layout, the looser the constraint on the block external pin position, the smaller the block area. Therefore, the amount of movement of the external pins of the block becomes a degree of freedom in layout, and a layout result having a small area can be obtained. Furthermore, since the movable amount of the external pin position of the block is set within the range that satisfies the required signal propagation time only for the path having a sufficient signal propagation time, the layout process of step 507 is completed. Even after that, a path having a propagation time longer than the required signal propagation time does not occur.

[0053]

As described above, in the present invention, the movable amount of the block external pin is calculated within the required signal propagation time, and the movable amount is given as the degree of freedom to perform the block layout. Thus, it is possible to perform the layout with the smallest area, which satisfies the required signal propagation time. As a result, it is guaranteed that the required signal propagation time is satisfied after the layout of all blocks is completed, so that design rework is eliminated and the design period is shortened. Furthermore, reducing the layout area also has the effect of reducing the chip cost.

[Brief description of the drawings]

FIG. 1 is a configuration diagram according to a first embodiment.

FIG. 2 is a process flow chart according to the first embodiment.

FIG. 3 is a diagram showing a method of calculating an external pin movable amount of a block according to the first embodiment.

FIG. 4 is a process flow chart for calculating an external pin movable amount of a block according to the first embodiment.

FIG. 5 is a processing flow chart showing an example of a conventional technique.

[Explanation of symbols]

 101 logic circuit storage unit 102 floor plan unit 103 wiring load resistance model unit 104 wiring load resistance calculation unit 105 wiring load resistance storage unit 106 propagation time constraint storage unit 107 propagation time analysis unit 108 propagation time allowance storage unit 109 block pin moveable Amount calculation unit 110 Block pin movable amount storage unit 111 In-block layout unit

Claims (4)

[Claims] 1. A layout design method for an LSI, wherein a layout design is performed by applying a constraint condition to satisfy a signal propagation time required between signal storage elements. 2. The layout design method according to claim 1, wherein the constraint condition is expressed by a movable amount of an external pin of each block that is a target of layout design. 3. A process of calculating a signal propagation time between signal storage elements extending between the blocks using a result of wiring between blocks of the block, and a difference between the calculation result and a required signal propagation time. 3. The layout according to claim 2, further comprising: a process for obtaining a margin length of the inter-block wiring from the process; and a process for calculating the movable amount by distributing and assigning the margin length to the block external pins. Design method. 4. An LSI layout design apparatus, a circuit storage section for storing a logic circuit, a wiring load resistance model storage section for storing a list of wiring load resistance values according to the number of wiring branches, and a signal storage element. A propagation time constraint storage unit that stores a signal propagation time required between and a logic circuit stored in the circuit storage unit are divided and arranged into a plurality of blocks, and the external pin positions of each block are provisionally determined and A list of wiring load resistance values stored in the wiring load resistance model storage unit based on the wiring results between blocks determined by the floorplan unit for the floor plan section that performs wiring between A wiring load resistance calculating unit for calculating a load resistance value of a wiring for each signal storage element based on the above, and a wiring for each signal storage element calculated by the wiring load resistance calculating unit. A wiring load resistance storage unit that stores a load resistance value, based on the wiring load resistance value stored in the wiring load resistance storage unit, calculates a signal propagation time between signal storage elements, and stores the result as the propagation time constraint storage. Compared with the required signal propagation time stored in the unit, the propagation time analysis unit for calculating the margin value of the signal propagation time, and the signal propagation time for each signal storage element obtained by the propagation time analysis unit Based on the propagation time margin value storage unit that stores the margin value, and the margin value of the signal propagation time stored in the propagation time margin value storage unit, the block external pin is moved for each signal storage element related to the inter-block wiring. A block pin movable amount calculation unit that calculates a movable amount; a block pin movable amount storage unit that stores the external pin movable amount of the block calculated by the block pin movable amount calculation unit; A movable amount of the external pins of the block stored in Kupyn movable amount storage unit by constraints layout designing apparatus which is characterized in that a block layout section for laying out in each block.