JPH09142844A - Method for producing bismuth oxide, method for forming oxide film, and method for producing capacitor structure of semiconductor device - Google Patents

Abstract

(57) [Abstract] [Problem] To have a sufficient vapor pressure at a low temperature and a high decomposition temperature
It is difficult to decompose in the process of vaporization and transportation, can maintain a stable vapor pressure for a long time, and the deposition rate is the feed rate-determining material at the deposition temperature, so that homogeneous nucleation reaction does not occur in the gas phase. Provided is a method for forming an oxide film, which uses a material and is not easily affected by the substrate temperature or the reaction pressure in the CVD method. SOLUTION: The oxide film is formed by using a bismuth organometallic compound having a bismuth-oxygen bond as a raw material, and CV.
An oxide film containing bismuth as a constituent element is formed by the D method. The oxide film is preferably formed of a Bi-based layered structure perovskite-type ferroelectric material, and more specifically, the oxide film is formed of a Y1-based material (Bi ₂ (Sr, Ba, Ca).
It is preferably composed of (Ta, Nb) ₂ O ₉ ).

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for producing bismuth oxide, a method for forming an oxide film, and a method for producing a capacitor structure of a semiconductor device.

[0002]

2. Description of the Related Art In recent years, application research of nonvolatile memory cells using a ferroelectric thin film has been actively pursued with the progress of film forming technology. This non-volatile memory cell is a non-volatile memory cell in which high-speed reversal of the ferroelectric thin film and high-speed rewriting utilizing the residual polarization thereof are possible. The ferroelectric thin film non-volatile memory cells that are currently being researched are classified into two types: a method of detecting a change in the stored charge amount of a ferroelectric capacitor and a method of detecting a resistance change due to spontaneous polarization of a ferroelectric substance. be able to. The semiconductor device of the present invention belongs to the former.

An example of a non-volatile memory cell that detects a change in the amount of charge stored in a ferroelectric capacitor is a non-volatile memory cell having a 1-capacitor + 1 transistor structure in which a selection transistor is added to the ferroelectric capacitor. You can The ferroelectric capacitor is composed of, for example, a lower electrode and an upper electrode, and a ferroelectric thin film sandwiched therebetween. Writing and reading of data in this type of non-volatile memory cell is performed by applying a ferroelectric PE hysteresis loop shown in FIG. When an external electric field is applied to the ferroelectric thin film and then the external electric field is removed, the ferroelectric thin film exhibits spontaneous polarization.
Then, the residual polarization of the ferroelectric thin film is a -P _r when when positive direction of the external electric field is applied + P _r, the negative direction of the external electric field is applied. Where remanent polarization is +
It is assumed that the state of P _r (see “D” in FIG. 14) is “0”, and the state of remanent polarization is −P _r (see “A” of FIG. 14) is “1”.

In order to determine the state of "1" or "0", an external electric field in the positive direction, for example, is applied to the ferroelectric thin film. Thus, the polarization of the ferroelectric thin film is in the state of “C” in FIG. At this time, if the data is "0", the polarization state of the ferroelectric thin film changes from "D" to "C". On the other hand, if the data is "1", the polarization state of the ferroelectric thin film changes from "A" to "C" via "B". If the data is "0",
The polarization reversal of the ferroelectric thin film does not occur. On the other hand, the data is "
In the case of 1 ", polarization inversion occurs in the ferroelectric thin film. As a result, there is a difference in the amount of charge stored in the ferroelectric capacitor. This storage is turned on by turning on the select transistor of the selected memory cell. The charge is detected as a signal current.
When the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric thin film becomes the state of “D” in FIG. 14 regardless of whether the data is “0” or “1”. Therefore, when the data is "1", an external electric field in the negative direction is applied to bring the state of "A" through the paths "D" and "E", and the data "1" is written.

A ferroelectric thin film made of a Bi-based layered structure perovskite type ferroelectric material (hereinafter sometimes referred to as a bismuth layered ferroelectric thin film) has the greatest drawback of the conventional PZT-based ferroelectric thin film. Since the fatig phenomenon (reduction of remanent polarization due to repeated rewriting of data) was not observed, it has been attracting attention as a ferroelectric thin film for the above nonvolatile memory. When applying a bismuth layered ferroelectric thin film to such a non-volatile memory, development of thin film forming technology is essential. Currently, MOD (Metal
It is said that a ferroelectric thin film exhibiting good ferroelectric characteristics can be obtained based on a spin coating method such as an organic decomposition method. However, in order to apply to a highly integrated memory, there is a strong demand for development of a MOCVD method which is excellent in step coverage, film quality, uniformity, suppression of particle generation and processing speed.

As a source material for MOCVD, (1) it has a sufficient vapor pressure at a low temperature (2) its decomposition temperature is high and it does not decompose in the process of vaporization and transportation (3) it is stable for a long time Maintaining vapor pressure (4) It is required that the deposition rate be the raw material supply rate at the deposition temperature and that homogeneous nucleation reaction in the gas phase does not occur. In addition, in order for the source gas to be constantly supplied at a saturated vapor pressure, it is desirable that it be a liquid or gas rather than a solid, and that there is no reaction between the source materials in the gas phase. It is a condition to be done. However, almost no commercially available source material for MOCVD for forming a bismuth layered ferroelectric thin film satisfies these conditions, and at present, it is dealt with by devising an MOCVD apparatus.

As the source material for MOCVD of bismuth, which is the main constituent element of the bismuth layered ferroelectric thin film, the following triphenylbismuth and its similar compounds are currently on the market.

[0008]

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[0009]

Triphenylbismuth vaporizes with decomposition at high temperatures. Therefore, it is difficult to control the temperature to maintain a stable vapor amount. For example, the literature, "Ferroelectric bismuth titanate films by hot w
all metalorganic chemical vapor deposition ", J. Si,
et al., J. Appl. Phys. 73 (11), 1 June 1993, pp791
According to 0-7913, in order to obtain a sufficient vapor pressure of triphenylbismuth, it is necessary to maintain the temperature of the raw material container at 165 to 170 ° C. When the raw material container is held at a high temperature in this way, the following adverse effects occur. (A) Triphenylbismuth in the raw material container is gradually decomposed by being exposed to a high temperature for a long time, which makes it difficult to maintain a stable gas supply. (B) In order to efficiently supply the gas and to prevent re-aggregation in the pipe during the transportation to the MOCVD reaction chamber, 150 to 200 parts of the MOCVD device such as the raw material container and the pipe are provided.
It is necessary to heat to ° C. However, temperature control and temperature management for that purpose are difficult.

Triphenylbismuth is a relatively stable substance, but on the other hand, its reactivity is low, so that M
When forming a ferroelectric thin film by the OCVD method, it is difficult to increase the component concentration. Furthermore, triphenylbismuth and its similar compounds do not have a metal-oxygen bond in the molecule, so they are not advantageous for forming an oxide film. When a ferroelectric thin film, which is an oxide film, is formed on the surface of the substrate, the reaction process on the substrate surface requires a reaction process with oxygen in addition to the decomposition reaction of triphenylbismuth. Therefore, when using these source materials, it is necessary to add an oxidizing source from the outside. The production of bismuth oxide using triphenylbismuth goes through the following process. _{-Bi-C 6 H 5 → -Bi-} + C 6 H 5 - -Bi- + O → -Bi-O-

That is, when bismuth oxide is produced using triphenylbismuth, a two-step reaction is performed. Therefore, the formation of bismuth oxide or the formation of an oxide film containing bismuth as a constituent element is easily affected by the substrate temperature and the reaction pressure in the MOCVD reaction chamber.

Therefore, an object of the present invention is to have a sufficient vapor pressure at a low temperature, have a high decomposition temperature, are difficult to decompose in the process of vaporization and transportation, and can maintain a stable vapor pressure for a long time. Yes, the deposition rate at the deposition temperature is the rate of raw material supply,
A method for producing bismuth oxide, a method for forming an oxide film, and a semiconductor device, which are made of a material that does not cause a homogeneous nucleation reaction in a gas phase and are not easily affected by a substrate temperature or a reaction pressure in a CVD method, It is to provide a method for manufacturing a capacitor structure.

[0013]

The method for producing bismuth oxide of the present invention for achieving the above-mentioned object comprises a bismuth-organic metal compound having a bismuth-oxygen bond as a raw material.
It is characterized in that bismuth oxide is generated by the CVD method.

Alternatively, in the method for forming an oxide film of the present invention for achieving the above object, a bismuth organometallic compound having a bismuth-oxygen bond is used as a raw material and is oxidized by a CVD method containing bismuth as a constituent element. It is characterized by forming a physical film. The structural formula of the bismuth organometallic compound having a bismuth-oxygen bond is shown below. In the formula below, X
₁ , X ₂ and X ₃ represent an alkyl group or a phenyl group.

[0015]

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It should be noted that the substituent "A" bonded to oxygen is replaced with an alkyl group having a relatively large number of carbon atoms (for example, a carbon number of 3 to 3).
By setting 6), it is preferable to prevent intermolecular polymerization and improve volatility. Alternatively, by making the substituent “A” bonded to oxygen have a structure containing oxygen, nitrogen, or a halogen element (F, Cl, I), it is possible to improve thermal stability and vaporization characteristics. Is possible. When the substituent “A” bonded to oxygen is an alkyl group,
A bismuth organometallic compound having a bismuth-oxygen bond is generally called a bismuth alkoxide compound. The substituent “A” includes C (CH ₃ ) ₃ and CH ₂ C (CH ₃ ).
₃ , CH (CH ₃ ) ₂ , (CH ₂ ) ₂ C (CH ₃ ) ₃ , C (C
F ₃ ) ₃ , CH ₂ C (CF ₃ ) ₃ , COCH ₃ , COC (CH
₃ ) ₃ , COCH ₂ C (CH ₃ ) ₃ , CO (C ₆ H ₅ ), CO
It can be exemplified NH ₂ and the like.

Alternatively, a method of manufacturing a capacitor structure of a semiconductor device of the present invention for achieving the above object is
(A) a step of forming a lower electrode layer on the substrate; and (b) a strong bismuth-containing element as a constituent element on the lower electrode layer using a bismuth organometallic compound having a bismuth-oxygen bond as a raw material. A step of forming a dielectric thin film,
(C) a step of forming an upper electrode layer on the ferroelectric thin film,
Characterized by comprising:

In the method for forming a ferroelectric thin film or the method for manufacturing a capacitor structure of a semiconductor device according to the present invention, the oxide film or the ferroelectric thin film is made of a Bi-based layered structure perovskite type ferroelectric material. You can
Specifically, the ferroelectric thin film is made of Bi ₂ SrTa ₂ O ₉ , B.
i ₂ SrNb ₂ O ₉ , Bi ₂ BaTa ₂ O ₉ , Bi ₄ SrTi ₄
O ₁₅ , Bi ₄ Ti ₃ O ₁₂ , Bi ₂ SrTa _x Nb _2-x O ₉ , B
Examples thereof include i ₂ PbTa ₂ O _{9 and the} like. Among them, the ferroelectric thin film is formed of a Y1-based material (Bi ₂ (Sr, B
a, Ca) (Ta, Nb) ₂ O ₉ ), and more preferably the Y1-based material is Bi ₂ SrTa ₂ O ₉ .

In the present invention, since a bismuth organometallic compound having a bismuth-oxygen bond (Bi (OA) ₃ ) is used as a source material for CVD, an oxide, an oxide film or a ferroelectric thin film (hereinafter, referred to as a general term). Sometimes referred to as an oxide or the like) can be easily generated or formed. This is because the oxygen atom in the bismuth-organic metal compound having a bismuth-oxygen bond is easily taken into the oxide network, and the oxide or the like can be produced or formed without adding an oxidizing source from the outside. -Bi-O-A- → -Bi-O- + A

Therefore, the production or formation of the oxide or the like from the organometallic compound is completed by a one-step reaction. When forming or forming an oxide or the like, a bismuth organometallic compound having a bismuth-oxygen bond is obviously more advantageous as a CVD source material than triphenylbismuth. CV for obtaining an oxide film or a ferroelectric thin film having a desired composition by using such a bismuth-organic metal compound having a bismuth-oxygen bond
It is possible to widen the allowable range of D condition (temperature, pressure, etc.). Furthermore, because of its high reactivity, oxides and the like can be generated or formed at lower temperatures.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings based on an embodiment of the invention (hereinafter, simply referred to as an embodiment).

(Embodiment 1) Embodiment 1 is a bismuth organometallic compound having a bismuth-oxygen bond.
A bismuth oxide thin film is formed by a CVD method (more specifically, M by using tributoxy bismuth [Bi (OC (CH ₃ ) ₃ ) ₃ ]).
OCVD method). As shown in the conceptual diagram of FIG. 1, the MOCVD apparatus includes stainless steel raw material containers 10 and 12, a MOCVD reaction chamber 20, and stainless steel pipes 14 and 15 connecting the raw material containers 10 and 12 and the MOCVD reaction chamber 20. It is configured. The raw material containers 10 and 12 are housed in constant temperature baths 11 and 13,
The structure is such that the source material in the material containers 10 and 12 can be maintained at a desired temperature. A heating means (not shown) such as a heater is arranged in the pipes 14 and 15 to keep the raw material gas flowing in the pipes at a desired temperature. The raw material gas introduced into the MOCVD reaction chamber 20 is a gas spray nozzle 2
The substrate 30 placed on the substrate stage 22 via
Sprayed on. As a result, a thin film is formed on the surface of the base 30. A heater (not shown) is incorporated in the substrate stage 22 to heat the substrate 30 to a desired temperature. The inside of the MOCVD reaction chamber 20 is evacuated by the vacuum pump 23.

In carrying out the MOCVD method, tributoxybismuth filled in a stainless steel raw material container 10 is heated to 80 to 110 ° C. Argon gas having a flow rate of 50 to 100 cc is introduced into the raw material container 10,
Sublimate tributoxybismuth under heating and reduced pressure. At this time, if the heating temperature exceeds 110 ° C, a slight amount of tributoxybismuth is decomposed with sublimation, so the heating temperature of tributoxybismuth should not exceed 110 ° C. Then, the sublimated tributoxybismuth is introduced into the pipe 14 kept at about 110 ° C. and sent to the MOCVD reaction chamber 20. When conventional triphenylbismuth is used, it is necessary to keep the temperature of the raw material container at 165 to 170 ° C and the temperature of the pipe at 180 to 200 ° C.

Then, it is placed on the substrate stage 22,
When a gas containing tributoxybismuth is introduced together with oxygen gas and argon gas for dilution onto the substrate 30 kept at 400 to 800 ° C., preferably 450 to 650 ° C., bismuth oxide is formed on the substrate 30. grow up. Substrate 30 made of silicon semiconductor substrate, SiO ₂ , platinum (Pt), etc.
Bismuth oxide can be grown on top. On the other hand, when triphenylbismuth which is a conventional material is used, it is possible to form bismuth oxide on a substrate made of platinum, but it is not possible to form bismuth oxide on a silicon semiconductor substrate or SiO _2. Can not. Also in this regard,
The use of tributoxy bismuth as a source material is a great advantage. A comparison of the physical properties of tributoxybismuth and triphenylbismuth is shown in Table 1 below.

[0025]

[Table 1] Tributoxy bismuth Triphenyl bismuth Melting point 110 ° C 78 ° C Vaporization temperature 80-110 ° C 150-160 ° C Vaporization method Sublimation Evaporation (Bubbling) Vapor pressure 13Pa (100 ° C) 13Pa (80 ° C)

(Embodiment 2) Embodiment 2 relates to a method for forming an oxide film of the present invention. More specifically, an oxide film that is a ferroelectric thin film made of Y1 based material (Bi ₂ SrTa ₂ O ₉ ) by MOCVD using tributoxybismuth as a bismuth-organic metal compound having a bismuth-oxygen bond. A method of forming the will be described.

As in the first embodiment, tributoxy bismuth filled in the stainless steel raw material container 10 is heated to 80 to 110 ° C. Argon gas having a flow rate of 50 to 100 cc is introduced into the raw material container 10 to sublimate tributoxybismuth under heating and reduced pressure. And about 1
Sublimated tributoxybismuth is introduced into the pipe 14 kept at 10 ° C., and sent to the MOCVD reaction chamber 20. On the other hand, tantalum pentaethoxide [Ta (OC ₂ H ₅ ) ₅ ] filled in another raw material container 12 is heated to 120 ° C.,
Bubble with argon gas at a flow rate of 50 to 100 cc. The vaporized tantalum pentaethoxide was introduced into a stainless steel pipe 15 heated to 130 ° C.
It is conveyed to the OCVD reaction chamber 20. Furthermore, strontium dipivaloyl methanetetraethylenepentamine (C ₃₈ H ₈₄ O ₄ N ₁₀ S) charged in another raw material container (not shown) was used.
r) is heated to 150 ° C. and bubbled with argon gas having a flow rate of 50 to 100 cc. Introduce vaporized strontium DPM tetraethylenepentamine into a stainless steel pipe (not shown) heated to 160 ° C,
It is conveyed to the MOCVD reaction chamber 20. Platinum (P) maintained at 400 to 800 ° C, preferably 450 to 700 ° C
On the substrate 30 consisting of t), the above three source materials, that is, tributoxybismuth, tantalum pentaethoxide and strontium DPM tetraethylenepentamine, are simultaneously added to the substrate 30 together with oxygen and argon gas for dilution.
When it is introduced into the surface of, an oxide film of Bi, Sr, and Ta is formed on the surface of the substrate 30. Desired composition (Bi
/ Sr / Ta = 2/1/2), the flow rate of the argon gas introduced into the raw material container and the heating temperature of the raw material container are adjusted to control the amount of each source material supplied to the MOCVD reaction chamber 20. do it. As a result, Bi ₂ SrTa ₂ O
_An oxide film, which is a ferroelectric thin film made of _9, can be formed.

The MOCVD method described above is a general MOCVD method in which a carrier gas is introduced into a source material filled in a stainless steel material container to vaporize the source material, but in addition, the source material is dissolved in a liquid, It is also possible to employ a flash MOCVD method in which the source materials are transported and mixed in a liquid phase and flash vaporized in a vaporization chamber (see Kirlin US Pat. No. 5,204,314). The outline of the film forming method by the flash MOCVD method will be described below.

In this case, as the substrate, for example, a substrate obtained by sequentially depositing titanium (Ti) and platinum (Pt) on a silicon semiconductor substrate by a sputtering method is used. Then, as a source material, tributoxy bismuth, pentaethoxy tantalum and strontium dipivaloylmethanetetraethylene pentamine are used, and each of these source materials is dissolved in an organic solvent such as tetrahydrazine (THF) and in a liquid state. Transport independently. Then, these three types of source material solutions are mixed at a ratio determined by a mixing manifold and introduced into the vaporization chamber together with an argon carrier gas. 0.1-10 Torr in the vaporization chamber
Reduce the pressure to (1.3 × 10 Pa to 1.3 × 10 ³ Pa),
The introduced mixed solution is diffused and vaporized on the porous metal plate arranged in the vaporization chamber. In the reactor, the substrate on which platinum (Pt) is formed is kept at 400 to 800 ° C, preferably 450 to 700 ° C, and the vaporized source material is introduced into the reactor together with the carrier gas and the oxygen gas. As a result, on the platinum, Bi, Sr, Ta
It is possible to form an oxide film of. In order to obtain a desired composition (Bi / Sr / Ta = 2/1/2), the flow rate of oxygen gas, the pressure in the reactor, the mixing ratio of the source material solution in the mixing manifold, etc. may be adjusted. This makes it possible to form an oxide film which is a ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ .

A Y1-based material (Bi ₂ SrTa ₂ O) formed by using tributoxybismuth and triphenylbismuth
_The film forming characteristics of the oxide film composed of ₉ ) are shown in FIGS. 2 (A) and 2 (B). Specifically, FIG. 2A shows the substrate temperature dependence of the Bi concentration when the Sr concentration in the oxide film is 1. In addition, in FIG. 2B, S in the oxide film is
The pressure dependence of the Bi concentration in the MOCVD reaction chamber when the r concentration is 1 is shown. The solid line shows the case of tributoxybismuth and the dotted line shows the case of triphenylbismuth.

From FIGS. 2A and 2B, it can be seen that when triphenylbismuth is used, it is greatly affected by the substrate temperature and the pressure in the MOCVD reaction chamber. On the other hand, when tributoxy bismuth is used, the influence of the substrate temperature and the pressure inside the MOCVD reaction chamber is small. Therefore, when an oxide film containing a desired Bi as a constituent element is formed, the use of tributoxybismuth gives a permissible variation range of the substrate temperature, the reaction pressure, etc. in the CVD method rather than the use of triphenylbismuth. Can be bigger,
It is easy to control the composition of the oxide film. Therefore, if tributoxybismuth is used as the source material, the oxide film can be formed with good reproducibility.

(Embodiment 3) Embodiment 3 includes a step of forming a ferroelectric thin film containing bismuth as a constituent element by a CVD method using a bismuth organometallic compound having a bismuth-oxygen bond as a raw material. The present invention relates to a method for manufacturing a capacitor structure of a semiconductor device. The ferroelectric thin film is
It is composed of Bi ₁ SrTa ₂ O ₉ which is a Y1-based material, and the semiconductor element is composed of the above-mentioned nonvolatile memory cell (so-called FERAM).

FIG. 3A shows a schematic partial cross-sectional view of a semiconductor element manufactured according to the method of manufacturing the capacitor structure of the semiconductor element of the third embodiment. An equivalent circuit of the semiconductor element is shown in FIG. This semiconductor element has a capacitor structure in which a lower electrode layer 52, a ferroelectric thin film 53 made of a bismuth layered ferroelectric thin film, and an upper electrode layer 54 are laminated. The ferroelectric thin film 53 is made of Bi ₂ SrTa ₂
It is composed of an oxide film containing bismuth composed of O ₉ as a constituent element.

More specifically, this semiconductor device has a source / drain region 44 and a channel region 45 formed in a silicon semiconductor substrate 40, a gate electrode 43 formed above the channel region 45, and a LOCOS structure. And the gate oxide film 42 formed under the gate electrode 43. These source / drain region 44, channel region 45 and gate electrode 43
A so-called selection transistor is configured by.
The gate electrode 43 also serves as a word line.
It is composed of polysilicon, polycide, or metal silicide. Then, the source / drain region 44
The gate electrode 43 is covered with the insulating layer 50. The insulating layer 50 is made of BPSG, for example.

In the capacitor structure of this semiconductor element, the lower electrode layer 52 made of Pt (platinum) is used as the BPSG.
Is formed on the insulating layer 50. A ferroelectric thin film 53 made of Bi ₂ SrTa ₂ O _9, which is a bismuth layered ferroelectric thin film, is formed on the lower electrode layer 52. Further, an upper electrode layer 54 made of Pt is formed on the ferroelectric thin film 53.

An upper insulating layer 60 made of, for example, BPSG is formed on the insulating layer 50, the lower electrode layer 52 and the upper electrode layer 54.
Are formed. A contact plug 65 is formed in the insulating layer 50 and the upper insulating layer 60 above the one source / drain region 44 (for example, the source region), and the contact plug 65 has one source / drain at the bottom thereof. It is electrically connected to the region 44. A contact plug 66 is also formed on the upper insulating layer 60 above the lower electrode layer 52. The lower electrode layer 52 is electrically connected to one of the source / drain regions 44 via the contact plug 66, the first wiring layer 68, and the contact plug 65. The upper electrode layer 54 is electrically connected to the second wiring layer 69 via the contact plug 67 formed above the upper electrode layer 54. The second wiring layer 69 corresponds to a plate line.

The other source / drain region 44 (eg drain region) is electrically connected to a bit line (not shown) via a bit contact portion (not shown).

The method of manufacturing a semiconductor device according to the third embodiment will be described with reference to FIGS.
This will be described below with reference to FIG.

[Step-300] First, the element isolation region 41 having a LOCOS structure is formed on the silicon semiconductor substrate 40 by a known method. Next, the surface of the semiconductor substrate 40 is oxidized to form the gate oxide film 42. And
After depositing a polysilicon layer on the entire surface by, for example, a CVD method, the polysilicon layer is patterned by a photolithography technique and an etching technique to form a gate electrode 43 made of polysilicon. The gate electrode 4
3 also serves as a word line. Next, ion implantation of impurity ions and activation treatment of the implanted impurities are performed to form the source / drain regions 44 and the channel region 45.

[Step-310] Next, an insulating layer 50 (corresponding to a base) made of, for example, BPSG is formed on the semiconductor substrate 40 by the CVD method. Thus, FIG.
Can be obtained. After forming the insulating layer 50 made of BPSG, for example, 900 nm in a nitrogen gas atmosphere.
It is preferable to reflow the insulating layer 50 for 20 minutes at ° C. Further, if necessary, the top surface of the insulating layer 50 is chemically and mechanically polished by, for example, a chemical mechanical polishing method (CMP method) to flatten the insulating layer 50, or an etch back method is used. It is desirable to planarize the insulating layer 50. The film forming conditions of the insulating layer 50 are illustrated below. Gas used: SiH ₄ / PH ₃ / B ₂ H ₆ Film formation temperature: 400 ° C Reaction pressure: normal pressure

[Step-320] Next, the lower electrode layer 52 is formed on the insulating layer 50 corresponding to the base. That is, the lower electrode layer 52 made of Pt is deposited on the insulating layer 50 by the RF magnetron sputtering method. The thickness of the lower electrode layer 52 was set to 0.1 to 0.2 μm (see FIG. 4B).
After that, the lower electrode layer 52 is patterned into a desired shape by using, for example, an ion milling technique. The RF magnetron sputtering conditions are exemplified below. Anode voltage: 2.6 kV Input power: 1.1 to 1.6 W / cm ² Process gas: Ar / O ₂ = 90/10 Pressure: 0.7 Pa Film forming temperature: 600 to 750 ° C Deposition rate: 5 to 10 mm / Min

[Step-330] After that, the lower electrode layer 52 is formed.
A ferroelectric thin film 53 containing bismuth as a constituent element is formed on the above by a CVD method using a bismuth organometallic compound having a bismuth-oxygen bond as a raw material. Specifically, the bismuth layered ferroelectric layer is formed on the lower electrode layer 52 by the MOCVD method using tributoxybismuth as a source gas under the same conditions as the method for forming the ferroelectric thin film described in the second embodiment. A ferroelectric thin film 53 made of Bi ₂ SrTa ₂ O ₉ which is a dielectric thin film is formed (see FIG. 4C). The ferroelectric thin film 53 made of bismuth titanate may be formed by the same method as in [Step-420] of Embodiment 4 described later.

[Step-340] Then, the ferroelectric thin film 5
The upper electrode layer 54 is formed on the upper surface 3. The upper electrode layer 54 is P
and can be formed by the same method as in [Step-320].

[Step-350] Next, the upper electrode layer 54 made of Pt is patterned into a desired shape by using, for example, the ion milling technique, and further, the ferroelectric thin film 53 is patterned by the RIE method. Thus, the capacitor structure shown in FIG. 5A can be obtained.

[Step-360] Next, for example, BPSG is formed on the insulating layer 50, the lower electrode layer 52 and the upper electrode layer 54.
An upper insulating layer 60 of is formed. The upper insulating layer 6
After forming 0, the upper insulating layer 60 is preferably flattened. Then, the opening 61 is formed in the insulating layer 50 and the upper insulating layer 60 above the one source / drain region 44 by using the photolithography technique and the etching technique. Further, openings 62 and 63 are formed in the upper insulating layer 60 above the lower electrode layer 52 and above the upper electrode layer 54 (see FIG. 5B).

[Step-370] Then, the openings 61,
On the upper insulating layer 60 including the insides of 62 and 63, for example, Ti
After the TiN layer and the TiN layer are formed by the sputtering method, the wiring material layer 64 made of an aluminum alloy (for example, Al-1% Si) is formed on the TiN layer by the so-called high temperature aluminum sputtering method (see FIG. 6). . The film forming conditions for the Ti layer, the TiN layer, and the wiring material layer made of an aluminum alloy are illustrated below. The reason for forming the Ti layer and the TiN layer is as follows.
This is for obtaining an ohmic low contact resistance, preventing damage to the semiconductor substrate 40 due to the wiring material layer made of an aluminum alloy, and improving wettability of the aluminum alloy. Ti layer (thickness: 20 nm) Process gas: Ar = 35 sccm Pressure: 0.52 Pa RF power: 2 kW Substrate heating: None TiN layer (thickness: 100 nm) Process gas: N ₂ / Ar = 100/35 sccm Pressure: 1 0.0Pa RF power: 6kW Substrate heating: None Wiring material layer made of aluminum alloy Process gas: Ar = 100sccm Pressure: 0.26Pa RF power: 15kW Substrate heating temperature: 475 ° C

Thus, in the openings 61, 62, 63,
Aluminum-based alloy embedded, contact plug 6
5, 66, 67 are formed (see FIG. 6). The TiN layer and the Ti layer are not shown in FIGS. 3 and 6. After that, the wiring material layer 64, T on the upper insulating layer 60,
The first wiring layer 6 is formed by patterning the iN layer and the Ti layer.
8, the second wiring layer 69 is formed (see FIG. 3A).

The wiring material layer made of an aluminum alloy was formed by a so-called high temperature aluminum sputtering method.
The method is not limited to such a film forming method, and may be a so-called high temperature reflow method or high pressure reflow method.
In the high temperature reflow method, a wiring material layer made of an aluminum alloy is deposited on the upper insulating layer 60 under the conditions exemplified below. Process gas: Ar = 100 sccm DC power: 20 kW Sputtering pressure: 0.4 Pa Substrate heating temperature: 150 ° C.

After that, the semiconductor substrate 40 is heated to about 500.degree. As a result, the wiring material layer made of an aluminum-based alloy deposited on the upper insulating layer 60 is brought into a fluid state, flows into the openings 61, 62, 63, and the opening 6
1, 62 and 63 are surely filled with an aluminum alloy to form contact plugs 65, 66 and 67.
On the other hand, a wiring material layer made of an aluminum alloy is left on the upper insulating layer 60. The heating conditions can be set as follows, for example. Heating method: Substrate backside gas heating Heating temperature: 500 ° C Heating time: 2 minutes Process gas: Ar = 100 sccm Process gas pressure: 1.1 × 10 ³ Pa

Here, the substrate backside gas heating method is to heat a heater block arranged on the backside of the semiconductor substrate 40 to a predetermined temperature (heating temperature), and to supply process gas between the heater block and the backside of the semiconductor substrate 40. This is a method of heating the semiconductor substrate 40 by introducing it. As the heating method, other than this method, a lamp heating method or the like can be used.

A high pressure reflow method may be used instead of the high temperature reflow method. In this case, the reflow process is performed under the conditions exemplified below. Substrate heating temperature: 400 ° C Heating time: 2 minutes Heating atmosphere: Argon gas Atmospheric pressure: 10 ⁶ Pa or more

In the third embodiment, the lower electrode layer is made of P
Instead of being composed of t, for example, La-Sr-Co-O (LSCO) having a perovskite structure may be used alone or may be composed of two layers of LSCO / Pt from the bottom. The LSCO film forming conditions by the pulse laser ablation method in this case are illustrated below. Target: LSCO Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Film formation temperature: 550 to 600 ° C Oxygen partial pressure: 40 to 120 Pa

(Embodiment 4) Embodiment 4 relates to a method for forming an oxide film and a method for manufacturing a capacitor structure of a semiconductor device according to the present invention.

In the non-volatile memory cell of the type which detects the change in the accumulated charge amount of the ferroelectric capacitor, the residual polarization ± P _r of the ferroelectric thin film is set high and the residual polarization ± P _r is high. How to maintain is a very important technical issue. By increasing the remanent polarization ± P _r of the ferroelectric thin film, it is possible to more easily and reliably detect which data, "0" or "1", the semiconductor memory cell holds. become. For that purpose, it is necessary to epitaxially grow the ferroelectric thin film on the lower electrode layer.

When the lower electrode layer 52 is composed of Pt (100), the lattice plane spacing of Pt (100) is, for example, B
i ₂ SrTa ₂ O ₉ , Bi ₄ SrTi ₄ O ₁₅ , Bi ₂ SrTi
It matches the lattice plane spacing of ₂ O ₉ or the like. Therefore, Pt (1
These ferroelectric materials can be epitaxially grown on (00) and the remanent polarization ± P _r of these ferroelectric thin films formed on Pt (100) can be increased. However, Pt (100)
It cannot be formed on the insulating layer 50 made of an amorphous material such as G. Therefore, there is a problem that the remanent polarization ± P _r of these ferroelectric thin films cannot be increased.

For example, the document "Ferroelectric La-Sr-Co-O"
/ Pb-Zr-Ti-O / La-Sr-Co-O heterostructure on silicon
via template growth ", R. Ramesh, et al., Appl. Phy
s. Lett. 63 (26), 27 December 1993, pp. 3592-3594
(Hereinafter referred to as Reference 2), reference "Template Approaches"
to Growth of Oriented Oxide Heterostructures on SiO
₂ / Si ", Journal Of Electronic Materials, Vol. 23, N
o. 1, 1994, pp. 19-23 (hereinafter referred to as reference 3),
Yttrium (Y) -added stabilized zirconia (hereinafter abbreviated as YSZ) on a silicon substrate or SiO ₂ formed on the silicon substrate, and bismuth titanate (BTO) having a perovskite structure oriented along the c-axis. )
Disclosed is a ferroelectric capacitor composed of a template layer made of, a lower electrode layer made of La-Sr-Co-O (LSCO) having a perovskite structure, a ferroelectric thin film made of PLZT, and an upper electrode layer made of LSCO. ing. When the template layer made of BTO is not provided, that is, LSCO / directly on YSZ or SiO _2.
When PLZT / LSCO is formed, LSCO / PLZ
T / LSCO has a [110] orientation, and in this state P
LZT exhibits low remanent polarization. However, when a template layer made of BTO is formed, LSCO / PL
ZT / LSCO has a [001] orientation, and in this state PLZT exhibits a high remanent polarization.

The resistivity of the LSCO, which is the material forming the lower electrode shown in Documents 2 and 3, is as high as 90 to 200 μΩcm at room temperature, and the material having the lowest resistivity, for example, Pt. It is preferable to form the lower electrode from {100}. The lattice constant of BTO is
a = 5.41 angstrom, b = 5.43 angstrom, and c = 32.82 angstrom. Further, platinum Pt has a face-centered cubic structure, and the lattice constant is a =
b = c = 3.92 angstrom. That is, BT
The (110) lattice spacing of O is almost equal to the lattice spacing of Pt {100}. Therefore, P is formed on the template layer (hereinafter referred to as a buffer layer) made of BTO oriented in the c-axis.
If a lower electrode layer made of t is formed, the lower electrode layer is Pt.
It may be composed of {100}.

The lattice constants (unit: angstrom) and the (110) lattice spacing (unit: angstrom) of the a-axis and the b-axis of the Bi-based layered structure perovskite-type ferroelectric material are exemplified below. Is Pt {1
00} is almost the same as the lattice spacing.

[0059]

[Table 2] Ferroelectric material name Lattice constant Lattice spacing Bi ₂ SrTa ₂ O ₉ 5.512 3.898 Bi ₂ SrNb ₂ O ₉ 5.500 3.889 Bi ₂ BaTa ₂ O ₉ 5.556 3.929 Bi ₄ SrTi ₄ O ₁₅ 5.420 3.833

Generally, if the difference between the lattice spacing of the lower electrode layer made of Pt {100} and the lattice spacing of the material forming the ferroelectric thin film is within 3%, the ferroelectric thin film is formed on the lower electrode layer. Can be epitaxially grown. Therefore, a ferroelectric thin film made of a Bi-based layered structure perovskite type ferroelectric material can be epitaxially grown on the lower electrode layer made of Pt {100}. As a result, a high residual polarization ± P _r can be imparted to the ferroelectric thin film formed on the lower electrode layer, and a semiconductor element having excellent performance can be manufactured.

The resistivity of platinum is 15 to 20 μΩc.
m, which has a lower resistance than LSCO, and is a preferable material for semiconductor devices.

In the semiconductor element described in the third embodiment, the lower electrode layer 52 made of Pt is formed on the insulating layer 50 corresponding to the base. On the other hand, in the fourth embodiment, the semiconductor element has a capacitor structure in which the lower electrode layer 52, the Bi-based layered structure perovskite type ferroelectric thin film 53 and the upper electrode layer 54 are laminated, and the lower electrode layer 52. There is a Bi-based layered structure perovskite type buffer layer 51 (corresponding to the substrate) formed underneath, and the buffer layer 51 is composed of an oxide film containing bismuth as a constituent element. FIG. 8B shows a schematic partial cross-sectional view of a semiconductor element manufactured based on the method for forming the capacitor structure of the semiconductor element according to the fourth embodiment.

More specifically, in the capacitor structure of the semiconductor device of the fourth embodiment, buffer layer 51 serving as a base layer is formed on insulating layer 50 made of BPSG. The buffer layer 51 is composed of an oxide film of Bi-based layered structure perovskite type Bi ₄ Ti ₃ O ₁₂ (BTO) oriented in the c-axis. Furthermore, Pt {10
0} of lower electrode layer 52 is formed on the buffer layer 51. Further, the ferroelectric thin film 53 formed on the lower electrode layer 52 by epitaxial growth is made of Bi ₂ SrTa ₂ O ₉ also in the fourth embodiment. Further, P
An upper electrode layer 54 made of t {100} is formed on the ferroelectric thin film 53. Except for these points, the structure of the semiconductor device of the fourth embodiment is substantially the same as the structure of the semiconductor device of the third embodiment. FIG. 7 is a schematic partial cross-sectional view of a semiconductor substrate or the like showing a method for manufacturing a semiconductor element including a method for forming a capacitor structure for a semiconductor element according to a fourth embodiment.
This will be described below with reference to FIG.

[Step-400] First, as in the case of [Step-300] of the third embodiment, the element isolation region 41, the gate oxide film 42, and the gate are formed on the semiconductor substrate 40 made of a silicon semiconductor substrate by a known method. An electrode 43, a source / drain region 44 and a channel region 45 are formed.

[Step-410] Next, as in [Step-310] of the third embodiment, the insulating layer 50 made of an amorphous material is formed on the semiconductor substrate 40. That is, for example, the insulating layer 50 made of BPSG which is an amorphous material.
Is deposited on the entire surface by, for example, the CVD method. Thus, the structure shown in FIG. 7A can be obtained.

[Step-420] Next, on the insulating layer 50,
A buffer layer 51 (corresponding to a substrate) which is an oxide film containing bismuth as a constituent element by a CVD method using a bismuth organometallic compound having a bismuth-oxygen bond as a raw material.
To form Specifically, according to the oxide film forming method described below, the buffer layer 5 made of bismuth titanate Bi ₄ Ti ₃ O ₁₂ and having high orientation (that is, c-axis oriented) is used.
1 is deposited on the insulating layer 50 (see FIG. 7B). The thickness of the buffer layer 51 was 0.01 to 0.02 μm.

As shown in FIG. 1, when forming the buffer layer 51, the raw material container 10 is filled with tributoxy bismuth, and the tributoxy bismuth in the raw material container 10 is adjusted to 80 to 80%.
Heat to 110 ° C. Argon gas having a flow rate of 50 to 100 cc is introduced into the raw material container 10 to sublimate tributoxybismuth under heating and reduced pressure. Then, the vaporized tributoxybismuth is sent to the MOCVD reaction chamber 20 through the pipe 14 maintained at about 110 ° C.

On the other hand, tetraisopropoxy titanium is filled in the raw material container 12 and the tetraisopropoxy titanium in the raw material container 12 is heated to about 40 ° C. Argon gas having a flow rate of 50 cc is introduced into the raw material container 12, and tetraisopropoxytitanium, which is liquid under heating and reduced pressure, is bubbled. Then, vaporized tetraisopropoxy titanium is introduced into the pipe 15 kept at about 80 ° C.
To the MOCVD reaction chamber 20 via.

The substrate 30 placed on the substrate stage in the MOCVD reaction chamber 20 is heated to 400 to 800 ° C.
When gaseous tributoxybismuth, gaseous tetraisopropoxytitanium gas, oxygen gas and diluting argon gas are introduced into the MOCVD reaction chamber 20, bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ) is formed on the substrate 30. An oxide film of is formed. That is, bismuth titanate (Bi ₄ T
A buffer layer 51 (corresponding to the substrate) made of i ₃ O ₁₂ ) and having a high orientation (that is, oriented to the c-axis) can be formed on the insulating layer 50.

The buffer layer 51 may be made of Bi ₂ SrTa ₂ O ₉ formed by the same method as in the second embodiment.

[Step-430] Then, the buffer layer 51
A lower electrode layer 52 is formed on top. That is, the buffer layer 51
A lower electrode layer 52 made of Pt and having a high orientation is deposited thereon by RF magnetron sputtering. The thickness of the lower electrode layer 52 was set to 0.1 to 0.2 μm. The RF magnetron sputtering conditions are [Step-32 of Embodiment 3].
0]. The lower electrode layer 52 made of Pt has a {100} plane. In other words, the {100} plane of platinum Pt forming the lower electrode layer 52 is formed parallel to the surface of the buffer layer 51.

After that, the lower electrode layer 52 is patterned into a desired shape by using, for example, an ion milling technique, and further, the buffer layer 51 which is an oxide film made of BTO is patterned into a desired shape by, for example, the RIE method ( Figure 7
(See (C)).

It is also possible to form the lower electrode layer made of Pt {100} by the pulse laser deposition method. The film forming conditions of Pt {100} by the pulse laser deposition method are illustrated below. Film forming conditions by pulsed laser deposition method Target: Pt Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 5 Hz, 1.1 J / cm ² ) Film formation temperature: 500 to 600 ° C

[Step-440] Next, the lower electrode layer 52.
In the same manner as in the second embodiment, Bi ₂ SrTa ₂ O is added to the above.
_A ferroelectric thin film 53 made of ₉ is epitaxially grown. A ferroelectric thin film 53 made of Bi ₂ SrTa ₂ O ₉ epitaxially grown on the surface of the lower electrode layer 52.
The azimuth is [110].

In the same manner as in [Step-420], the MOCVD method using tributoxybismuth as a raw material gas
On the lower electrode layer 52, a ferroelectric thin film made of Bi-based layered structure perovskite type Bi ₄ Ti ₃ O ₁₂ (BTO) may be formed.

Furthermore, a ferroelectric thin film made of PZT is
It is also possible to epitaxially grow on the lower electrode layer 52 by a magnetron sputtering method. The film forming conditions are exemplified below. The ferroelectric thin film made of PZT has a (100) plane. In other words, the orientation of the epitaxially grown PZT ferroelectric thin film with respect to the surface of the lower electrode layer 52 is [100]. The target is PLZT
By exchanging with, the ferroelectric thin film made of PLZT can be epitaxially grown on the lower electrode layer 52. Target: PZT process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Film formation temperature: 500 ° C Thickness of ferroelectric thin film: 0.1-0.3 μm

Alternatively, a ferroelectric thin film made of PZT or PLZT can be formed by the pulse laser ablation method. The film forming conditions in this case are exemplified below. Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Film formation temperature: 550 to 600 ° C Oxygen partial pressure: 40 to 120 Pa

Alternatively, the ferroelectric thin film is made of Bi ₂ SrT.
It can also be formed of a ₂ O ₉ and formed by a pulse laser ablation method. The film forming conditions for the ferroelectric thin film made of Bi ₂ SrTa ₂ O ₉ will be illustrated below. In addition, Bi ₂ S
After the film formation of rTa ₂ O ₉ , it is desirable to carry out post-baking in an oxygen atmosphere at 800 ° C. for 1 hour. Target: Bi ₂ SrTa ₂ O ₉ Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25nsec, 5Hz) Film formation temperature: 500 ° C Oxygen partial pressure: 3Pa

[Step-450] After that, the ferroelectric thin film 5
The upper electrode layer 54 is formed on the upper surface 3. The upper electrode layer 54 is P
t {100}, and [Process-32 of the third embodiment.
0] can be used to form a film.

[Step-460] Next, the upper electrode layer 54 made of Pt is patterned into a desired shape by using, for example, an ion milling technique, and further, the ferroelectric thin film 5 is formed by RIE.
3 is patterned. Thus, the capacitor structure of the semiconductor element having the structure shown in FIG. 8A can be obtained.

[Step-470] After that, through steps similar to [Step-360] and [Step-370] of the third embodiment, a semiconductor element having the structure shown in FIG. 8B is manufactured. be able to.

In the fourth embodiment, the buffer layer 5
1 and the insulating layer 50, for example, yttrium oxide Y ₂
Stabilized zirconia (YSZ) which is zirconium oxide ZrO ₂ with O ₃ added may be formed. Such an underlayer can be formed by, for example, the MOCVD method or the pulse laser deposition method whose film forming conditions are exemplified below. Deposition conditions source material by _{MOCVD: Zr (C 4 H 9 O} ) 4 Y (C 11 H 19 O 2) 3 deposition temperature: 550 to 650 ° C deposition pressure: 27～400Pa oxygen concentration: 50% Pulse Film forming conditions by laser deposition method Target: ZrO ₂ / Y Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 5 Hz, 1.1 J / cm ² ) Film formation temperature: 500 ° C Oxygen partial pressure: 3 Pa

(Embodiment 5) In Embodiment 5, a bismuth-organic metal compound having a bismuth-oxygen bond is used as a raw material and a superconductor thin film made of an oxide film containing bismuth as a constituent element is formed by a CVD method. The present invention relates to a method for forming an oxide film formed thereover. The oxide film is Bi-Sr-Ca-
It is a Cu-O system.

In the fifth embodiment, the MOCVD apparatus described in the first embodiment is used and Si (1
00) is used. Raw material gases in the MOCVD method are shown below. Bi source: tributoxy bismuth [Bi (OC (CH ₃ ) ₃ ) ₃ ] Sr source: Sr (C ₁₁ H ₁₉ O ₂ ) ₂ [Sr (tmhd) ₂ ] Ca source: Ca (C ₁₁ H ₁₉ O ₂ ). ₂ [Ca (tmhd) ₂ ] Cu source: Cu (C ₅ H ₇ O ₂ ) ₂ [Cu (acac) ₂ ]

Each raw material is heated to an appropriate temperature in a raw material container, placed on a substrate stage 22 in the MOCVD reaction chamber 20 and heated to an appropriate temperature on a substrate 30 made of Si (100). By introducing the Ar carrier gas, oxygen gas, and each of the above-mentioned source gases, a superconductor thin film made of a Bi—Sr—Ca—Cu—O-based oxide film can be formed on the substrate 30.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments.

As source materials for Sr, Ba and Ca,
Sr (C ₁₁ H ₁₉ O ₂ ) ₂ [dis (tetramethylheptanedione) strontium], Ba (C ₁₁ H ₁₉ O ₂ ) ₂ [dis (tetramethylheptanedione) barium] and Ca
(C ₁₁ H ₁₉ O ₂ ) ₂ [dis (tetramethylheptanedione) calcium] is used as a source material for Ta and Nb, Ta (OC ₂ H ₅ ) ₅ [pentaethoxytantalum], Nb (OC ₂ H ₅ ) ₅ [pentaethoxyniobium], Bi ₂ AB ₂ O ₉ (where A is one element selected from the group consisting of Sr, Ba and Ca, and B is a group consisting of Ta and Nb) An oxide film composed of a Y1-based material consisting of one element selected from
The film can be formed on the substrate by the CVD method. As the combination of elements A / B, not only Sr / Ta but also S
r / Nb, Ba / Ta, Ba / Nb, Ca / Ta, Ca
/ Nb can be mentioned.

The structure of the semiconductor element described in the manufacturing method of the capacitor structure of the semiconductor element of the present invention is an example, and the design can be appropriately changed. For example, the upper electrode layer may also serve as a plate line. That is, in the capacitor structure of the semiconductor device having such a structure, [Step-330] of the third embodiment.
After forming the ferroelectric thin film 53 in FIG.
3 is patterned into a desired shape. Next, after forming the upper insulating layer 60 on the entire surface, the opening 61 is formed in the insulating layer 50 and the upper insulating layer 60, and the opening 62 is formed in the upper insulating layer 60 above the lower electrode layer 52. Then, Ti is sequentially formed on the upper insulating layer 60 including the insides of the openings 61 and 62.
Layer, a TiN layer, and a wiring material layer made of an aluminum alloy. After that, the wiring material layer, the TiN layer, and the Ti layer on the upper insulating layer 60 are patterned to form the first wiring layer 6 made of a wiring material layer made of an aluminum alloy or the like.
8 is formed (see FIG. 9A). After that, the second insulating layer 70 made of, for example, BPSG is formed on the entire surface. The upper insulating layer 60 above the ferroelectric thin film 53 and the second
The opening 71 is formed in the insulating layer 70, and then a Pt film is formed on the second insulating layer 70 including the inside of the opening 71 as in [Step-340] of the third embodiment. After that, the Pt film is left in the opening 71, and Pt on the second insulating layer 70 is left.
Pattern the film. As a result, the ferroelectric thin film 5
An upper electrode layer 54A made of Pt is formed on top of No. 3.
Moreover, the upper electrode layer 54A extends over the second insulating layer 70 through the opening 71 to form the second wiring layer 69A and also functions as a plate line (see FIG. 9B). . The upper electrode layer 54A and the second wiring layer 69A may be made of an aluminum alloy.

Element isolation region 41 having LOCOS structure
Alternatively, the element isolation region may have a trench structure. The gate electrode 43 and the bit line may be made of polycide or metal silicide instead of being made of a polysilicon layer. As an insulating layer, instead of BPSG, SiO ₂ , PSG, BSG, AsSG, PbS
G, SbSG, SOG, SiON, SiN, NSG, L
A known insulating material such as TO or a laminated material of these insulating materials can be given. The insulating layer may be smoothed by, for example, a resist etch back method. The ferroelectric thin film may have a structure in which a plurality of ferroelectric materials are laminated.

In the [Step-370] of the third embodiment or the [Step-470] of the fourth embodiment, the aluminum-based alloy is embedded in the openings 61 formed in the insulating layer 50 and the upper insulating layer 60 to form a contact. Instead of forming the plug 65, the contact plug 65A can be formed by a so-called blanket tungsten CVD method. For that purpose, after forming the openings 61 in the insulating layer 50 and the upper insulating layer 60, [Step-37 of the third embodiment is performed.
0], a Ti layer and a TiN layer are formed by a sputtering method. After that, the wiring material layer 64A made of tungsten is deposited on the TiN layer by the CVD method under the conditions exemplified below (see FIG. 10A). Gas used: WF ₆ / H ₂ / Ar = 40/400/2250 sccm Pressure: 10.7 kPa Film formation temperature: 450 ° C

After that, the wiring material layer 64A made of tungsten, the TiN layer and the Ti layer on the insulating layer 50 are removed by etching (see FIG. 10B). The etching conditions can be set as follows, for example. First-stage etching: Tungsten layer etching Working gas: SF ₆ / Ar / He = 110/90/5 sccm Pressure: 46 Pa RF power: 275 W Second-stage etching: TiN layer / Ti layer etching Working gas: Ar / Cl ₂ = 75/5 sccm Pressure: 6.5 Pa RF power: 250 W

In this way, the contact plug 65A in which tungsten is embedded in the opening 61 is formed. After that, openings are formed in the upper insulating layer 60 above the lower electrode layer 52 and above the upper electrode layer 54, and then, similarly to [Step-370] of the third embodiment, a Ti layer, a TiN layer,
After forming a wiring material layer made of an aluminum alloy by a sputtering method, each of these layers is patterned to form a first wiring layer 68 and a second wiring layer 69 (see FIG. 11). The contact plug 65A may be formed by filling the opening 61 with polysilicon doped with impurities.

Alternatively, the insulating layer 50 and the upper insulating layer 6
An opening 61 is formed at 0, and an opening 62 is formed in the upper insulating layer 60 above the lower electrode layer 52. Then the opening 6
1, 62 on the upper insulating layer 60 including the inside,
A wiring material layer 64A made of a TiN layer and tungsten is formed. Then, the wiring material layer 64A made of tungsten, the TiN layer, and the Ti layer on the upper insulating layer 60 are patterned to form the first wiring layer 6 made of the wiring material layer 64A and the like.
8A is formed and, in addition, contact plugs 65A and 66 are formed.
A may be formed. After that, an opening 63 is formed in the upper insulating layer 60 above the upper electrode layer 54, and then a Ti layer and a TiN layer are formed in the same manner as in [Step-360] of the third embodiment.
After forming a layer and a wiring material layer made of an aluminum alloy by a sputtering method, these layers are patterned to form the second wiring layer 69. In this way, the structure shown in FIG. 12 can be obtained.

Further, after the contact plug 65A is formed on the insulating layer 50 by, for example, the blanket tungsten CVD method, the contact plug 65A is formed on the insulating layer 50 by the same method as in [Step-320] of the third embodiment. You may form the lower electrode layer 52 connected with. After that, [Step-330], [Step-340], and [Step-350] of the third embodiment are executed. Next, the upper insulating layer 60 made of, for example, BPSG is formed on the insulating layer 50 and the upper electrode layer 54. Then, after forming an opening in the upper insulating layer 60 above the upper electrode layer 54, a contact plug 67 is formed in the opening by the same method as in [Step-370] of the third embodiment, and the upper insulating layer is formed. A wiring layer 69B is formed on 60. Thus, the semiconductor element having the structure shown in FIG. 13 can be obtained.

Examples of aluminum alloys include pure aluminum, Al-Si, Al-Cu, and Al-Si-C.
It can be composed of various aluminum alloys such as u, Al-Ge and Al-Si-Ge. Alternatively, instead of the aluminum alloy, polysilicon, titanium, titanium alloy, copper, copper alloy, tungsten, or tungsten alloy can be used to form the first or second wiring layer. Although the underlying layer of the contact plug has a two-layer structure of Ti / TiN in the embodiment, it may have a one-layer structure of Ti or TiN in some cases. Further, the contact plugs are TiW, TiNW, W
It can also be made of Si ₂ , MoSi _2, or the like.

Further, instead of the ferroelectric thin film electrically connected to one source / drain region via the contact plug and the first wiring layer, it is electrically connected to one source / drain region. A wiring electrically connected to the contact plug is provided, another connection hole (for example, a via hole) electrically connected to the wiring is formed, and the ferroelectric thin film is electrically connected to the connection hole. It may be connected. Alternatively, a capacitor structure in a semiconductor device can be formed by forming a lower electrode layer or a buffer layer on the device isolation region.
In this case, the element isolation region or the buffer layer corresponds to the base.

The bit line can be formed, for example, by the following method. That is, [Step-30 of the third embodiment
0] and [Step-310], a lower insulating layer is formed, and an opening is formed in the lower insulating layer above the other source / drain region 44 by using a photolithography technique and an etching technique. Then, a polysilicon layer is deposited on the lower insulating layer including the inside of the opening by, for example, the CVD method. As a result, a bit contact portion in which polysilicon is embedded in the opening is formed. Then, the polysilicon layer on the lower insulating layer is patterned. Thus, a bit line made of polysilicon electrically connected to the other source / drain region 44 through the bit contact portion is formed. After that, the insulating layer 50 is formed on the lower insulating layer including the bit line. The procedure for forming the bit line is arbitrary. For example, the bit line can be formed after forming the second wiring layer.

As a semiconductor element, not only a non-volatile memory cell using a ferroelectric thin film (so-called FERAM) but also
A DRAM can also be configured. In this case, only the polarization of the ferroelectric thin film is used. That is, the characteristic that the difference (P _max −P _r ) between the maximum (saturation) polarization P _{max due} to the external electrode and the remnant polarization P _r when the external electrode is 0 has a constant proportional relationship with the power supply voltage To do. Polarization of the ferroelectric thin film is always located between the saturation polarization (P _max) and the residual polarization (P _r), not inverted. Data is held by refresh.

[0099]

In the present invention, by using a bismuth-organic metal compound having a bismuth-oxygen bond as a source material in the CVD method, the heating temperature of the material container can be lowered to 80 to 110 ° C. There is little loss due to decomposition due to heating over time, and a wide temperature range (400 to 800 ° C) and a wide pressure range (0.5
The film can be formed at a pressure of up to 20 torr. In addition, the required heating temperature of the raw material container and the required heating temperature of the pipe can be lowered, and maintenance and management of the entire CVD apparatus can be facilitated. This makes it possible to form and manufacture a high-quality oxide film, a ferroelectric thin film, or a capacitor structure of a semiconductor element. Moreover, unlike the case of using triphenylbismuth which is a conventional material, it is possible to form a film of bismuth oxide on a silicon semiconductor substrate or SiO ₂ .

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of an MOCVD apparatus suitable for carrying out the method of the present invention.

FIG. 2 is a Y1-based material (Bi ₂ SrTa ₂ O ₉ ) formed using tributoxybismuth and triphenylbismuth.
3 is a graph showing film formation characteristics of an oxide film made of.

3A and 3B are a schematic partial cross-sectional view and an equivalent circuit diagram of a semiconductor element manufactured by a method for manufacturing a capacitor structure of a semiconductor element according to a third embodiment.

FIG. 4 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure for a semiconductor element according to a third embodiment.

5 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure for a semiconductor element according to a third embodiment, which is subsequent to FIG. 4;

6 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure for a semiconductor element according to a third embodiment, which is subsequent to FIG. 5;

FIG. 7 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure for a semiconductor element according to a fourth embodiment.

FIG. 8 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure for a semiconductor element according to a fourth embodiment, following FIG. 7;

FIG. 9 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure according to the present invention.

FIG. 10 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure according to the present invention.

11 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure according to the present invention, following FIG. 10;

FIG. 12 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure according to the present invention.

FIG. 13 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor element including a method for manufacturing a capacitor structure according to the present invention.

FIG. 14 is a PE hysteresis loop diagram of a ferroelectric substance.

[Explanation of symbols]

10, 12 ... Raw material container, 11, 13 ... Constant temperature bath,
14, 15 ... Piping, 20 ... MOCVD reaction chamber,
22 ... Base stage, 30 ... Base, 40 ...
Semiconductor substrate, 41 ... Element isolation region, 42 ... Gate oxide film, 43 ... Gate electrode, 44 ... Source
Drain region, 45 ... channel region, 50 ... insulating layer, 51 ... buffer layer, 52 ... lower electrode layer,
53 ... Ferroelectric layer, 54, 54A ... Upper electrode layer, 60 ... Upper insulating layer, 61, 62, 63, 71.
..Openings, 64, 64A ... Wiring material layers, 65, 6
5A, 66, 66A, 67 ... Contact plug, 6
8, 68A ... first wiring layer, 69,69A ... second wiring layer, 70 ... second insulating layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/8242 H01L 29/78 371 21/8247 29/788 29/792 // H01L 21/316 ( 72) Inventor Takaaki Ami 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (9)

[Claims] 1. A method for producing bismuth oxide, characterized in that bismuth oxide is produced by a CVD method using a bismuth organometallic compound having a bismuth-oxygen bond as a raw material. 2. A method for forming an oxide film, which comprises forming an oxide film containing bismuth as a constituent element by a CVD method using a bismuth organometallic compound having a bismuth-oxygen bond as a raw material. 3. The oxide film is made of a Bi-based layered structure perovskite type ferroelectric material.
The method for forming an oxide film according to item 1. 4. The Y1-based material (Bi ₂ (Sr,
The method for forming an oxide film according to claim 3, wherein the oxide film is formed of Ba, Ca) (Ta, Nb) ₂ O ₉ ). 5. The method for forming an oxide film according to claim 4, wherein the Y1-based material is Bi ₂ SrTa ₂ O ₉ . 6. (a) a step of forming a lower electrode layer on a substrate; and (b) a bismuth organometallic compound having a bismuth-oxygen bond is used as a raw material on the lower electrode layer to form bismuth by a CVD method. A step of forming a ferroelectric thin film containing as a constituent element, (c) a step of forming an upper electrode layer on the ferroelectric thin film,
A method of manufacturing a capacitor structure of a semiconductor device, comprising: 7. The method for manufacturing a capacitor structure of a semiconductor device according to claim 6, wherein the ferroelectric thin film is made of a Bi-based layered structure perovskite type ferroelectric material. 8. A ferroelectric thin film is formed of a Y1-based material (Bi ₂ (S
r, Ba, Ca) (Ta , Nb) method of fabricating a capacitor structure of a semiconductor device according to claim 7, characterized in that it consists of ₂ O _9). 9. The method for manufacturing a capacitor structure of a semiconductor device according to claim 8, wherein the Y1 material is Bi ₂ SrTa ₂ O ₉ .