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JPH09199650A - Method for manufacturing lead material for semiconductor - Google Patents
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JPH09199650A - Method for manufacturing lead material for semiconductor - Google Patents

Method for manufacturing lead material for semiconductor

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Publication number
JPH09199650A
JPH09199650A JP8004007A JP400796A JPH09199650A JP H09199650 A JPH09199650 A JP H09199650A JP 8004007 A JP8004007 A JP 8004007A JP 400796 A JP400796 A JP 400796A JP H09199650 A JPH09199650 A JP H09199650A
Authority
JP
Japan
Prior art keywords
work roll
work
semiconductor
work rolls
roll surfaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8004007A
Other languages
Japanese (ja)
Other versions
JP2869031B2 (en
Inventor
Yoji Mitani
洋二 三谷
Teruo Kusano
照雄 草野
Hisashi Yamamoto
尚志 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP8004007A priority Critical patent/JP2869031B2/en
Publication of JPH09199650A publication Critical patent/JPH09199650A/en
Application granted granted Critical
Publication of JP2869031B2 publication Critical patent/JP2869031B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a lead material for semiconductor with small internal residue stress and improved etching processability. SOLUTION: A metal line material after finishing temper rolling is passed between two work roll surfaces 20 where a work roll 10 of a multi roller tension leveler is arranged flatly for calibration. In this case, equations regarding a tilt angle (an inclination angle between two work roll surfaces) θ of the above work roll surface 20, an amount of out-side intermesh (out-side interval between two work roll surfaces) D, and a unit tension T applied to the metal line material can be met, namely 60>=K>=-60, 1.0deg>=θ×L/250>=0.1deg, 60N/mm<2> >=T>=10 N/mm<2> , where K=85.6×D (mm)+470.1×θ(deg)×L/250+3.7×T(N/mm2)-277.2, L: distance (mm) between in-side and out-side work rolls, work roll diameter: 10-20mm, the number of work rolls (both sides): 5-25.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、内部残留応力が小
さくエッチング加工性に優れた半導体用リード材の製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor lead material having a small internal residual stress and excellent etching processability.

【0002】[0002]

【従来の技術】半導体用リード材(リードフレーム等)
には、一般に銅合金や42アロイ等が用いられている。
前記半導体用リード材は、例えば、銅合金鋳塊を熱間圧
延後、面削し、次いで冷間圧延と中間焼鈍を繰返したの
ち、仕上げ調質圧延により所望の板厚に仕上げ、次いで
テンションレベラーを掛けて形状を修正し、次いでプレ
ス又はエッチング加工により所定形状に加工して製造さ
れる。エッチング加工の際、ダイパット部(半導体チッ
プを接合する箇所)にディンプルを形成して半導体チッ
プの接合性を高めるようにしている。
2. Description of the Related Art Lead materials for semiconductors (lead frames, etc.)
In general, copper alloy, 42 alloy, etc. are used.
The lead material for semiconductors is, for example, hot-rolling a copper alloy ingot, chamfering it, then repeating cold rolling and intermediate annealing, and then finishing temper rolling to finish it to a desired plate thickness, and then a tension leveler. Is applied to correct the shape, and then it is manufactured by pressing or etching into a predetermined shape. During the etching process, dimples are formed in the die pad portion (the portion where the semiconductor chips are joined) to enhance the joining property of the semiconductor chips.

【0003】ところで、前記テンションレベラーには、
例えば図1に示すような、複数のワークロール10を平面
状に配したワークロール面20を有する2個のロール群30
を、前記ワークロール面20を対向配置させて構成したマ
ルチローラテンションレベラーが用いられている。前記
ワークロール面20間は、入側から出側にかけて間隔が広
がるように構成されている。整直しようとする金属条材
は、前記ワークロール面20間を通過する際にワークロー
ル面20を形成する個々のワークロール10により繰返し曲
げ加工を受けて矯正される。ここで、ワークロール10の
径は10〜20mm、その本数は両側で5〜25本が一般的であ
る。また条材の形状をより良好に矯正する為に、金属条
材が入る側のワークロール面20間隔(以下、入側インタ
ーメッシュ量Eと称す、図2参照)は 3.0mm以上に大き
くし、金属条材に掛ける単位面積当たりの張力(以下、
ユニット張力Tと称す)も100N/mm2以上に大きくしてい
る。
By the way, the tension leveler has
For example, as shown in FIG. 1, two roll groups 30 each having a work roll surface 20 in which a plurality of work rolls 10 are arranged in a plane.
A multi-roller tension leveler configured by arranging the work roll surfaces 20 to face each other is used. The space between the work roll surfaces 20 is configured to widen from the entrance side to the exit side. The metal strip to be straightened is repeatedly bent and corrected by the individual work rolls 10 forming the work roll surface 20 when passing between the work roll surfaces 20. Here, the diameter of the work roll 10 is generally 10 to 20 mm, and the number thereof is generally 5 to 25 on both sides. Also, in order to better correct the shape of the strip material, the interval between the work roll surfaces 20 on the side where the metal strip material enters (hereinafter referred to as the entry side intermesh amount E, see FIG. 2) is increased to 3.0 mm or more. Tension per unit area applied to the metal strip (hereinafter,
The unit tension T) is also increased to 100 N / mm 2 or more.

【0004】[0004]

【発明が解決しようとする課題】近年、電子機器の小型
化、高集積度化の一環として、半導体用リードフレーム
等も薄肉化が進み、それに伴い、内部残留応力のより小
さい金属条材が要求されるようになった。しかし、従来
の方法では、前記要求を満足する半導体用リード材を安
定して製造することができなかった。そこで、本発明者
等は、内部残留応力の低減方法について鋭意研究を行
い、内部残留応力はテンションレベラーの設定条件を適
正化することにより低減し得ることを知見し、更に研究
を重ねて本発明を完成させるに到った。本発明は、内部
残留応力が小さくエッチング加工性に優れた半導体用リ
ード材の製造方法の提供を目的とする。
In recent years, as electronic devices have become smaller and more highly integrated, lead frames for semiconductors have become thinner, and metal strips having a smaller internal residual stress have been required. Came to be. However, with the conventional method, it has not been possible to stably manufacture a semiconductor lead material that satisfies the above requirements. Therefore, the inventors of the present invention conducted extensive research into a method for reducing internal residual stress, and found that the internal residual stress can be reduced by optimizing the setting conditions of the tension leveler, and further researches have made the present invention. Came to complete. It is an object of the present invention to provide a method for producing a semiconductor lead material having a small internal residual stress and excellent etching processability.

【0005】[0005]

【課題を解決するための手段】請求項1記載の発明は、
仕上げ調質圧延後の金属条材を、マルチローラテンショ
ンレベラーのワークロールが平面状に配された2個のワ
ークロール面間に通して矯正する半導体用リード材の製
造方法において、前記ワークロール面のチルト角度(2
個のワークロール面間の傾斜角度)θ、出側インターメ
ッシュ量(出側に位置する2個のワークロール間の間
隔)D、金属条材に掛けるユニット張力Tが下記 (1),
(2),(3)式を満足することを特徴とする半導体用リード
材の製造方法である。 60≧K≧−60…………………………(1) 1.0deg≧θ×L/250≧0.1deg……………(2) 60N/mm2≧T≧10N/mm2 ……………………(3) 但し、K=85.4×D(mm)+ 470.1×θ(deg) ×L/250+
3.7×T(N/mm2) −277.2 、 L:入側と出側のワークロール間の距離(mm)、 ワークロール直径:10〜20mm、ワークロール本数(両
側):5〜25本。
According to the first aspect of the present invention,
In the method for producing a semiconductor lead material, the metal strip material after finish temper rolling is straightened by passing it between two work roll surfaces on which work rolls of a multi-roller tension leveler are arranged in a plane. Tilt angle of (2
The inclination angle between each work roll surface) θ, the exit side intermesh amount (distance between two work rolls located on the exit side) D, and the unit tension T applied to the metal strip are as follows (1),
A method of manufacturing a lead material for a semiconductor, characterized in that the expressions (2) and (3) are satisfied. 60 ≧ K ≧ −60 ………………………… (1) 1.0deg ≧ θ × L / 250 ≧ 0.1deg ………… (2) 60N / mm 2 ≧ T ≧ 10N / mm 2 …. ………………… (3) However, K = 85.4 × D (mm) + 470.1 × θ (deg) × L / 250 +
3.7 × T (N / mm 2 ) -277.2, L: Distance between work rolls on the input side and output side (mm), work roll diameter: 10 to 20 mm, number of work rolls (both sides): 5 to 25.

【0006】本発明は、マルチローラテンションレベラ
ーでの矯正条件を限定して、矯正時における金属条材の
曲げによる伸びを小さくし、又金属条材にかかるユニッ
ト張力を低く抑える等して、得られる半導体用リード材
の形状を良好に保持しつつ内部残留応力を低減させるも
のである。
The present invention can be obtained by limiting the straightening conditions in the multi-roller tension leveler to reduce the elongation due to bending of the metal strip during straightening, and to keep the unit tension applied to the metal strip low. This is to reduce the internal residual stress while maintaining the shape of the obtained semiconductor lead material in a good condition.

【0007】[0007]

【発明の実施の形態】本発明において、チルト角度θと
はマルチローラテンションレベラーの両ワークロール面
間のなす傾斜角度で、θ= tan-1〔(E−D)/L〕
(但し、Eは2個のワークロール面間の入側間隔、Dは
2個のワークロール面間の出側間隔、Lは前記入側と出
側の距離)である。本発明において、〔85.4×D(mm)+
470.1×θ(deg) ×L/250+ 3.7×T(N/mm2) −277.2
〕で示されるK値を60以下、−60以上に限定した理由
は、K値が60を超えた場合、金属条材の伸びが大きくな
り内部残留応力が増加する為である。又−60未満では形
状や反りが修正されない。このK値を示す式及びその限
定範囲は、多くの実験を元にして得られた経験式であ
る。本発明で、前記チルト角度θにL/250を乗じた角度
を 0.1〜1.0degに限定した理由は、0.1deg未満では形状
や反りが修正できない為である。1.0degを超えると、形
状や反りは修正できるものの、内部残留応力が増加して
エッチングの際にリードフレームのダイパット部の反り
が10μmを超える大きな値になってしまう為である。又
ユニット張力を10〜60N/mm2 に限定した理由は、ユニッ
ト張力が10N/mm2 未満では、条材の形状や反りが十分に
矯正されず、 60N/mm2を超えては、形状や反りは矯正で
きるが、内部残留応力が増加してエッチングの際にリー
ドフレームのダイパット部の反りが10μmを超える大き
な値になってしまう為である。本発明において、マルチ
ローラテンションレベラーは仕上げ圧延後に入れる。仕
上げ圧延後に焼鈍を入れる場合は、焼鈍前後にテンショ
ンレベラーを入れても良いし、焼鈍前後のどちらか片方
でも良い。又テンションレベラーは、仕上げ圧延後の幅
広条材にかけても、又は前記幅広条を使用板幅にスリッ
トした幅狭条材にかけても良い。
BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, the tilt angle θ is an inclination angle formed between both work roll surfaces of a multi-roller tension leveler, and θ = tan -1 [(ED) / L].
(However, E is an entrance side distance between two work roll surfaces, D is an exit side distance between two work roll surfaces, and L is a distance between the entrance side and the exit side). In the present invention, [85.4 × D (mm) +
470.1 x θ (deg) x L / 250 + 3.7 x T (N / mm 2 ) -277.2
The reason why the K value shown by [] is limited to 60 or less and -60 or more is that when the K value exceeds 60, the elongation of the metal strip increases and the internal residual stress increases. If it is less than -60, the shape and warp are not corrected. The formula showing the K value and its limited range are empirical formulas obtained based on many experiments. In the present invention, the reason why the angle obtained by multiplying the tilt angle θ by L / 250 is limited to 0.1 to 1.0 deg is that the shape and the warp cannot be corrected when the angle is less than 0.1 deg. If it exceeds 1.0 deg, the shape and warp can be corrected, but the internal residual stress increases and the warp of the die pad portion of the lead frame becomes a large value exceeding 10 μm during etching. The reason for limiting the unit tension 10~60N / mm 2, in less than unit tension 10 N / mm 2, the shape and warpage of the strip material is not sufficiently corrected, exceed 60N / mm 2, the shape Ya Although the warp can be corrected, the internal residual stress increases, and the warp of the die pad portion of the lead frame becomes a large value exceeding 10 μm during etching. In the present invention, the multi-roller tension leveler is put in after finish rolling. When annealing is applied after finish rolling, a tension leveler may be added before or after annealing, or either one may be used before or after annealing. Further, the tension leveler may be applied to the wide strip material after finish rolling, or may be applied to the narrow strip material in which the wide strip is slit to the plate width to be used.

【0008】[0008]

【実施例】以下に、本発明を実施例により詳細に説明す
る。 (実施例1)Snを0.25wt%、Crを0.30wt%含有し、残部
銅と不可避的不純物からなる銅合金を常法により溶解鋳
造して鋳塊とし、この鋳塊を熱間圧延後面削し、次いで
冷間圧延と焼鈍を繰返した後、加工率40%の仕上げ調質
圧延を行って厚さ 0.2mmの銅合金条を得た。次に前記銅
合金条を、焼鈍後、図1に示したマルチローラテンショ
ンレベラーに掛けて矯正して、半導体用銅系リード材を
製造した。矯正にあたり、入側インターメッシュ量E、
出側インターメッシュ量D、チルト角度θ、ユニット張
力Tは種々に変化させた(E、Dは図2、θは図1参
照)。
The present invention will be described below in detail with reference to examples. Example 1 A copper alloy containing 0.25 wt% of Sn and 0.30 wt% of Cr, the balance of which is copper and unavoidable impurities is melt-cast by an ordinary method to form an ingot, and the ingot is subjected to hot-rolling and surface-cutting. Then, after repeatedly performing cold rolling and annealing, finish temper rolling with a working rate of 40% was performed to obtain a copper alloy strip having a thickness of 0.2 mm. Next, the copper alloy strip was annealed and then hung on the multi-roller tension leveler shown in FIG. 1 to be straightened to manufacture a copper-based lead material for semiconductors. Upon correction, the inter-mesh amount E on the incoming side,
The outgoing side intermesh amount D, the tilt angle θ, and the unit tension T were variously changed (see FIGS. 2A and 2B for E and D, and FIG. 1A).

【0009】得られた各々の半導体用銅系半導体用リー
ド材について、急峻度、カール、内部残留応力、ダイパ
ット部の反り量を調べた。急峻度は、板のうねりの高さ
を、そのピッチで除した百分率で示した。カールは長さ
1mの材料を壁につり下げ、その下端と壁までの距離で
表した。内部残留応力は、条の表面をエッチングにより
所定厚さ除去し、そのときの反りを測定して内部残留応
力分布を求め、その分布の最大引張残留応力で表した。
ダイパット部の反り量はダイパット部のサイズが20×20
mmの材料をディンプル面積を全面積の10%、ディンプル
深さを条の厚さの50%でエッチングしてダイパット中央
部と周辺の高さの差で表した。矯正条件を表1に、試験
結果を表2にそれぞれ示す。
The steepness, the curl, the internal residual stress, and the warp amount of the die pad portion of each of the obtained copper-based semiconductor lead materials for semiconductors were examined. The steepness is represented by the percentage of the height of waviness of the plate divided by its pitch. The curl hangs a material having a length of 1 m on a wall and expresses the distance from the lower end to the wall. The internal residual stress was obtained by removing the surface of the strip to a predetermined thickness by etching, measuring the warpage at that time to determine the internal residual stress distribution, and expressing it as the maximum tensile residual stress of the distribution.
The amount of warp of the die pad part is 20 × 20
The material of mm was etched with a dimple area of 10% of the total area and a dimple depth of 50% of the strip thickness, and expressed as the difference in height between the center and the periphery of the die pad. Table 1 shows the straightening conditions and Table 2 shows the test results.

【0010】[0010]

【表1】 *:負号(−)のついたものは上のワークロールの最下面が下のワークロール の最上面より上にあるもの。 ☆:θ= tan-1 [(E−D)/L] 、 L=250mm 。[Table 1] *: Those with a minus sign (-) have the lowermost surface of the upper work roll above the uppermost surface of the lower work roll. ☆: θ = tan -1 [(E-D) / L], L = 250 mm.

【0011】[0011]

【表2】 *:エッチング後の反り。[Table 2] *: Warpage after etching.

【0012】表1より明らかなように、本発明例品(N
o.1〜6)は、いずれも、条の形状(急峻度、カール)及
び引張強さが従来品(No.13) と同程度に良好であり、し
かも内部残留応力とダイパット部の反り量が従来品(No.
13) より著しく優れるものであった。これに対し、比較
例品のNo.7〜9 は、いずれも、 (1)式を満足せず、内部
残留応力とダイパット部の反り量が大幅に増加した。又
No.10,11は、チルト角度が小さかった為、形状・反りが
著しく低下した。この為内部残留応力とダイパット部の
反り量は測定しなかった。No.12 はチルト角度は小さい
が、張力が大きい為、内部残留応力が大きく、ダイパッ
ト部の反りが大きくなった。
As is clear from Table 1, the product of the present invention (N
In o.1 to 6), the strip shape (steepness, curl) and tensile strength are as good as those of the conventional product (No. 13), and the internal residual stress and the amount of warpage of the die pad are Is a conventional product (No.
13) It was significantly better than On the other hand, Comparative Examples Nos. 7 to 9 did not satisfy the formula (1), and the internal residual stress and the warp amount of the die pad part were significantly increased. or
In Nos. 10 and 11, the tilt angle was small, so the shape and warpage were significantly reduced. Therefore, the internal residual stress and the warp amount of the die pad were not measured. No. 12 had a small tilt angle, but had a large tension, resulting in a large internal residual stress and a large warp in the die pad.

【0013】[0013]

【発明の効果】以上に述べたように、本発明によれば、
内部残留応力が小さくエッチング加工性に優れた半導体
用リード材が得られ、工業上顕著な効果を奏する。
As described above, according to the present invention,
A lead material for semiconductors having a small internal residual stress and an excellent etching processability can be obtained, and a remarkable effect is industrially achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にて用いるマルチローラテンションレベ
ラーの例を示す説明図である。
FIG. 1 is an explanatory diagram showing an example of a multi-roller tension leveler used in the present invention.

【図2】マルチローラテンションレベラーの入側インタ
ーメッシュ量及び出側インターメッシュ量の説明図であ
る。
FIG. 2 is an explanatory diagram of an input side intermesh amount and an output side intermesh amount of a multi-roller tension leveler.

【符号の説明】[Explanation of symbols]

10……ワークロール 20……ワークロール面 30……ロール群 10 …… Work roll 20 …… Work roll surface 30 …… Roll group

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 仕上げ調質圧延後の金属条材を、マルチ
ローラテンションレベラーのワークロールが平面状に配
された2個のワークロール面間に通して矯正する半導体
用リード材の製造方法において、前記ワークロール面の
チルト角度(2個のワークロール面間の傾斜角度)θ、
出側インターメッシュ量(出側に位置する2個のワーク
ロール間の間隔)D、金属条材に掛けるユニット張力T
が下記(1),(2),(3)式を満足することを特徴とする半導
体用リード材の製造方法。 60≧K≧−60…………………………(1) 1.0deg≧θ×L/250≧0.1deg……………(2) 60N/mm2≧T≧10N/mm2 ……………………(3) 但し、K=85.4×D(mm)+ 470.1×θ(deg) ×L/250+
3.7×T(N/mm2) −277.2 、 L:入側と出側のワークロール間の距離(mm)、 ワークロール直径:10〜20mm、ワークロール本数(両
側):5〜25本。
1. A method of manufacturing a semiconductor lead material, comprising: a metal strip material after finish temper rolling; and straightening the metal strip material by passing it between two work roll surfaces on which flat work rolls of a multi-roller tension leveler are arranged. , The tilt angle of the work roll surface (the tilt angle between the two work roll surfaces) θ,
Output side intermesh amount (distance between two work rolls located on the output side) D, unit tension T applied to the metal strip
Satisfies the following formulas (1), (2), (3): 60 ≧ K ≧ −60 ………………………… (1) 1.0deg ≧ θ × L / 250 ≧ 0.1deg ………… (2) 60N / mm 2 ≧ T ≧ 10N / mm 2 …. ………………… (3) However, K = 85.4 × D (mm) + 470.1 × θ (deg) × L / 250 +
3.7 × T (N / mm 2 ) -277.2, L: Distance between work rolls on the input side and output side (mm), work roll diameter: 10 to 20 mm, number of work rolls (both sides): 5 to 25.
JP8004007A 1996-01-12 1996-01-12 Method of manufacturing lead material for semiconductor Expired - Fee Related JP2869031B2 (en)

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