JPH09223665A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Problem] When patterns with large design rules and patterns with small design rules coexist on the same substrate, it is difficult to simply mix optical lithography and electron beam lithography because different resist types are used. . Also, patterning all patterns by electron beam lithography is
It is not suitable for mass production of semiconductor devices because the throughput is significantly reduced. SOLUTION: A selection film 16 having substantially the same etching characteristics as a conductive film 14 is formed on an insulating film 15, and the selection film 16 is used to form a resist pattern 41 corresponding to a portion having a small design rule. Formed by line lithography, a resist pattern 21 corresponding to a portion having a large design rule is formed by photolithography, and the conductive film 1
4 is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a resist mask is formed by using both photolithography and electron beam lithography and is used as a patterning mask for an underlayer.

[0002]

2. Description of the Related Art Conventionally, in a method for manufacturing a semiconductor device, a step of forming a conductive film on the entire surface of a semiconductor substrate, patterning the conductive film, and processing the conductive film into a predetermined shape to form a wiring layer or the like is performed. ing.

As a conventional technique, a process of forming a gate electrode wiring of a MOS transistor and a wiring connecting portion in a process of forming a wiring layer will be described with reference to FIGS. 12 to 14. In the following description, it is assumed that the wiring connecting portion is connected to the gate electrode wiring. In addition, this wiring connection portion has a fitting margin in order to make contact between the wiring layer (not shown) formed in the upper layer and the gate electrode wiring,
The size of the gate electrode wiring is larger than that of the gate electrode wiring.

Further, (a) of each drawing is a sectional view of a portion corresponding to the AA plane of FIG. 1 (c) referred to in the embodiment of the invention, and (b) of each drawing is a B- It is sectional drawing of the part corresponding to B surface.

First, as shown in FIG. 12, a semiconductor substrate 11 is formed.
A field insulating film 112 is formed in the element isolation region of No. 1 and a gate insulating film 113 is formed on the element region of the semiconductor substrate 111.
To form In the figure, the field insulating film 112 is L
Although an example of forming by an OCOS (Local Oxidation of Silicon) method is shown, STI (Shallow Trench Isola) is shown.
formation) method. Next, these insulating films 1
On 12 and 113, a conductive film 114 of a polycrystalline silicon film or the like is formed to form a gate electrode wiring. Next, the cap insulating film 115 is formed over the conductive film 114.
The conductive film 114 and the cap insulating film 115 are formed by CVD.
(Chemical Vapor Deposition) method or sputtering method is used for deposition. After that, a resist for photolithography or a resist for electron beam lithography is applied on the cap insulating film, the resist is exposed to the shape of the gate electrode wiring by photolithography or electron beam lithography, and then exposed. By developing the resist of
A resist pattern 116 is formed.

Subsequently, as shown in FIG. 13, the cap insulating film 115 is patterned by anisotropic etching using the resist pattern 116 as a mask. Next, the resist pattern 116 used as the mask during etching is removed by ashing or the like.

Subsequently, as shown in FIG. 14, the conductive film 114 is patterned by anisotropic etching using the patterned cap insulating film 115 as a mask to form a gate electrode wiring and a wiring connection portion connected to the gate electrode wiring.

The above example shows the method of forming the gate electrode wiring of the MOS transistor and the area of the wiring connecting portion connected to the gate electrode wiring. In addition to this, the wiring layer and the wiring connecting portion between ordinary elements are formed. In the case of doing so, the same manufacturing process as described above can be used.

[0009]

In the prior art, in forming a resist pattern used as a mask for forming gate electrode wiring, g-line, i-line or Kr line is used.
Optical lithography using an F excimer laser as a light source is generally used, and in addition to this, it is conceivable to use electron beam lithography for drawing a pattern with an electron beam.

Optical lithography is a method usually used for forming a resist pattern and has a relatively high throughput, and is suitable for mass production of semiconductor devices. However, considering the production of VLSI that will be further miniaturized in the future,
There is a problem with the resolution. In the current photolithography technology, patterning with a width of about 0.25 μm is a limit even when a KrF excimer laser is used as a light source. It is predicted that the wiring design rule will be around 0.1 μm or less along with the trend of miniaturization of VLSI in the future, and the wiring design rule will be patterned using the current optical lithography technology. Is difficult to do.

On the other hand, electron beam lithography has a higher resolution than optical lithography, and it is said that electron beam lithography can sufficiently deal with patterning of design rules around 0.1 μm. However, compared with optical lithography, there is a problem that throughput is extremely poor. In photolithography, the plane of the resist can be exposed over a wide area at one time, whereas in electron beam lithography, the plane of the resist cannot be exposed over a wide area at a time, and it is necessary to fill the exposed area by drawing. Because.

Usually, the wiring patterns in the elements of the semiconductor integrated circuit have a relatively large design rule, that is, a pattern that can be sufficiently patterned even by the current photolithography, and a relatively small design rule, that is, the current pattern. Patterns that are becoming difficult to pattern by optical lithography are mixed. Therefore, in order to achieve both improved throughput and improved resolution, electron beam lithography is used only when forming patterns that have small design rules and are difficult to pattern by optical lithography. It is conceivable to use lithography.

However, originally, the types of resists to be formed as an etching mask are different between optical lithography and electron beam lithography. Therefore, it is impossible to simply use optical lithography and electron beam lithography together. If it is attempted to use the resists corresponding to the optical lithography and the electron beam lithography in combination, for example, a mask covering the formed resist pattern is formed so that the resist pattern formed by the optical lithography is not affected by the electron beam. After that, it becomes necessary to carry out electron beam lithography, or it becomes necessary to remove the resist pattern after being used as an etching mask, resulting in an increase in the number of steps. On the other hand, a resist that can be exposed to both light and an electron beam without degrading the resolution is being developed, but it has not been put to practical use yet.

It is also conceivable to pattern all the patterns having large design rules and patterns having small design rules by electron beam lithography, but in this case, the throughput is significantly reduced. That is, as described above, in the photolithography, the plane of the resist can be exposed over a wide range at once, whereas in the electron beam lithography, it is necessary to fill the area to be exposed by drawing. At present, the time required to expose the resist per wafer is about several minutes including the movement time of the wafer in the case of exposure by optical lithography, whereas several hours are required for each wafer in electron beam lithography. . Therefore, it is not realistic to expose the resist pattern only by the electron beam lithography in the manufacture of a semiconductor device in which large-scale mass production is performed.

[0015]

According to the present invention, in a method of manufacturing a semiconductor device, particularly in a step of forming a wiring layer, a resist having a small design rule is provided so as to prevent a decrease in throughput and to cope with miniaturization of a VLSI. There is provided a manufacturing method for using electron beam lithography for the patterning of, and photolithography for the patterning of the resist in other portions. This is done by the following means.

That is, according to the first means of the present invention, the first insulating film, the conductive film, the second insulating film, and the conductive film have etching characteristics on the surface of the semiconductor substrate having the first and second regions. A step of sequentially forming a substantially similar selective film,
Forming a first resist pattern on the first region of the surface of the selective film by photolithography, patterning the selective film using the first resist pattern as a mask, and removing the first resist pattern A step, a step of forming a second resist pattern on the second region of the surface of the second insulating film by electron beam lithography, the second insulating film using the second resist pattern and the selective film as a mask The method is characterized by including a step of patterning, a step of removing the second resist pattern, and a step of patterning the conductive film using the patterned second insulating film as a mask.

According to the second aspect of the present invention, the first insulating film, the conductive film, the second insulating film, and the conductive film have substantially the same etching characteristics on the semiconductor substrate having the first and second regions. Sequentially forming a similar selective film, a step of forming a second resist pattern on the second region of the selective film surface by an electron beam lithography method, and the selective film using the second resist pattern as a mask Patterning, a step of removing the second resist pattern, a step of forming a first resist pattern on the second insulating film by a photolithography method, the first resist pattern and the selective film as a mask Patterning the second insulating film, removing the first resist pattern, and patterning the conductive film using the patterned second insulating film as a mask. Characterized by comprising the step of packaging.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a first embodiment of the present invention, a manufacturing process of a gate electrode wiring of a MOS transistor and a wiring connecting portion connected thereto will be described with reference to FIGS. Incidentally, FIG. 1C shows a schematic top view of the MOS transistor after the formation of each element. In this figure, a gate electrode wiring formation region 211, an element formation region 212, an element isolation region 213, and a wiring connection portion formation region 214 are shown. Further, (a) of each figure is shown in FIG.
1C is a cross-sectional view of a portion corresponding to the AA plane in FIG. 1C, that is, a cross section in a direction perpendicular to the gate electrode wiring, and FIG. 1B is a BB plane in FIG. A cross-sectional view of a corresponding portion, that is, a cross section in a direction parallel to the gate electrode wiring is shown. In addition, this wiring connecting portion is formed to have a contact margin with a wiring layer (not shown) formed in an upper layer and a gate electrode wiring with a fitting margin, and its size is larger than that of the gate electrode wiring. And

First, as shown in FIGS. 1A and 1B, the field insulating film 12 is formed in the element isolation region on the semiconductor substrate 11 by the LOCOS method. The field insulating film can be formed by the STI method instead of the LOCOS method. Next, gate oxidation is performed to form a film thickness of 5 ~
A 20 nm gate insulating film 13 is formed. Next, in order to form a gate electrode wiring, a conductive film 14 having a film thickness of 100 to 400 nm is formed on the gate insulating film 13 by a CVD method, a sputtering method or the like. Next, a film thickness of 20 is formed on the conductive film 14 by the CVD method or the like.
A cap insulating film 15 of about 0 nm is formed. Further, a selective film 16 having substantially the same etching characteristics as the conductive film 14 is formed on the cap insulating film 15.

The conductive film 14 is made of polycrystalline silicon containing phosphorus or boron at a high concentration, a refractory metal such as tungsten, or a refractory metal silicide such as tungsten silicide or molybdenum silicide as an upper layer. A laminated structure using crystalline silicon or a refractory metal such as tungsten or molybdenum is formed in an upper layer and a laminated structure using polycrystalline silicon in a lower layer.

The cap insulating film 15 is formed of a material having a sufficient selection ratio for etching with the conductive film 14, that is, a silicon oxide film, a silicon nitride film, or the like. The selection film 16 is
A material having substantially the same etching characteristics as the conductive film 14, that is, the same material as all or part of the conductive film 14, or a material containing the conductive film 14, such as polycrystalline silicon or refractory metal. , A refractory metal silicide, or a material containing these. In general, refractory metal and refractory metal silicide have an etching selection ratio of about several times that of polycrystalline silicon. Therefore, the selection film 16 is most preferably formed of polycrystalline silicon. Specifically, when the conductive film 14 is formed of a single layer of polycrystalline silicon or refractory metal, or when the conductive film 14 is formed of a laminated layer of refractory metal or refractory metal silicide and polycrystalline silicon. Most preferably, the selection film 16 is made of polycrystalline silicon.

When the selection film 16 is made of polycrystalline silicon, the film thickness of this polycrystalline silicon is the conductive film 14.
It is desirable that the thickness is less than or equal to the thickness of the polycrystalline silicon formed as a part of

However, regarding the film thickness and the material of the selection film 16, it is only necessary to select the conditions such that the film is removed together with the part where the conductive film 14 is removed during the etching for forming the gate electrode described later.

Subsequently, as shown in FIG. 2, a resist for photolithography is applied to the entire surface of the selection film 16. Next, a resist pattern 21 is formed by exposing the resist to a predetermined pattern using photolithography and developing the resist. The resist pattern 21 is formed at a portion having a relatively large design rule, which can be sufficiently dealt with by photolithography. That is, it is formed not in a place such as a gate electrode wiring, which is difficult to cope with by photolithography, but in a portion corresponding to a wiring connecting portion or a pad for making a connection with an upper wiring. Linewidth of 0.25μ in current optical lithography
Although it is possible to perform patterning with a length of about m, the vertical and horizontal dimensions of the resist pattern are formed here with a length of about 0.8 to 1.4 μm.

Subsequently, as shown in FIG. 3, the selection film 16 is etched by anisotropic etching using the resist pattern 21 as a mask. At this time, since the etching selection ratio between the cap insulating film 15 and the selection film 16 is large, only the selection film 16 can be etched and the cap insulating film 15 can be left. When etching the selective film 16, by using Cl ₂ , HBr, SF ₆ or the like as an etching gas, the etching selection ratio with respect to the insulating film can be set to about 10 to 30. Next, the resist pattern 21 is removed by ashing or a combination of ashing and chemical treatment with sulfuric acid and hydrogen peroxide.

Subsequently, as shown in FIG. 4, a resist for electron beam lithography is applied on the cap insulating film 15 and the patterned selection film 16. Next, a resist pattern 41 is formed by exposing and developing only a portion corresponding to the gate electrode wiring, which is becoming difficult to be patterned by photolithography, using electron beam lithography. In electron beam lithography, patterning is possible even with a line width of about 0.1 μm or less, but here, the resist pattern is formed with a line width of about 0.15 μm.

It should be noted that a pattern having a relatively large design rule, which can be sufficiently dealt with by optical lithography, and a pattern having a relatively small design rule, which is becoming difficult to pattern by optical lithography, are combined to form one pattern. In this case, the resist pattern 41 is
By forming the selective film 16 so as to overlap it, it is possible to deal with a slight misalignment between the two.

Subsequently, as shown in FIG. 5, a resist pattern 41 whose patterning is completed by the preceding step.
Using both the selective film 16 and the mask 16 as a mask, the cap insulating film 1
5 is etched by anisotropic etching. On this occasion,
Since the etching selection ratio of the cap insulating film 15 to the conductive film 14 and the selection film 16 is relatively large, only the cap insulating film 15 can be etched and the conductive film 14 and the selection film 16 can be left. When the cap insulating film 15 is etched, CF ₄ , CO, CHF ₃ or the like is used in combination as an etching gas, so that the etching selection ratio to the conductive film can be set to about 10 to 30. Next, the resist pattern 41 is removed by ashing or the like.

Subsequently, as shown in FIG. 6, the conductive film 14 is etched by anisotropic etching using the cap insulating film 15 as a mask. At this time, since the selective film 16 has substantially the same etching characteristics as the conductive film 14, it is etched and removed at the same time as the conductive film 14. Therefore, the step of removing the selection film 16 can be omitted. The conductive film 14
At the time of etching, by using Cl ₂ , HBr, SF ₆ or the like as an etching gas, the etching selection ratio with respect to the cap insulating film 15 can be set to about 10 to 30. Through the above steps, the step of forming the gate electrode wiring and the wiring connecting portion connected thereto is completed.

According to the first embodiment of the present invention, the selection film 16 having substantially the same etching characteristics as the conductive film 14 is further formed on the cap insulating film 15. Then, after forming a resist pattern 21 in a portion having a large design rule that can be dealt with by the photolithography technique, the selective film 16 is patterned using this as a mask. Next, a resist pattern 41 at a portion which is becoming difficult to deal with by the photolithography technique is formed by using electron beam lithography, and the cap insulating film 15 is formed by using the resist pattern 41 and the patterned selection film 16 as a mask.
Is performed. Then, the conductive film 14 is patterned using the finally patterned cap insulating film 15 as a mask.

Next, regarding the second embodiment of the present invention,
This will be described with reference to FIGS. 7 to 11. The same components as those in the first embodiment are designated by the same reference numerals in the drawings, and the description thereof will be omitted. The film thickness and material of each structure are the same as those in the first embodiment unless otherwise specified. Incidentally, (a) of each figure is A- in FIG. 1 (c).
Sectional views corresponding to the plane A, (b) of each figure are sectional views corresponding to the plane BB in FIG. 1 (c).

First, as shown in FIG. 7, a gate insulating film 13, a conductive film 14, and a cap insulating film 1 are formed on a semiconductor substrate 11.
5, the selection film 16 is sequentially formed. This step is the same as the step shown in FIG. 1 in the first embodiment. The film thicknesses and materials of the conductive film 14, the cap insulating film 15, and the selection film 16 are also the same as those in the first embodiment. Next, a resist for electron beam lithography is applied on the selection film 16,
A resist pattern 71 is formed by patterning using electron beam lithography only a portion that is becoming difficult to deal with with the optical lithography technique. When there is a portion where a pattern with a large design rule that can be sufficiently dealt with by optical lithography and a pattern with a small design rule that is becoming difficult to deal with by optical lithography are combined, the resist pattern 71 is more than the original pattern. It is possible to deal with a slight misalignment between the two by forming them so as to overlap on the pattern side having a large design rule.

Then, as shown in FIG. 8, the selective film 16 is etched by anisotropic etching using the resist pattern 71 as a mask. At this time, since the etching selection ratio between the selection film 16 and the cap insulating film 15 is large, only the selection film 16 can be patterned and the cap insulating film 15 can be left. Next, the resist pattern 71 is removed by ashing or the like.

Subsequently, as shown in FIG. 9, a resist for photolithography is applied on the cap insulating film 15 and the selection film 16. Next, a resist pattern 91 is formed by exposing and developing a predetermined pattern using optical lithography.
To form The resist pattern 91 is formed at a portion having a relatively large design rule, which can be sufficiently dealt with by photolithography. That is, the gate electrode wiring is not formed in a portion that is difficult to cope with by photolithography, but is formed in a portion corresponding to a wiring connection portion or a portion where a pad is formed for connection with an upper layer wiring.

Then, as shown in FIG. 10, the cap insulating film 15 is etched by anisotropic etching using both the resist pattern 91 and the selection film 16 as a mask. At this time, the cap insulating film 15, the conductive film 14, and the selection film 16
Since the etching selection ratio is high, only the cap insulating film 15 can be etched and the conductive film 14 and the selection film 16 can be left. Next, the resist pattern 91 is removed by ashing or the like.

Subsequently, as shown in FIG. 11, the conductive film 14 is etched by anisotropic etching using the cap insulating film 15 as a mask. At this time, the selection film 16 is the conductive film 14
Since the etching characteristics are substantially the same, they are simultaneously etched and removed together with the conductive film 14. Therefore, the step of removing the selection film 16 can be omitted. Through the above steps, the step of forming the gate electrode wiring and the wiring connecting portion connected thereto is completed.

In the second embodiment, the conductive film 1 is further formed on the cap insulating film 15 as in the first embodiment.
4 to form a selective film 16 having substantially the same etching characteristics. Then, first, a resist pattern 71 is formed by electron beam lithography in a portion where it is becoming difficult to deal with with the photolithography technique, and the selection film 16 is patterned using this. Next, after forming a resist pattern 21 in a portion having a large design rule that can be dealt with by optical lithography, the cap insulating film 15 is patterned using these as a mask. Then, using the finally patterned cap insulating film 15 as a mask, the conductive film 1 is formed.
4 is patterned. That is, the order of forming a resist pattern using optical lithography and forming a resist pattern using electron beam lithography is different between the first embodiment and the second embodiment.

In each of the above-described embodiments, a laminated structure of a conductive film to be a gate electrode wiring and a cap insulating film formed on the upper surface thereof is used, and the conductive film and the etching characteristic are substantially formed on the laminated structure. By providing a similar selective film,
Optical lithography and electron beam lithography can be used together. Further, since the selective film is removed at the same time as the step of etching the conductive film, the step for removing it can be omitted. As a result, when patterning a wiring layer or the like, it becomes possible to select only a portion with a small design rule, which is becoming difficult to pattern with current optical lithography, and pattern this portion with electron beam lithography. It is possible to cope with the miniaturization of the LSI and prevent a decrease in throughput.

In the above embodiment, the thickness of the selection film 16 is equal to that of the conductive film 14, and even if the thickness of the conductive film 14 is greater than or equal to that of the conductive film 14, they are simultaneously removed in the conductive film etching step. It suffices if it has the property to be. Further, in the above-described embodiment, the formation process of the gate electrode wiring and the wiring connection portion is described, but the present invention is not limited to this, and it is not limited to the formation process of the entire wiring layer in which the conductive film and the insulating layer are stacked. It is possible to apply. Further, it can be applied to a step of forming a resistance element formed of a conductive film having a high resistance on a semiconductor substrate and a connection pole portion of the resistance element connected to the resistance element. That is, since a region having a narrower line width can be patterned by electron beam lithography, a resistance element having a higher resistance can be formed in a fine region. Further, the numerical values, materials and the like shown above are not limited to the above, and can be implemented in various modes.

[0040]

According to the present invention, when a pattern including a pattern which is difficult to be dealt with by the current photolithography technique is included, the wiring layer having a similar etching property to the upper surface of the film formed as the wiring layer. By providing the selected film, it becomes possible to perform patterning by using a mixture of optical lithography and electron beam lithography. Further, since this selective film is etched and removed at the same time when the conductive film is etched, it is not necessary to add a step for removing it. Therefore, at the time of patterning the wiring layer, it is possible to select only a portion having a small design rule, which is becoming difficult to perform by the current optical lithography, and to pattern only this portion by electron beam lithography, which lowers the throughput. Can be prevented.

[Brief description of drawings]

FIG. 1 is a process sectional view illustrating a first embodiment of the present invention.

FIG. 2 is a process sectional view explaining the first embodiment of the present invention following FIG. 1;

FIG. 3 is a process sectional view explaining the first embodiment following FIG. 2 of the present invention.

FIG. 4 is a process sectional view explaining the first embodiment following FIG. 3 of the present invention.

FIG. 5 is a process sectional view explaining the first embodiment following FIG. 4 of the present invention.

FIG. 6 is a process sectional view illustrating the first embodiment following FIG. 5 of the present invention.

FIG. 7 is a process cross-sectional view illustrating a second embodiment of the present invention.

FIG. 8 is a process cross-sectional view illustrating a second embodiment following FIG. 7 of the present invention.

FIG. 9 is a process sectional view for explaining the second embodiment following FIG. 8 of the present invention.

FIG. 10 is a process sectional view explaining a second embodiment following FIG. 9 of the present invention.

FIG. 11 is a process sectional view illustrating a second embodiment following FIG. 10 of the present invention.

FIG. 12 is a process cross-sectional view illustrating a conventional manufacturing method.

FIG. 13 is a process cross-sectional view illustrating the manufacturing method following conventional FIG.

FIG. 14 is a process sectional view explaining the manufacturing method following the conventional manufacturing method shown in FIG. 13;

[Explanation of symbols]

 11, 111 Semiconductor substrate 12, 112 Field insulating film 13, 113 Gate insulating film 14, 114 Conductive film 15, 115 Cap insulating film 16 Selective film 21, 41, 71, 91, 116 Resist pattern 211 Element forming region 212 Gate electrode wiring Formation region 213 Element isolation formation region 214 Wiring connection portion formation region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/88 Q

Claims (15)

[Claims] 1. A first insulating film, a conductive film, a second insulating film, and a selection film having substantially the same etching characteristics as those of the conductive film on a surface of a semiconductor substrate having first and second regions. A step of sequentially forming, a step of forming a first resist pattern on the first region of the surface of the selective film by an optical lithography method, a step of patterning the selective film using the first resist pattern as a mask, A step of removing one resist pattern, a step of forming a second resist pattern on at least the second region of the surface of the second insulating film by an electron beam lithography method, and a mask of the second resist pattern and the selective film Patterning the second insulating film, removing the second resist pattern, and using the patterned second insulating film as a mask The method of manufacturing a semiconductor device characterized by comprising a step of patterning the film. 2. A first insulating film, a conductive film, a second insulating film, and a selective film having etching characteristics substantially the same as those of the conductive film are sequentially formed on a semiconductor substrate having first and second regions. A step of forming, a step of forming a second resist pattern on a second region of the surface of the selective film by an electron beam lithography method, a step of patterning the selective film using the second resist pattern as a mask, A step of removing the resist pattern, a step of forming a first resist pattern on at least the second insulating film by an optical lithography method, and a patterning of the second insulating film using the first resist pattern and the selective film as a mask And a step of removing the first resist pattern after the step of patterning the second insulating film, and a step of removing the patterned second insulating film. The method of manufacturing a semiconductor device characterized by comprising the step of patterning the conductive film as a disk. 3. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of patterning the conductive film, the patterned selective film is simultaneously removed. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness of the selection film is formed to be equal to or less than the film thickness of the conductive film. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the first region is a wiring connection portion forming region, and the second region is a gate electrode wiring forming region. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the first region is a resistance element connection portion formation region, and the second region is a resistance element formation region. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film and the selection film are formed of the same material or containing the same material. 8. The manufacturing of a semiconductor device according to claim 1, wherein the conductive film is formed by stacking a refractory metal silicide and polycrystalline silicon, and the select film is formed by polycrystalline silicon. Method. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film is formed by stacking a refractory metal and polycrystalline silicon, and the select film is formed by polycrystalline silicon. 10. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film and the selection film are formed of polycrystalline silicon. 11. The film thickness of the polycrystalline silicon formed as the selection film is set to be equal to or less than the film thickness of the polycrystalline silicon formed as the conductive film.
0. A method for manufacturing a semiconductor device according to item 0. 12. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is formed of a silicon oxide film or a silicon nitride film. 13. When the first region and the second region are adjacent to each other, the second resist pattern is formed on a part of the first region by extending from the second region. The method for manufacturing a semiconductor device according to claim 1 or 2. 14. A step of sequentially forming a first insulating film, a conductive film, a second insulating film, and a selection film on a surface of a semiconductor substrate having first and second regions, and the selection by photolithography. Forming a first resist pattern on the first region of the film surface; patterning the selective film using the first resist pattern as a mask; removing the first resist pattern; electron beam lithography Forming a second resist pattern on the second region of at least the second insulating film surface by a method, and patterning the second insulating film using the second resist pattern and the selective film as a mask, A step of removing the second resist pattern, and a step of patterning the conductive film using the patterned second insulating film as a mask, Serial selective membrane, in the step of patterning the conductive film, a method of manufacturing a semiconductor device and forming with the characteristic to be removed at the same time. 15. A step of sequentially forming a first insulating film, a conductive film, a second insulating film, and a selection film on a semiconductor substrate having first and second regions, and the selection by electron beam lithography. A step of forming a second resist pattern on a second region of the film surface, a step of patterning the selective film using the second resist pattern as a mask, a step of removing the second resist pattern, and a photolithography method. Forming a first resist pattern on at least the second insulating film; patterning the second insulating film using the first resist pattern and the selection film as a mask; and patterning the second insulating film After the step, a step of removing the first resist pattern and a step of patterning the conductive film using the patterned second insulating film as a mask. The method of manufacturing a semiconductor device according to claim 1, wherein the selective film is formed with a characteristic that the selective film is simultaneously removed in the step of patterning the conductive film.