JPH09233000A - Amplitude equalizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the malfunction of the equalizing operation of the reception signal of a variable amplitude equalizer, and also to attain the improvement of the quality of a transmission signal even in the case that fading larger than the equalizing capacity of an amplitude distortion equalization circuit occurs in a transmission line. SOLUTION: This amplitude equalizer is provided with the variable amplitude equalizer 10 provided with two amplitude distortion equalization circuits 1, 2, a demodulation circuit 3, a waveform equalization circuit 4, a residual distortion detection circuit 5, two reset circuits 6, 7 and a control signal generation circuit 8. Here, when the residual value of primary distortion in the output of the variable amplitude equalizer 10 is large on the basis of a tap coefficient signal 105 showing the weighted state of each tap coefficient in the waveform equalization circuit 4, the residual distortion of the primary distortion is detected by the residual distortion detection circuit 5. Then, a reset instructing signal 106 is sent to the reset circuit 6 inputting/outputting and resetting a control signal 108 so as to stop a secondary amplitude distortion equalization circuit 1 by the control signal 108 from the control signal generation circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is mainly used for digital microwave communication using a multi-valued quadrature amplitude modulation method and attenuates the amplitude of a specific frequency component by superimposing a direct wave and an interference wave on a propagation path. The present invention relates to an amplitude equalizer having a function of equalizing.

[0002]

2. Description of the Related Art Conventionally, as an example of this type of amplitude equalizer, there is an adaptive automatic equalizer disclosed in Japanese Patent Laid-Open No. 3-220924. FIG. 3 is a circuit block diagram showing the basic configuration of this adaptive automatic equalizer.

This adaptive automatic equalizer is, as shown in the figure,
Primary distortion equalizer 11, resonance type equalizer 12, switch 13,
It comprises a three-wave detector 18, a logic circuit 19, a demodulator 14, an I-channel transversal equalizer 15, a Q-channel transversal equalizer 16, and a phase discriminating means 17. Here, it has a function of equalizing the first-order distortion included in the input signal by the first-order distortion equalizer 11 or equalizing the second-order distortion included in the input signal by the resonance type equalizer 12. As the equalizer control method here, the first-order distortion equalizer 11 is controlled by transversal equalizers 15, 1
The center tap values of the six orthogonal I and Q channels are used, and the phase discrimination means 1 is used for controlling the resonance type equalizer 12.
The phase information of the signals before and after the transversal equalizer 16 obtained in 7 is used. As a result, when the resonance type equalizer 12 detects non-minimum phase fading that cannot be equalized, that is, fading in which the interference wave advances from the main wave in the two-wave interference fading, the waveform equalization action is stopped. We are in control.

Another example of the amplitude equalizer is disclosed in Japanese Patent Laid-Open No. Hei 3
The demodulation device disclosed in Japanese Patent Laid-Open No. -46829 is mentioned. FIG. 4 is a circuit block diagram showing the basic configuration of this demodulation device.

This demodulator includes an adaptive amplitude equalizer 21, which includes an adaptive equalizer 22 connected to an input terminal T _I and a control signal generator 23 for supplying a control signal to the adaptive equalizer 21, a demodulator 2.
4, disconnection detection circuit 25, and two output terminals T _O 1, T _O
2 and comprises a transversal equalizer 26 connected to 2. Here, the disconnection detection circuit 25 detects a signal disconnection from the demodulator 4, and when the disconnection is detected, the equalization operation of the adaptive equalizer 22 and the transversal equalizer 26 is reset. Due to this reset operation, if deep fading occurs in the propagation path and the demodulation signal in the demodulator 24 is cut off due to synchronization pull-out or the like, synchronization pull-in at the time of re-pull-in can be facilitated.

Furthermore, in addition to overcoming the disadvantage that the equalizing action of the resonance type equalizer 12 in the non-minimum phase fading occurs in the adaptive automatic equalizer 12 shown in FIG. As another example of an amplitude equalizer that repeatedly performs a reset operation to facilitate synchronization pull-in at the time of re-pull-in when demodulation output is abnormal due to synchronization pull-out or the like of the demodulator 24 in the demodulator, JP-A-4-2227 is disclosed.
An automatic adaptive equalizer according to the publication is given. FIG.
FIG. 3 is a circuit block diagram showing the basic configuration of this automatic adaptive equalizer.

As shown in the figure, this automatic adaptive automatic equalizer includes a variable amplitude equalizer 10 including a secondary amplitude distortion equalization circuit 1 and a primary amplitude distortion equalization circuit 2, a demodulation circuit 3, and a wave type. It comprises an equalizing circuit 4, two reset circuits 6 and 7, and a control signal generating circuit 8. However, here, the out-of-synchronization detector and the oscillator are shown in the form of being included in the demodulation circuit 3, and the waveform equalization circuit 4 as a decision feedback equalizer is generally based on the feasibility of the circuit configuration. In consideration of the fact that a band and digital processing type is used, the circuit configuration disclosed is modified and arranged in the subsequent stage of the demodulation circuit 3.
As the variable amplitude equalizer 10 here, the one proposed in Japanese Patent Application No. 54-156610 is applied as an example, and the delay amount of the delay line is changed.

Here, a secondary amplitude distortion equalization circuit 1 for secondary amplitude distortion equalization and a primary amplitude distortion equalization circuit 2 for primary amplitude distortion equalization are provided, and each amplitude distortion equalization circuit 1 is provided. , 2 are connected to reset circuits 6 and 7 for inputting / outputting a control signal, and a reset operation is performed in order to facilitate synchronization pull-in at the time of re-pull-in when demodulation output is abnormal due to synchronization pull-out of the demodulator circuit 3 or the like. Repeat. As a result, even if the amplitude is changed, the delay characteristic with respect to the frequency is always constant. Therefore, a minimum phase in the propagation path, that is, fading in which the interference wave is delayed from the main wave due to two-wave interference fading, or a non-minimum Even when any fading of the phase occurs, the same equalization characteristic can be obtained. Further, the control signal generation circuit 8 includes the amplitude distortion equalization circuits 1,
2 is controlled, but the control means here is Japanese Patent Application No. 58-0.
No. 68635, a control technique for detecting the secondary amplitude distortion and the primary amplitude distortion included in the eye pattern after the demodulation identification and minimizing them is used. Further, the waveform equalizer circuit 4 as a transversal equalizer uses a decision feedback type equalizer which has a relatively simple circuit configuration and can obtain a large equalizing ability. This decision feedback equalizer uses the reference signal obtained by judging the output of the transversal filter instead of directly using the equalizer input signal for the tap that is temporally preceding the center tap of the transversal filter. In particular, the equalization effect is extremely large when fading in the minimum phase occurs due to the two-wave interference fading.
Incidentally, as a publicly known document relating to this decision feedback equalizer, see "Application of Digital Signal Processing" edited by The Institute of Electronics and Communication Engineers, pp. 56-5-20, p. 163.

[0009]

In the case of the automatic adaptive equalizer shown as another example of the above-mentioned amplitude equalizer, when fading exceeding the equalization capability of the amplitude distortion equalization circuit occurs in the propagation path, the amplitude is increased. The distortion equalization circuit may malfunction to deteriorate the quality of the transmission signal (reception signal).

More specifically, in this automatic adaptive equalizer, fading exceeding the equalizing ability of the amplitude distortion equalizing circuit occurs and, for example, the frequency spectrum of the transmission signal with respect to the center frequency fc is shown in FIG. When one state S1a as shown in a) is changed by the frequency characteristic of the propagation path and is received as another state S2a as shown in FIG. 6B, the frequency spectrum of the received signal corresponds to it. With respect to the center frequency fc, one state S1b as shown in FIG. 7A to another state S as shown in FIG. 7B.
It shall be changed to 2b.

At this time, the amplitude characteristics of the received signal in the secondary amplitude distortion equalization circuit are from one state S1c as shown in FIG. 8A to another state S as shown in FIG. 8B.
2c, and the amplitude characteristic of the received signal in the first-order amplitude distortion equalization circuit is changed from one state S1d as shown in FIG. 9 (a) to another state S2d as shown in FIG. 9 (b). . As a result, the frequency spectrum related to the output of the variable amplitude equalizer is shown in FIG.
From one state S1e as shown in (a) to FIG. 10 (b).
The state is changed to the other state S2e as shown in FIG. Here, since the amount of fading exceeds the equalization capability of the amplitude equalizer, the residual distortion shown as the shaded portion is generated in the one state S1e.

In the amplitude equalizer, the control signal generation circuit 8 for controlling the amplitude distortion equalization circuits 1 and 2 detects the amplitude distortion component of the demodulated signal of the demodulator 3 to detect the secondary amplitude distortion, The first-order amplitude distortion is controlled so as to be the minimum, but when residual distortion such as the shaded portion in FIG. 10A occurs, the variable amplitude equalizer detects this as the residual first-order distortion component. At the same time, the residual (second-order) distortion component is detected, and the second-order amplitude distortion equalizer circuit equalizes the residual second-order distortion component with a concave (convex downward) frequency characteristic as shown in FIG. 8B. Therefore, the frequency spectrum related to the output of the variable amplitude equalizer is added with the second-order amplitude distortion by this amount, and finally the other state S as shown in FIG.
2e.

Therefore, in this amplitude equalizer, when the concave frequency characteristic shown in FIG. 8 (b) is given in the second-order amplitude distortion equalization circuit, the center frequency fc component of the received signal is reduced, resulting in transmission. The quality of the signal deteriorates.

Incidentally, when residual distortion occurs in the output of such a variable amplitude equalizer, the amplitude distortion equalizer circuit for detecting the residual distortion malfunctions especially when a decision feedback equalizer is used as the waveform equalizer. It is known that This is because the decision feedback equalizer has a very large equalizing action, so even if fading that exceeds the capacity of the amplitude distortion equalizer circuit occurs and residual distortion occurs in the output of the amplitude distortion equalizer circuit, This is because the transmission signal can be reproduced and identified by the waveform equalization function of the waveform equalization circuit.

However, one state S as shown in FIG.
Other state S2e as shown in FIG.
Has a downward convex frequency characteristic, the waveform equalization in the waveform equalization circuit is not sufficiently performed when this is processed as an in-circuit signal, and the quality of the transmission signal deteriorates significantly. To do.

The present invention has been made to solve such a problem, and its technical problem is that even if fading exceeding the equalizing ability of the amplitude distortion equalizing circuit occurs in the propagation path, the variable amplitude can be changed. It is an object of the present invention to provide an amplitude equalizer capable of preventing the malfunction of the equalization operation of the reception signal of the equalizer and improving the quality of the transmission signal.

[0017]

According to the present invention, in an amplitude equalizer used in a multi-valued quadrature amplitude modulation system, N-th order amplitude distortion (where N is a natural number Amplitude variable equalizer for variable equalization, a demodulation circuit for demodulating the equalized received signal and outputting a demodulated signal, and a control signal for controlling the variable amplitude equalizer according to the demodulated signal Control signal generating circuit, a waveform equalizing circuit that equalizes the demodulated signal on the time axis, a residual distortion detection circuit that detects the residual distortion of the demodulated signal and outputs a reset instruction signal, and a reset An amplitude equalizer having a reset circuit that outputs a reset signal for resetting a control signal according to an instruction signal is obtained.

Further, according to the present invention, in the above-mentioned amplitude equalizer, the variable amplitude equalizer is K based on K of 1 or more and N or less.
The residual distortion detection circuit includes a second-order amplitude distortion equalization circuit, and the residual distortion detection circuit detects the residual distortion of the demodulated signal and detects the residual distortion of the demodulated signal, which is equal to or greater than 1 and equal to or less than N (where J ≠ K). A reset instruction signal is output according to the value, and the reset circuit inputs the control signal for the K-order amplitude distortion equalization circuit from the control signal generation circuit according to the reset instruction signal to input the K-order amplitude distortion equalization circuit. An amplitude equalizer is provided that stops the equalization.

Further, according to the present invention, in any one of the amplitude equalizers described above, the waveform equalizer circuit outputs a tap coefficient signal indicating a plurality of time-series weighted tap coefficients, and residual distortion is generated. The detection circuit compares the residual amplitude distortion amount of the demodulated signal obtained by calculating the weighting of the tap coefficient based on the tap coefficient signal with a specified value that depends on the equalization capability of the variable amplitude equalizer, and thereby performs a reset instruction. An amplitude equalizer that outputs a signal is obtained.

[0020]

In the amplitude equalizer of the present invention, the residual value of the first-order distortion at the output of the variable amplitude equalizer is based on the tap coefficient signal indicating the weighted state of the time-series tap coefficients in the waveform equalizer circuit. When the value is large, the residual distortion detection circuit detects the residual distortion of the first-order distortion, and the control signal from the control signal generation circuit causes the secondary amplitude distortion equalization circuit to stop. A reset instruction signal is sent to the circuit. Due to this reset function, deep fading occurs in the transmission signal input as a reception signal, large first-order distortion occurs, and even if the residual value of the first-order distortion is large, it is possible to prevent malfunction of the second-order amplitude distortion equalization circuit. . Therefore, distortion addition in the amplitude distortion equalization circuit in the variable amplitude equalizer is prevented, and the quality improvement of the transmission signal is promoted.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The amplitude equalizer of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a circuit block diagram showing the basic configuration of an amplitude equalizer according to an embodiment of the present invention.

This amplitude equalizer is different from the conventional one shown in FIG. 3 in that it receives the tap coefficient signal 105 indicating the weighted state of a plurality of time-series tap coefficients in the waveform equalizer circuit 4 and receives the reset circuit 6 therein. It is different in that a residual strain detection circuit 5 for transmitting a reset instruction signal 106 is provided in the. The other components are common, and the variable amplitude equalizer 10 including the secondary amplitude distortion equalization circuit 1 and the primary amplitude distortion equalization circuit 2, the demodulation circuit 3, the wave type equalization circuit 4, and It is provided with reset circuits 6 and 7 and a control signal generation circuit 8 and is also applied in the multilevel quadrature amplitude modulation system.

Of these, the demodulation circuit 3 is a variable amplitude equalizer 1
Carrier wave synchronization, demodulation, and identification are performed on the reception signal 101 that has undergone amplitude equalization at 0, and a demodulation signal 104 is output. The waveform equalization circuit 4 performs waveform shaping on the demodulated signal 104, cancels intersymbol interference, performs waveform equalization on the time axis, and outputs the output signal 102.
And a tap coefficient signal 105 indicating a plurality of time-series weighted tap coefficients described above. The control signal generation circuit 8 sends control signals 108 and 109 to the secondary amplitude distortion equalization circuit 1 and the primary amplitude distortion equalization circuit 2 in the variable amplitude equalizer 10, respectively, and outputs the secondary amplitude included in the received signal 101. The equalization operation is controlled so that the distortion and the first-order amplitude distortion are minimized. The residual distortion detection circuit 5 has a function of inputting the tap coefficient signal 105 and detecting a first-order amplitude distortion component included in the demodulation signal 104 input to the waveform equalization circuit 4, and the first-order amplitude distortion has a specific prescribed value. Reset instruction signal 1 for resetting the secondary amplitude distortion equalization circuit 1
06 is sent to the reset circuit 6. Reset circuit 6,7
Inputs and outputs the control signal 108 for second-order amplitude distortion equalization and the control signal 109 for first-order amplitude distortion equalization.
When the reset instruction signal 106 from the residual distortion detection circuit 5 is input, the reset signal 107 is output to stop the demodulation operation and the waveform equalization operation of the demodulation circuit 3 and the waveform equalization circuit 4, and the amplitude distortion equalization circuit 1 Then, the amplitude distortion equalization circuit 2 is reset through the reset circuit 7 and the equalization operation is stopped.

FIG. 2 is a circuit block diagram showing a detailed configuration of the residual distortion detection circuit 5. The residual distortion detection circuit 5 has a predetermined number of lines for inputting a tap coefficient signal 105 including weighting of each tap coefficient for 5 taps on the orthogonal side of each CH of I-CH and Q-CH orthogonal to each other, It has an arithmetic circuit composed of a subtractor 31 and an adder 32 inserted in each line, a register 34 and a comparator 33. However, the tap coefficient output may be any value as long as it is 3 taps or more including the center tap.

The calculation method here is the tap coefficient signal 10
5 is input to the arithmetic circuit, and each tap coefficient before and after the center tap is calculated to calculate the first-order amplitude distortion amount of the residual distortion included in the demodulated signal 104.

Specifically, the calculation here is performed by the subtracter 3
1 and adder 32, for example, Japanese Patent Application No. 58
The first-order amplitude distortion amount proposed in No. 068635 is Im.
According to the principle expression represented by the absolute value of (−N) −Im (+ N), N = 1, 2, the first-order amplitude distortion amount here is a value obtained by adding Ich and Qch, that is, CI ⁱ (− 1) -CI ⁱ (+
1), the absolute value of CI ⁱ (−2) −CI ⁱ (+2), the absolute value of CQ ⁱ (−1) −CQ ⁱ (+1),
A value obtained by adding the absolute value of CQ ⁱ (−2) −CQ ⁱ (+2) is used. This addition output is input to the comparator 33, compared with the value of the register 34 predetermined by the equalization capability of the amplitude distortion equalization circuits 1 and 2, and the comparison result is sent to the reset circuit 6 as the reset instruction signal 106. To be done.

By the way, in the amplitude equalizer having such a configuration, even if fading exceeding the equalization capability of the amplitude distortion equalization circuits 1 and 2 occurs, a malfunction of the equalization operation of the variable amplitude equalizer 10 is caused. Can be prevented.

That is, also in this case, the frequency spectrum of the transmission signal is changed from one state S1a shown in FIG. 6 (a) to the center frequency fc by the frequency characteristic of the propagation path and is shown in FIG. 6 (b). When received as the other state S2a, the frequency spectrum of the received signal 101 correspondingly corresponds to the center frequency fc and is shown from one state S1b to FIG. 7B as shown in FIG. 7A. The other state S2b will be described below.

In this case, the amplitude characteristic of the received signal 101 is waveform-shaped by the amplitude distortion equalization circuits 1 and 2, and at this time, the first-order distortion in the received signal 101 is completely corrected by the first-order amplitude distortion equalization circuit 2. Since the equalization cannot be completed, the output of the variable amplitude equalizer 10 shows one state S1e shown in FIG. 10A in the frequency spectrum.
Residual strain occurs as shown in. Residual strain detection circuit 5
Then, the first-order amplitude distortion component of this residual distortion is calculated / calculated by calculating each tap coefficient of the transversal filter. As a result, the reset command signal 106 for stopping the secondary amplitude distortion equalization action is generated because the primary amplitude component exceeds the threshold value that is set in advance by the equalization capability of the secondary amplitude distortion equalization circuit 1. Output.

As described above, when the secondary amplitude distortion equalization action is stopped, the concave frequency characteristic due to the malfunction of the secondary distortion amplitude distortion equalization circuit 1 due to the residual distortion is not given, so that the variable amplitude equalizer 10 is not provided. Figure 10 shows the frequency spectrum of the output of
The one state S1e shown in (a) remains. Therefore, the output of the variable amplitude equalizer 10 here is sufficiently subjected to the waveform equalization operation of the waveform equalization circuit 4 as compared with the other state S2e shown in FIG. Therefore, the quality of the received signal 101 is kept good.

Incidentally, when the demodulation output is abnormal due to the synchronization pull-out of the demodulation circuit 3 or the like, in order to facilitate the synchronization pull-in at the time of re-pull-in, the secondary amplitude distortion equalization circuit 1, the primary amplitude distortion equalization circuit 2, And the reset operation is repeatedly performed on the waveform equalization circuit 4.

Although the variable amplitude equalizer 10 is composed of the secondary amplitude distortion equalization circuit 1 and the primary amplitude distortion equalization circuit 2 in the embodiment, the variable amplitude equalizer 10 generally receives the received signal 10.
A variable amplitude equalization (where N is a natural number) on the frequency axis of 1 is variably equalized, and a K-order amplitude distortion equalization circuit based on K of 1 or more and N or less is included. You can In this case, the residual distortion detection circuit 5 uses the demodulated signal 1
The residual strain of 04 was detected, and the residual J of 1 or more and N or less
The reset signal corresponding to the K-order amplitude distortion equalization circuit that outputs the reset instruction signal according to the value of the J-order amplitude distortion based on (where J ≠ K) is the control signal generation circuit 8 It suffices to have a basic function of inputting a control signal to the Kth-order amplitude distortion equalization circuit from the above to stop the equalization of the Kth-order amplitude distortion equalization circuit.

[0034]

As described above, according to the amplitude equalizer of the present invention, even when fading exceeding the equalization capability of the amplitude distortion equalization circuit occurs in the propagation path, the variable amplitude equalizer Since the residual distortion detection circuit for detecting the residual distortion of the output is provided and is controlled so as to stop the operation of the amplitude distortion equalization circuit in the variable amplitude equalizer based on the distortion detection result,
It is possible to prevent malfunction of the equalizing action in the amplitude distortion equalizing circuit. As a result, the quality of the transmission signal (reception signal) is improved.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing the basic configuration of an amplitude equalizer according to an embodiment of the present invention.

2 is a circuit block diagram showing a detailed configuration of a residual distortion detection circuit provided in the amplitude equalizer shown in FIG.

FIG. 3 is a circuit block diagram showing a basic configuration of an amplitude equalizer according to a conventional example.

FIG. 4 is a circuit block diagram showing a basic configuration of an amplitude equalizer according to another conventional example.

FIG. 5 is a circuit block diagram showing a basic configuration of an amplitude equalizer according to another conventional example.

6 shows a frequency spectrum of a transmission signal received and input to the amplitude equalizer shown in FIG. 1 or FIG.
(A) relates to one state, and (b) relates to another state changed from one state.

7 shows a frequency spectrum of a reception signal received and input to the amplitude equalizer shown in FIG. 1 or FIG.
(A) relates to one state, and (b) relates to another state changed from one state.

FIG. 8 is a view of the 2 provided in the amplitude equalizer shown in FIG. 1 or FIG.
The amplitude characteristics of the received signal in the next-amplitude distortion equalization circuit are shown, where (a) relates to one state and (b) relates to another state that has changed from one state.

FIG. 9 is a view showing one included in the amplitude equalizer shown in FIG. 1 or FIG.
The amplitude characteristics of the received signal in the next-amplitude distortion equalization circuit are shown, where (a) relates to one state and (b) relates to another state that has changed from one state.

10A and 10B show a frequency spectrum related to the output of the variable amplitude equalizer included in the amplitude equalizer shown in FIG. 1 or FIG. 5, where FIG. 10A shows one state and FIG. It is about other states that have changed.

[Explanation of symbols]

 1 2nd-order amplitude distortion equalization circuit 2 1st-order amplitude distortion equalization circuit 3 Demodulation circuit 4 Waveform equalization circuit 5 Residual distortion detection circuit 6, 7 Reset circuit 8 Control signal generation circuit 10 Variable amplitude equalizer 31 Subtractor 32 Addition Unit 33 Comparator 34 Register 101 Received signal 102 Output signal 104 Demodulated signal 105 Tap coefficient signal 106 Reset instruction signal 107 Reset signals 108, 109 Control signal

Claims (3)

[Claims] 1. An amplitude equalizer used in a multi-level quadrature amplitude modulation system, a variable amplitude or the like for performing variable equalization of Nth-order amplitude distortion (where N is a natural number) on the frequency axis of a received signal. An equalizer, a demodulation circuit that demodulates the equalized received signal and outputs a demodulated signal, and a control signal generation circuit that generates a control signal for controlling the variable amplitude equalizer according to the demodulated signal A waveform equalization circuit for equalizing waveforms of the demodulated signal on the time axis; a residual distortion detection circuit for detecting residual distortion of the demodulated signal and outputting a reset instruction signal; And a reset circuit that outputs a reset signal for resetting the control signal. 2. The amplitude equalizer according to claim 1, wherein the variable amplitude equalizer includes a Kth-order amplitude distortion equalization circuit based on K of 1 or more and N or less, and the residual distortion detection circuit. Detects the residual distortion of the demodulated signal and outputs the reset instruction signal in accordance with the value of the J-order amplitude distortion based on J (where J ≠ K) of 1 or more and N or less remaining, and the reset circuit According to the reset instruction signal, the control signal from the control signal generating circuit to the K-order amplitude distortion equalization circuit is input to stop the equalization of the K-order amplitude distortion equalization circuit. Amplitude equalizer. 3. The amplitude equalizer according to claim 1 or 2, wherein the waveform equalization circuit outputs a tap coefficient signal indicating a plurality of time-series weighted tap coefficients, and the residual distortion detection is performed. The circuit compares the residual amplitude distortion amount of the demodulated signal obtained by calculating the weighting of the tap coefficient based on the tap coefficient signal with a specified value that depends on the equalization capability of the variable amplitude equalizer. The amplitude equalizer is characterized in that the reset instruction signal is output by the amplitude equalizer.