JPH09274202A - Thin-film transistor array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor array which obviates the occurrence of interlayer short circuit between source electrode lines and holding capacitor electrode lines and lessens the delay of the voltage impressed on source electrodes and the fluctuation of the potential acting on the holding capacitor electrode lines. SOLUTION: This substrate is constituted by forming a transparent insulative substrate, gate electrode lines 3a, 3b disposed in juxtaposition on this transparent insulative substrate, the source electrode line 7, a thin-film transistor, a pixel electrode 9, the holding capacitor electrode line 2 and holding capacitor insulating films as one pixel and arraying these pixels in a two-dimensional array form. In such a case, the holding capacitor insulating films are formed on the transparent insulative substrate side viewed from the pixel electrodes. The multilayered insulating films which consist of the holding capacitor insulating films, the gate insulating film 5a, 3b, semiconductor layers and channel protective films and include the semiconductor layers are formed by being held between the source electrode lines 7 and the holding capacitor electrode lines 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array used in a matrix type display device.

[0002]

2. Description of the Related Art A matrix type display device generally includes a thin film transistor array substrate (hereinafter simply referred to as TFT array substrate) provided with a plurality of source electrode lines, gate electrode lines, thin film transistors (hereinafter simply referred to as TFT) and a color. A display material such as a liquid crystal is sandwiched between two substrates, a counter substrate provided with a filter and a black matrix, and a voltage is selectively applied to the display material. The black matrix formed on the counter substrate is formed to prevent the transmission of light from a region where a voltage is not normally applied to the liquid crystal layer and the incidence of light from the outside on the TFT. In the alignment when such a black matrix is superposed on the TFT array substrate, the deviation is as large as several μm, so that the aperture ratio of the pixel is significantly reduced. In order to improve such a decrease in aperture ratio, a TFT as shown in FIG. 10 in which a black matrix is formed on the TFT array substrate side.
There is an array.

FIG. 10 is a plan view showing one pixel of a conventional TFT array substrate, FIG. 11 is a sectional view taken along line BB of FIG. 10, and FIG. 12 is a sectional view taken along line AA of FIG. . FIG.
A protective film is provided over the entire upper surface of 0,
The protective film is not shown in FIG. 11 and 12, the protective film 12 is shown as the uppermost layer. 10 to 12, 1 is a transparent insulating substrate such as glass, 2 is a storage capacitor electrode line, 7a is a source electrode, 3 is a gate electrode line, 3b ₁ is a gate electrode, Reference numeral 4 is a gate insulating film, 5 is a semiconductor layer, 6 is a channel protective film, 7 is a source electrode line, 7a is a source electrode, 8 is a drain electrode, and 9 is a pixel electrode. is there. In FIG. 10, the gate insulating film 4 and the transparent insulating substrate 1 shown in FIGS. 11 and 12 are not shown in order to clarify the positional relationship of the wiring.

A method of forming such a conventional TFT array substrate will be described.

First, the gate electrode line 3 and the storage capacitor electrode line 2 are formed of the same metal material, for example, chromium. The storage capacitor electrode line 2 forms a storage capacitor between the storage capacitor electrode line 2 and the pixel electrode, thereby preventing a decrease in potential due to a leak current of the TFT,
It has the function of preventing the deterioration of the liquid crystal due to the DC voltage component.
The DC voltage component is a voltage component generated when the center value of the liquid crystal drive voltage applied to the liquid crystal and the center value of the voltage of the common electrode (the counter electrode provided on the counter substrate) are different. . The storage capacitor electrode line 2 has a function as a black matrix that shields the gap between the pixel electrode 9 and the source electrode line 7 in addition to the above function. Therefore, as shown in FIG.
In order to shield the gap between the source electrode line 7 and the pixel electrode 9 from light, the first terminal 2a and the second terminal 2b are arranged in the longitudinal direction of the source electrode line 7 from the side farther from the source electrode line 7 in FIG. It is provided along the direction.

Next, amorphous silicon (hereinafter, simply referred to as a-Si) which is the gate insulating film 4 and the semiconductor layer 5 is used.
After the layer and the channel protection film 6 are formed and the channel protection film is removed, a phosphorus-doped a-Si layer (not shown) serving as a contact layer is formed in the channel portion of the TFT. Next, the semiconductor layer 5 is formed into an island, and unnecessary portions other than the TFT are removed. Further, the pixel electrode 9 is connected to, for example, IT.
After forming the transparent conductive film such as the O film, the source electrode line 7 and the drain electrode 8 are formed. Finally protective film 12
To produce a desired TFT array substrate. Here, the TFT channel portion means the gate electrode 3b of the TFT.
₁ is an overlapping portion of the semiconductor layer 5 and the portion between the source electrode 7a and the drain electrode 8. The channel protective film is for protecting the semiconductor layer of the channel portion during etching of the contact layer. It refers to an insulating film formed in the channel portion.

[0007]

In the conventional TFT array substrate described above, since the gate insulating film, the semiconductor layer and the channel protective film are formed between the storage capacitor electrode line and the source electrode line, the insulating film is formed. The thickness was insufficient, which caused an interlayer short circuit between the source electrode line and the storage capacitor electrode line.

Furthermore, since the insulating film thickness cannot be made sufficiently large, the capacitance of the overlapping portion of the source electrode line and the storage capacitor electrode line becomes large, resulting in a time delay of the voltage applied to the source electrode. However, there is a problem in that the display characteristics are deteriorated because the potential applied to the storage capacitor electrode line varies.

The present invention has been made in order to solve such a problem, does not cause an interlayer short circuit between the source electrode line and the storage capacitor electrode line, and delays or holds the voltage applied to the source electrode with time. An object of the present invention is to provide a TFT array substrate in which the potential applied to the capacitor electrode line is less likely to change.

[0010]

A thin film transistor array substrate of the present invention is provided with a transparent insulating substrate, gate electrode lines arranged in parallel on the transparent insulating substrate, and orthogonal to the gate electrode lines. A source electrode line, a thin film transistor provided at an intersection of the gate electrode line and the source electrode line, a pixel electrode connected to a drain electrode of the thin film transistor, a storage capacitor electrode line, the storage capacitor electrode line, and the storage capacitor electrode line. A thin film transistor array substrate having a storage capacitor insulating film sandwiched between pixel electrodes as one pixel, the pixels being arranged in a two-dimensional array, wherein the storage capacitor insulating film is the transparent insulating substrate rather than the pixel electrode. A multi-layer insulating film formed on the side of the storage capacitor insulating film, the gate insulating film, the semiconductor layer, and the channel protective film. Characterized in that it is formed sandwiched amount electrode line.

Of the storage capacitor electrode line, only the region where the source electrode line and the storage capacitor electrode line overlap each other and the region where the storage capacitor electrode line portion and both ends in the width direction of the source electrode line overlap each other It is preferable that the storage capacitor electrode line be provided in the above because the capacity of the overlapping portion per unit area can be reduced.

It is preferable that the pixel electrode is formed on the same plane as the gate electrode line because it is formed on a plane different from the source electrode line and the source electrode line and the pixel electrode are brought close to each other.

The thin film transistor array substrate of the present invention is
Transparent insulating substrate, gate electrode lines arranged in parallel on the transparent insulating substrate, source electrode lines provided so as to intersect the gate electrode lines, and intersections of the gate electrode lines and the source electrode lines A thin film transistor provided in the thin film transistor, a pixel electrode connected to the drain electrode of the thin film transistor,
A thin film transistor array substrate having a storage capacitor electrode line and a storage capacitor insulating film sandwiched between the storage capacitor electrode line and the pixel electrode as one pixel, the pixels being arranged in a two-dimensional array, The storage capacitor electrode line is formed of the same material as the gate electrode line, (b) the storage capacitor insulating film is formed on the storage capacitor electrode line, and (c) the storage capacitor insulating film is formed on the gate electrode of the thin film transistor. And (d) a gate insulating film and a semiconductor layer, a channel protective film, the source electrode line and the drain electrode are formed in the removed portion, and (e) the storage capacitor insulating film,
It is characterized in that a multi-layered insulating film including the gate insulating film, the semiconductor layer and the channel protective film is formed between the source electrode line and the storage capacitor electrode line.

By providing the storage capacitor insulating film between the gate electrode line and the source electrode line, at least the storage capacitor insulating film and the gate insulating film are provided between the gate electrode line and the source electrode line. It is preferable that two layers of insulating films are formed because a sufficient thickness of the insulating film between the gate electrode line and the source electrode line can be secured.

Among the gate electrode lines, a part of the pixel electrode is provided through an insulating film on the gate electrode line adjacent to the gate electrode line of the pixel to which the pixel electrode belongs in the longitudinal direction of the source electrode line. It is preferable that the gate electrodes are overlapped because the gate electrode line can be effectively used as a light-shielding film and the aperture ratio can be improved.

The storage capacitor electrode line is formed only in a region where the source electrode line and the storage capacitor electrode line overlap with each other, and in a region where the storage capacitor electrode line and both end portions in the width direction of the source electrode line overlap each other. It is preferable that the capacitance between the source electrode line and the storage capacitor electrode line is further reduced.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a TFT array substrate of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing one pixel in the first embodiment of the TFT array substrate of the present invention.
1 is a sectional view taken along the line CC of FIG. 1, FIG. 3 is a sectional view taken along the line AA of FIG. 1, and FIG. 4 is a sectional view taken along the line BB of FIG. 5 is a plan view of the second embodiment of the TFT array substrate of the present invention, FIG. 6 is a sectional view taken along line CC of FIG. 5, and FIG. 7 is a sectional view taken along line AA of FIG. 8 is a sectional view taken along line BB in FIG. 5, and FIG. 9 is a plan view of a third embodiment of the TFT array substrate of the present invention. 1 and 5
9 does not show the protective film as in FIG. 10, but FIG. 2, FIG. 3, FIG. 4, FIG. 6, FIG. 7 and FIG. 8 show the protective film 12 as the uppermost layer.

In FIGS. 1, 5 and 9, in order to clarify the positional relationship of the wiring, the gate insulating film 4, the storage capacitor insulating film 11 and the transparent film shown in FIGS. 2 to 4 and 6 to 8 are shown. The insulating substrate 1 is not shown.

In the following description, one pixel will be described, but in reality, the elements included in the portion surrounded by the gate electrode line and the source electrode line, that is, the gate electrode line, the source electrode line, and the thin film transistor. With the pixel electrode, the storage capacitor electrode line, and the storage capacitor insulating film as one pixel, the pixels are arranged in a two-dimensional array on the transparent insulating substrate.

1 to 9, 3a is a gate electrode line of a pixel electrode in the previous stage (or the next stage) of the pixel electrode 9 shown in FIG. 1, and 3b is the pixel electrode 9 shown in FIG.
1b is a gate electrode line for driving the pixel electrode 3b _{1 and} is connected to the gate electrode line 3b, and is a gate electrode of the TFT for driving the pixel electrode 9 shown in FIG.
Reference numeral 1 is a storage capacitor insulating film (see FIG. 2), and a portion surrounded by a two-dot chain line H is a TFT. The same elements as those in FIGS. 10 to 12 are designated by the same reference numerals.

1 to 8, in addition to the first terminal 2a and the second terminal 2b of FIG.
The third terminal 2c (see FIG. 1) is formed.

In the first mode of the TFT array substrate of the present invention, first, as shown in FIG. 2, the storage capacitor electrode line 2 (the third terminal 2c in FIG. 2) is formed on the transparent insulating substrate 1. It The storage capacitor electrode line is formed in a single layer structure such as a chromium film or a multilayer structure such as a chromium film and an aluminum film. When forming the storage capacitor electrode line, the storage capacitor electrode line is not formed in a portion below the source electrode line 7 and unnecessary for light shielding for the purpose of also serving as a black mask. That is, a portion of the storage capacitor electrode line 2 where the source electrode line 7 and the storage capacitor electrode line overlap,
In addition, it is formed only in a region where the storage capacitor electrode line portion and both ends of the source electrode line in the width direction overlap. Therefore, in FIG. 1, the first terminal 2a and the second terminal 2
b, the third terminal 2c is formed.

As described above, since the storage capacitor electrode line (first terminal 2a, second terminal 2b and third terminal 2c) is formed only in the portion required for light shielding, the area of the overlapping portion is small. It is possible to obtain the effect that the capacity of the overlapping portion is reduced. Even if the area of the overlapping portion is the same as the conventional one, the insulating film between the source electrode line 7 and the storage capacitor electrode line 2 has a multi-layer structure (storage capacitor insulating film, gate insulating film, semiconductor layer and channel protective film). Therefore, the capacity of the overlapping portion is reduced.

After that, on the storage capacitor electrode line 2, as shown in FIG.
As shown in FIG. 4, the storage capacitor insulating film 11 is formed to 0.2 by a sputtering method or a plasma CVD method, for example.
The gate electrode lines 3a and 3b (including the gate electrode 3b ₁ ) are further formed to a thickness of 0.1 to 0.5 μm on the storage capacitor insulating film 11 (see FIG. 2 and FIG. 4). Since the storage capacitor insulating film 11 is formed, a storage capacitor is generated between the storage capacitor electrode line 2 and the gate electrode line 3b, and this storage capacitor changes the pixel voltage caused by the leak current of TFT or the parasitic capacitance. With the function to suppress.

The gate electrode lines 3a and 3b are set to 0.1 to 0.1.
After being formed to a thickness of 0.5 μm, a pixel electrode 9 made of a transparent electrode film such as an ITO film is further formed (see FIGS. 3 and 4), and for example, SiN, SiO ₂ or Ta _{2 is formed.}
The gate insulating film 4 made of O ₅ , for example, the semiconductor layer 5 made of an a-Si layer or a polysilicon layer (poly-Si layer), and the channel protective film 6 made of an insulating film such as SiN or SiO ₂ are formed to have a thickness. 0.1 to 0.7μ respectively
m, 0.03-0.3 μm, and 0.1-0.3 μm
Film is continuously formed by the plasma CVD method so as to obtain (see FIGS. 2 to 4). In this way, since the pixel electrode 9 and the gate electrode line 3b (including the gate electrode 3b ₁ ) are formed on the same plane, the source electrode line 7 and the pixel electrode 9 are formed on different planes. Therefore, the pixel electrode 9 and the source electrode line 7 can be brought close to each other without a pattern defect, and the aperture ratio can be improved. When the pixel electrode 9 is formed, the pixel electrode 9 and the gate electrode line 3a (gate electrode line 3b and gate electrode 3b ₁ ) are formed on the same plane. Therefore, as shown in FIG. The lines are formed at a predetermined interval so as not to short-circuit.

After patterning the channel protective film 6, for example, a contact layer 10 made of phosphorus (P) -doped a-Si is formed, and a source electrode line 7 and a drain electrode 8 made of the same material as the gate electrode line 2 are formed. Formed,
Finally, a protective film 12 is formed to form the TF of the present invention.
The T array substrate is completed. As shown in FIG. 4, a storage capacitor insulating film 11, a gate insulating film 4, a semiconductor layer 5 and a channel protective film 6 are formed as a multilayer insulating film between the source electrode line 7 and the storage capacitor electrode line 2. . That is, since the multi-layer insulating film (including the semiconductor layer) is formed between the source electrode line 7 and the storage capacitor electrode line 2, it is sufficient between the source electrode line 7 and the storage capacitor electrode line 2. This has the effect of forming a large insulating film thickness and thus reducing the capacitance between the source electrode line 7 and the storage capacitor electrode line 2. In addition, the capacity of the overlapping portion per unit area can be reduced.

In the first aspect, the TF of the TFT array substrate
Although the TFT using the channel protective film 6 has been described as T, the gate insulating film, the non-doped a-Si layer, and the phosphorus-doped a-Si layer are continuously formed, and the TFT is formed without using the channel protective film 6. A channel etch type TFT can also be used.

Further, the storage capacitor electrode line 2 and the source electrode line 7
Between both electrode lines at the intersection of and
As shown in, the total thickness of the gate insulating film 4, the storage capacitor insulating film 11 and the channel protective film 6 is 0.7.
It is formed to have a thickness of about 1.0 μm. Therefore, a sufficient film thickness can be obtained as an insulating film between the storage capacitor electrode line 2 and the source electrode line 7. Therefore, it is possible to prevent the occurrence of defects due to a short circuit between the storage capacitor electrode line 2 and the source electrode line 7. In addition, since the insulating film including the storage capacitor insulating film 11, the gate insulating film 4, the semiconductor layer 5, and the channel protective film 6 is thicker than the conventional one, the capacitance at the overlapping portion of the source electrode line and the storage capacitor electrode line is reduced to the conventional one. It can be reduced more than the TFT.

Further, the semiconductor layer 5 and the channel protection film 6
Is formed at the intersection of the storage capacitor electrode line 2 and the source electrode line 7, the insulating film thickness is further increased, and the effect of reducing the capacitance and reducing defects due to short circuits is further improved. Moreover, if the storage capacitor electrode is not formed in an unnecessary portion of the lower layer of the source electrode line by using such a multilayer insulating film structure, the capacitance of the overlapping portion can be further reduced.

Next, the second TFT array substrate of the present invention is used.
This aspect will be described with reference to FIGS. Also in the second aspect, the storage capacitor electrode line is a portion where the source electrode line and the storage capacitor electrode line overlap each other, and the region where the storage capacitor electrode line portion and both end portions in the width direction of the source electrode line overlap each other. Formed only in.

Further, unlike the above-mentioned first mode, FIG.
To the gate electrode line 3a not connected to the pixel electrode 9 of
Part of the pixel electrode (upper part of the pixel electrode 9 in FIG. 5) d ₂ (1
5 μm) is overlaid via an insulating film (gate insulating film 4 in FIG. 6). That is, of the gate electrode lines, the gate electrode line (gate electrode line 3b in FIG. 5) adjacent to the gate electrode line of the pixel to which the pixel electrode belongs (the source electrode line 7 in FIG. The pixel electrode 9 is formed so as to partially overlap the gate electrode line 3a) existing in the direction. By arranging the pixel electrode and the gate electrode line in this way, the gate electrode line can be used as a black mask, and the aperture ratio of the pixel can be improved.

First, as shown in FIGS. 6 and 8,
The storage capacitor electrode line 2 (including the first, second and third terminals) and the gate electrode lines 3a and 3b are provided on the transparent insulating substrate 1.
The gate electrode 3b ₁ (including the gate electrode 3b ₁ ) is formed in a single layer structure such as a chromium film or a multilayer structure such as a chromium film and an aluminum film. When forming the storage capacitor electrode line 2 and the gate electrode lines 3a and 3b, both electrode lines are formed of the same material, and both electrode lines are formed at once.

After that, the storage capacitor insulating film 11 is formed. The storage capacitor insulating film 11 is not formed on the unnecessary portion of the channel portion on the gate electrode (the channel portion is a region surrounded by the chain double-dashed line D in FIG. 5, which corresponds to the upper layer of the gate electrode 3b ₁ ).

Further, a pixel electrode 9 made of a transparent conductive film such as an ITO film is formed, and silicon nitride, Si is used.
A gate insulating film 4 made of O ₂ or Ta ₂ O ₅ , a semiconductor layer 5 made of a non-doped a-Si layer, and a channel protective film 6 made of a polysilicon layer are continuously formed in the same thickness as in the first embodiment. (See Figures 6 and 7). The film forming method at this time may be the same as the film forming method in the first aspect described above, and the thickness of the film may be the same as the thickness in the first aspect described above.

After that, the channel protective film 6 is patterned, and then the contact layer 10 made of a phosphorus-doped a-Si layer is formed (see FIGS. 6 to 8).

After that, a source electrode line 7 and a drain electrode 8 made of the same material as the gate electrode line 2 are formed, and finally, a protective film 12 made of, for example, silicon nitride or SiO ₂ is formed to form a TFT array substrate. Is completed. In this way, as shown in FIG.
Between the storage capacitor electrode line 2 and the storage capacitor insulating film 11
Are formed. Therefore, at least between the gate electrode line 3a and the source electrode line 7, since the two layers of the insulating film of the storage capacitor insulating film 11 and the gate insulating film 4 are formed, the insulating film thickness is sufficient and the interlayer short circuit occurs. Does not occur.

Although the TFT using the channel protective film has been described here, the gate insulating film and the non-doped a-S are used.
A channel-etch type TFT in which an i layer and a phosphorus-doped a-Si layer are continuously formed can also be used. When the TFT array thus formed is used as a TFT array substrate, the second mode is that the storage capacitor electrode line 2 and the source electrode line 7 are used.
Has the same interlayer structure as that of the first aspect described above, and the gate electrode lines 3a and 3b and the storage capacitor electrode line 2 (first
Terminal 2a, second terminal 2b, and third terminal 2c) can be formed of the same material, so that there is an advantage that the process is simplified as compared with the first mode.

FIG. 9 is a plan view showing the third embodiment of the present invention.

According to the third mode, a part of the pixel electrode (on the source electrode 7 side of the pixel electrode 9 in FIG. 9) d ₃ (1 to ₃ μm)
m) is formed so as to overlap the source electrode 7 with an insulating film interposed therebetween. By being formed in this way, the source electrode line can be used as a black mask, and the aperture ratio can be improved.

Of the above-mentioned embodiments, the second embodiment is preferable in terms of cost and display characteristics.

In the second aspect, the storage capacitor electrode line is 0.3 μm thick with a chromium film, the storage capacitor insulating film is a silicon nitride film with a thickness of 0.4 μm, and the gate electrode line is chromium with a transparent insulating substrate. A film having a thickness of 0.3 μm is sequentially formed by a sputtering method and a plasma CVD method. No storage capacitor insulating film 8 is formed in an unnecessary portion. Further, a pixel electrode made of ITO is formed to a thickness of 0.1 μm, and a gate insulating film made of silicon nitride, a semiconductor layer made of a-Si, and a channel protective film made of silicon nitride are respectively formed to a thickness of 0.4 μm.
m, 0.1 μm, and 0.2 μm are sequentially formed by the plasma CVD method. Then, n ⁺ type a-
Contact layer made of Si with a thickness of 0.5 μm plasma C
It is formed by the VD method, and the source electrode line and the drain electrode made of a chromium film are both formed to a thickness of 0.4 μm. Finally, it is most preferable to form a protective film made of silicon nitride so as to cover the entire surface of the transparent insulating substrate, because the capacitance of the overlapping portion and the short circuit defect are reduced without deteriorating the TFT characteristics.

[0043]

According to the present invention, there is no interlayer short circuit between the source electrode line and the storage capacitor electrode line, and the capacity of the overlapping portion between the source electrode line and the storage capacitor electrode line is reduced. Therefore, a light-shielding film (black matrix) can be formed on the TFT array substrate side, and display with a high pixel aperture ratio can be performed.

[Brief description of drawings]

FIG. 1 is a plan view showing a first mode of a thin film transistor array substrate of the present invention.

2 is a cross-sectional view taken along line CC of the thin film transistor array substrate of FIG.

3 is a cross-sectional view taken along the line AA of the thin film transistor array substrate of FIG.

4 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line BB.

FIG. 5 is a plan view showing a second mode of the thin film transistor array substrate of the present invention.

6 is a cross-sectional view taken along line CC of the thin film transistor array substrate of FIG.

7 is a cross-sectional view of the thin film transistor array substrate of FIG. 5 taken along the line AA.

8 is a cross-sectional view taken along line BB of the thin film transistor array substrate of FIG.

FIG. 9 is a plan view showing a third mode of the thin film transistor array substrate of the present invention.

FIG. 10 is a plan view showing an example of a conventional thin film transistor array substrate.

FIG. 11 is a B- of the thin film transistor array substrate of FIG.
It is a B sectional view.

12 is a view of A- of the thin film transistor array substrate of FIG.
FIG. 3 is a sectional view taken along line A.

[Explanation of symbols]

1 Transparent Insulating Substrate 2 Storage Capacitance Electrode Line 2a First Terminal 2b Second Terminal 2c Third Terminal 3 Gate Electrode Line 3a Gate Electrode Line 3b Gate Electrode Line 3b ₁ Gate Electrode 4 Gate Insulating Film 5 Semiconductor Layer 6 Channel Protective film 7 Source electrode line 8 Drain electrode 9 Pixel electrode 11 Storage capacitor insulating film

Claims (7)

[Claims] 1. A transparent insulating substrate, gate electrode lines arranged in parallel on the transparent insulating substrate, source electrode lines provided so as to be orthogonal to the gate electrode lines, and the gate electrode lines and sources. A thin film transistor provided at the intersection of the electrode lines, a pixel electrode connected to the drain electrode of the thin film transistor, a storage capacitor electrode line, and a storage capacitor insulating film sandwiched between the storage capacitor electrode line and the pixel electrode. A thin film transistor array substrate in which one pixel is arranged in a two-dimensional array, and the storage capacitor insulating film is formed on the transparent insulating substrate side as viewed from the pixel electrode. A thin film, characterized in that a multi-layered insulating film consisting of a gate insulating film, a semiconductor layer and a channel protective film is sandwiched between the source electrode line and the storage capacitor electrode line. Transistor array substrate. 2. A portion of the storage capacitor electrode line where the source electrode line and the storage capacitor electrode line overlap each other, and the storage capacitor electrode line portion and both end portions in the width direction of the source electrode line overlap each other. The thin film transistor array substrate according to claim 1, wherein the storage capacitor electrode line is provided only in a region. 3. The thin film transistor array substrate according to claim 1, wherein the pixel electrode is formed on the same plane as the gate electrode line. 4. A transparent insulating substrate, a gate electrode line provided in parallel on the transparent insulating substrate, a source electrode line provided so as to intersect with the gate electrode line, the gate electrode line and the source. A thin film transistor provided at the intersection of the electrode lines, a pixel electrode connected to the drain electrode of the thin film transistor, a storage capacitor electrode line, and a storage capacitor insulating film sandwiched between the storage capacitor electrode line and the pixel electrode. A thin film transistor array substrate in which one pixel is arranged in a two-dimensional array, wherein (a) the storage capacitor electrode line is formed of the same material as the gate electrode line, and (b) on the storage capacitor electrode line. The storage capacitor insulating film is formed on
(C) the storage capacitor insulating film on the gate electrode of the thin film transistor is removed, and (d) the gate insulating film and the semiconductor layer, the channel protective film, the source electrode line and the drain electrode are formed in the removed portion, (E) A multilayer insulating film including the storage capacitor insulating film, the gate insulating film, the semiconductor layer, and the channel protective film is formed by being sandwiched between the source electrode line and the storage capacitor electrode line. Thin film transistor array substrate. 5. The storage capacitor insulating film is provided between the gate electrode line and the source electrode line,
The thin film transistor array substrate according to claim 4, wherein at least two layers of insulating films, the storage capacitor insulating film and the gate insulating film, are formed between the gate electrode line and the source electrode line. 6. A gate electrode line of the gate electrode line, which is adjacent to the gate electrode line of the pixel to which the pixel electrode belongs in the longitudinal direction of the source electrode line, includes one of the pixel electrode lines via an insulating film. 6. The parts according to claim 4, wherein the parts are overlapped.
The thin film transistor array substrate described. 7. The storage capacitor electrode line is provided only in a region where the source electrode line and the storage capacitor electrode line overlap each other, and only in a region where the storage capacitor electrode line and both end portions in the width direction of the source electrode line overlap each other. 7. The thin film transistor array substrate according to claim 4, wherein the thin film transistor array substrate is formed.