JPH10242226A - Semiconductor device - Google Patents

Abstract

(57) Abstract: In a semiconductor device having a multilayer structure, it is an object to easily test circuit characteristics inside the device without increasing the chip size. A plurality of electrodes (pads) are arranged and formed on the entire surface of a wiring pattern of a semiconductor device having a multilayer wiring, and a probe wiring terminal is provided in a lower layer portion thereof. At the time of the probe, the metal of the electrode 2 is locally removed using a processing technique, the probe wiring terminal 3 is exposed, and a probing technique such as an electron beam 7 is applied to the exposed probe wiring terminal 3. To check the characteristics of the circuit. Thereby, the characteristics of the circuit formed in the lower layer or the operation state of the specific wiring become clear.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a multilayer structure having a probe wiring terminal.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become larger and more highly integrated, the number of metal wirings formed in the devices has been increased, and for example, semiconductor devices having four wiring layers have been put to practical use. In addition, the demand for multi-pin semiconductor devices is increasing in these systemized or highly functional semiconductor devices.
00 pins are manufactured.

Further, at present, a five-layer wiring structure has a 10-layer wiring structure.
A semiconductor device with a size of 00 pins is being realized, and the wiring structure and mounting form of the semiconductor device are expected to become more and more complicated in the future.

On the other hand, the demand for high-speed operation of semiconductor devices will continue to increase in the future. To realize this high speed, not only the operation capability of the transistor element is improved but also the wiring structure and mounting form of the entire device. We need to be careful.

Against this background, in recent semiconductor devices, semiconductor devices in which electrodes are arranged over the entire area of the wiring pattern surface have come into practical use.

In such a case, the area in which the electrodes can be arranged is wider than that of a conventional semiconductor device in which the electrodes are arranged only in the peripheral portion of the device. It has become possible to arrange a large number of electrodes without making the pitch narrower than necessary. With such an electrode arrangement, it is possible to realize a 1000-pin semiconductor device.

Further, in a conventional semiconductor device, a circuit inside the device and an electrode (pad) in a peripheral portion are connected to a plurality of circuits via long wires, so that a delay time is generated, and the speed of the semiconductor device is increased. Although this hindered the implementation, in semiconductor devices where electrodes are arranged over the entire wiring pattern surface, the delay between the internal circuit and the electrodes arranged on the internal circuit is short, so that such a delay time is avoided. can do.

Further, when such a semiconductor device is mounted on a mounting substrate, flip-chip mounting in which electrodes on the device side and electrodes on the substrate side are connected by bumps is applied. This flip-chip mounting makes it easier to optimize the characteristic impedance between the semiconductor device and the substrate and makes it easier to increase the speed of the device, compared to the wire bonding method or the ILB method as a conventional electrical connection method. Can be realized.

For the above reasons, semiconductor devices in which electrodes are arranged over the entire surface of a wiring pattern and related technologies have heretofore been used as an important technology for increasing the number of pins and increasing the speed of a semiconductor device with higher performance. It has become.

FIG. 9 is a plan view of a semiconductor device for explaining an example of the related art. As shown in FIG. 9, in a conventional semiconductor device 11 having a multilayer structure, a plurality of electrodes 12 for connecting to an internal circuit or an external circuit, and an internal circuit or an external circuit for investigating circuit characteristics inside the device. And a plurality of probe wiring terminals 13 provided between the electrodes 12 for connection with the probe.

In the semiconductor device 11, in order to test the electrical characteristics and the like of the lower layer circuit, a thin probe needle is directly applied to the probe wiring terminal 13 connected to the lower layer circuit, or an electron is applied thereto. The measurement is performed by hitting a beam.

[0012]

In the above-mentioned conventional semiconductor device, multilayer wiring has been advanced, and the area of the lower wiring covered by the upper wiring has been increased with the progress of multi-layer wiring. EB using electron beam
It has become difficult to apply the electrical characteristic measurement technique by the testing method to the lower layer wiring, and it has become difficult to investigate the circuit characteristics inside the semiconductor device or the operation state of a specific wiring.

That is, in order to measure the characteristics of a circuit hidden in the upper layer wiring or the operating state of a specific wiring, the wiring for the probe is pulled out from the corresponding lower circuit or wiring to the upper layer, and the probe wiring is connected to the upper layer. In order to avoid hiding in the wiring, a method of arranging between the upper wiring and the upper wiring must be adopted. If the probe wiring is drawn out to the upper layer, the above-described electrical characteristic measurement technique can be easily applied, and the characteristics of the circuit in the lower layer and the operation state of the wiring can be measured.

When such a method or means is applied to a semiconductor device in which electrodes are arranged over the entire area of the wiring pattern, the probe wiring terminals are arranged between the electrodes as shown in FIG. Will be.

However, in such an arrangement structure,
It is necessary to provide a probe wiring region between the electrodes, and as a result, there arises a problem that the chip size of the semiconductor device increases.

An object of the present invention is to provide a semiconductor device capable of easily testing circuit characteristics and the like inside the device without increasing the chip size.

[0017]

According to the present invention, there is provided a semiconductor device comprising:
A plurality of electrodes formed on a pattern wiring surface for connecting a power supply line, a GND line, and a signal line used for forming a circuit function, and a plurality of probes formed on an insulating layer below the plurality of electrodes. And a wiring terminal for use.

In the semiconductor device of the present invention, the plurality of electrodes form a window corresponding to a portion directly above the plurality of probe wiring terminals, and the electron beam is applied to the surface of the probe wiring terminal through the window. Is formed to check circuit characteristics.

Further, the plurality of probe wiring terminals in the semiconductor device of the present invention are formed in multiple layers.

Further, the plurality of probe wiring terminals in the semiconductor device of the present invention include a first wiring terminal not used for forming a circuit and a second wiring terminal used for forming a circuit mixedly arranged. Formed.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor device for explaining a first embodiment of the present invention. As shown in FIG. 1, a semiconductor device 1 according to the present embodiment has a plurality of electrodes 2 formed over the entire area of a wiring pattern surface, and a plurality of probe wiring terminals 3 below each electrode 2. It is provided. A signal wiring (not shown) pulled up from a lower layer for the purpose of a probe and a probe wiring terminal 3 not used for the formation of a circuit function are provided in a lower layer portion of the electrode 2. They are mixed. When these wirings or terminals are to be probed, a part of the electrode 2 is locally removed to expose the corresponding probe wiring terminal 3.

That is, since the probe wiring terminal 3 is disposed below the electrode 2, the probe wiring terminal 3 is covered by the metal of the electrode 2 when viewed from above the surface of the semiconductor device 1. I have.

There are various methods for locally removing the metal wiring used for the electrode 2.
First, there is a method using a focused ion beam (FIB). The FIB technique is used in a wide range of applications such as wiring correction and failure analysis of the semiconductor device 1. The FIB technique irradiates Ga ions in a vacuum to form a local region (up to 15 μm □) can be accurately removed.

Second, there is a method called gas assist FIB. This technology irradiates the workpiece with Ga ions in an atmosphere of gas selected according to the material of the workpiece, thereby accelerating the processing of the corresponding workpiece, and performing short-time local processing. Enable. For example, when the workpiece is aluminum (Al), chlorine, bromine, iodine, or the like is selected. When the workpiece is a protective film or an interlayer film, a halogen-based gas such as XeF ₂ is selected.

Thirdly, there is a local removal method using an excimer laser. This excimer laser has an oscillation wavelength shorter than that of a YAG laser (oscillation wavelength: 1060 nm) conventionally used for processing a semiconductor device (when KrF is used as an excitation gas, 248 nm when ArF is used). 193 nm), since the absorptance in the surface layer portion of the material to be processed is high, without affecting the peripheral portion by heat,
Accurate local processing (up to 30 μm □) becomes possible.

FIGS. 2A and 2B are partially enlarged plan views of the semiconductor device including the electrodes in FIG.
It is -B sectional drawing. As shown in FIGS. 2A and 2B,
The electrode 2 is disposed on the entire wiring pattern surface of the semiconductor device 1, and the probe wiring terminal 3 is formed in the insulating film 4 which is a lower layer of the electrode 2. In order to perform a circuit check using the probe wiring terminal 3, the electrode unnecessary portion 2a of the electrode 2 is removed using the above-described method.

Thereafter, the insulating film 4 on the probe wiring terminal 3 is formed.
Is removed by a method such as etching, and the internal circuit is checked using an electron beam or the like.

FIGS. 3A and 3B are cross-sectional views of a typical semiconductor device shown in the order of steps for explaining a second embodiment of the present invention. First, as shown in FIG. 3A, the semiconductor device in the present embodiment is an example of a two-layer structure in which a lowermost-layer probe wiring terminal 5 is further provided below the probe wiring terminal 3. 2 shows a cross section of a part before processing over two electrodes 2 in FIG. Reference numeral 6 denotes an electrode wiring, and the insulating layer is omitted.

Next, as shown in FIG. 3 (b), the electrode 2 is locally removed from above by FIB (focused ion beam: not shown), and the unnecessary portion 2a is removed. Further, the unnecessary portion 3a of the probe wiring terminal 3 is removed to expose the upper surface of the lowermost probe wiring terminal 5.

After the unnecessary portions 2a and 3a of the electrodes 2 and the probe wiring terminals 3 have been removed in this manner, the exposed lowermost probe wiring terminals 5 are irradiated with the probe electron beam 7. And measure the electrical characteristics. In addition, the remaining probe wiring terminals 3
Is irradiated with the probe electron beam 7 to measure the electrical characteristics. Here, the portions 2a to be removed from the electrode 2 toward the lowermost-layer probe wiring terminal 5 are removed.
3a is reduced.

That is, when performing a probe analysis on the semiconductor device, the unnecessary portion 2a of the electrode 2 described above is removed by a processing technique such as FIB, gas assist FIB, or excimer laser. At this time, the insulating film is removed together with the part 2a of the electrode 2. Further, the probe wiring terminal 3 in the upper layer is also removed by the same processing technique, so that the lowermost probe wiring terminal 5 in the lower layer is exposed. After the exposure, the electrical measurement of the lowermost-layer probe wiring terminal 5 is performed using a probing technique.

In this embodiment, the probe electron beam 7 is irradiated, and the operation state of the lowermost probe wiring terminal 5 is observed by the EB probing method. This lowermost-layer probe wiring terminal 5 is connected to a lower-layer circuit, and its operation status reflects a malfunction operation of the corresponding lower-layer circuit.

On the other hand, since the processing of the electrode 2 is local, there is no effect when the semiconductor device 1 is mounted on a substrate or the like. Therefore, after processing the electrode 2 and analyzing the probe, the semiconductor device 1 can be mounted on a substrate. In actual mounting, it is preferable to apply an insulator to each processed portion to protect the probe wiring terminal 3 and the lowermost probe wiring terminal 5. Note that the same processing technology as that of the present embodiment can be applied even if the wiring arranged in the lower layer of the electrode 2 is a signal wiring used for forming a circuit function.

FIGS. 4A and 4B are a partially enlarged plan view of a semiconductor device and a cross-sectional view taken along the line CC, respectively, for explaining a third embodiment of the present invention. FIG. 4 (a),
As shown in (b), the present embodiment is also an example in which the electrode 2 is arranged over the entire wiring pattern surface of the semiconductor device 1.
In this case, a window 8 is formed in a part of the electrode 2. Moreover, the window 8 is formed corresponding to the probe wiring terminal 3 formed in the lower insulating film 4.

In this case, the probe access to the probe wiring terminal 3 may be performed by removing the portion of the insulating film 4 on the probe wiring terminal 3 or may be performed with the insulating film 4 left. Alternatively, the irradiation may be performed by irradiating a probe electron beam.

First, as shown in FIG. 4A, in this embodiment, the probe wiring terminal 3 in the lower layer can be seen from the window 8 opened in a part of the electrode 2.

Next, as shown in FIG.
Is covered with the insulating film 4. For this reason,
Even if this semiconductor device 1 is mounted on a substrate, the probe wiring terminals 3
Is not damaged or short-circuited with the adjacent wiring or the electrode 2. In addition, since the semiconductor device 1 has a structure in which the window 8 is formed only in a part of the electrode 2, there is no hindrance to the mounting on the substrate, and the semiconductor device 1 is similar to FIGS. 2A and 2B described above. , Can be implemented.

FIG. 5 is a sectional view of a semiconductor device for explaining a fourth embodiment of the present invention. As shown in FIG. 5, this embodiment is a modification of FIGS. 4A and 4B, and also shows the state of the probe of FIGS. 4A and 4B. I have. In other words, FIG. 5 shows an example in which the probe wiring terminal 3 is irradiated with the probe electron beam 7 with the insulating film 4 of the window 8 interposed therebetween.

FIG. 6 is a sectional view of a semiconductor device for explaining a fifth embodiment of the present invention. As shown in FIG. 6, the present embodiment is different from the above-described embodiment of FIG. 5 in that the insulating film 4 under the window 8 is removed and a hole 9 is formed. This is an example in which the probe electron beam 7 is directly applied to the exposed probe wiring terminal 3 without intervention.

FIG. 7 is a plan view of a semiconductor device for explaining a sixth embodiment of the present invention. As shown in FIG. 7, the semiconductor device 1 in the present embodiment has a plurality of probe wiring terminals 3 and 10 formed in a lower layer portion of the electrode 2 mixedly arranged, and is particularly used for forming a circuit. The probe wiring terminals 3 only for the purpose of the probe and the probe wiring terminals 10 pulled up from the lower layer and used for forming a circuit are mixedly arranged. Note that these terminals may be arranged in each wiring layer as needed.

In short, this embodiment is different from the first embodiment described above in that the first probe wiring terminal 3 is used to form a circuit function and is pulled up from a lower layer for the purpose of a probe. That is, the second wiring terminal 10 for probe is mixedly arranged. When the terminals 3 and 10 are probed, a part of the electrode 2 is locally removed by using the above-described processing technique to expose the corresponding terminal, and thereafter, the probe needle or the electron beam for the probe is used. Probe the corresponding terminal using.

FIG. 8 is a plan view of a semiconductor device for explaining a seventh embodiment of the present invention. As shown in FIG. 8, in the semiconductor device 1 in the present embodiment, a plurality of electrodes 2 are formed around the wiring pattern surface, and a plurality of probe wiring terminals 3 are provided below the electrodes 2. It is a thing.

The present embodiment shows that the present invention is applicable to a conventional semiconductor device having a configuration in which a plurality of electrodes 2 are arranged around a wiring pattern surface. Of course, also in the present embodiment, the probe wiring terminal 3 and the probe wiring terminal 10 from the lower layer may be mixed.

Although several embodiments have been described above, it goes without saying that these embodiments may be combined.

For example, a combination of FIG. 2 and FIG.
Modifications such as a combination of the example of FIG. 4 and FIG. 5 or FIG. 6 are also conceivable.

That is, when the probe analysis is performed on the semiconductor device 1 shown in FIGS. 4A and 4B, first, as shown in FIG. 3 is irradiated with an electron beam 7. If the probe wiring terminal 3 is located at a depth where the electron beam 7 to be irradiated reaches, it is not necessary to remove the insulating film 4 because the operation state can be measured without removing the insulating film 4.

On the other hand, when the probe wiring terminal 3 is located at a depth where the irradiated electron beam 7 does not reach, as shown in FIG. 6, a processing technique such as FIB, gas assist FIB or excimer laser is used. Then, the insulating film 4 attached to the window 8 is removed to form a hole 9. afterwards,
The EB probing technique is applied to the exposed probe wiring terminals 3 to perform operation analysis and the like.

[0049]

As described above, in the semiconductor device of the present invention, a plurality of probe wiring terminals are arranged in a lower layer of an electrode for circuit connection, and are located immediately above the probe wiring terminals. By removing a part of the electrode to be used, the entire area of the wiring pattern surface can be effectively used, so that it is possible to easily test the circuit characteristics and the like inside the device without increasing the chip size.

Further, the present invention has an effect that the chip size can be further reduced by forming the probe wiring terminals arranged in the lower layer of the electrode in multiple layers.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device for describing a first embodiment of the present invention.

2 is a diagram illustrating a partially enlarged plane of a semiconductor device including an electrode in FIG. 1 and a BB cross section thereof.

FIG. 3 is a cross-sectional view of a semiconductor device shown in a process order for describing a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a partially enlarged plane of a semiconductor device and a CC cross section thereof for describing a third embodiment of the present invention;

FIG. 5 is a cross-sectional view of a semiconductor device for describing a fourth embodiment of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor device for describing a fifth embodiment of the present invention.

FIG. 7 is a plan view of a semiconductor device for describing a sixth embodiment of the present invention.

FIG. 8 is a plan view of a semiconductor device for explaining a seventh embodiment of the present invention.

FIG. 9 is a plan view of a semiconductor device for explaining an example of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Electrode (pad) 3,10 Wiring terminal for probe 4 Insulating film 5 Wiring terminal for lowermost probe 6 Wiring for electrode 7 Electron beam for probe 8 Window part 9 Hole part

Claims (4)

[Claims] 1. A power supply wiring used for forming a circuit function,
It has a plurality of electrodes formed on a pattern wiring surface for connecting a GND wiring and a signal wiring, and a plurality of probe wiring terminals formed on an insulating layer below the plurality of electrodes. Semiconductor device. 2. The method according to claim 1, wherein the plurality of electrodes form a window corresponding to a portion directly above the plurality of probe wiring terminals, and irradiate the surface of the probe wiring terminal with an electron beam through the window. 2. The semiconductor device according to claim 1, wherein circuit characteristics are checked. 3. The semiconductor device according to claim 1, wherein the plurality of probe wiring terminals are formed in multiple layers. 4. The plurality of probe wiring terminals according to claim 1, wherein a first wiring terminal not used for forming a circuit and a second wiring terminal used for forming a circuit are mixedly arranged. Semiconductor device.