JPH1154616A - Semiconductor integrated circuit device manufacturing method and semiconductor manufacturing device - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] In a wiring technology for a semiconductor integrated circuit device,
Provided is a technique capable of improving the flatness of an OG film. SOLUTION: After forming a first-layer SOG film 15, a semiconductor wafer is subjected to a pre-bake treatment at a temperature of 80 to 230 ° C. for 60 to 120 seconds, so that impurities adhering to the surface of the first-layer SOG film 15 are formed. Alternatively, moisture is sublimated to improve the wettability of the surface of the first SOG film. Next, after cooling the semiconductor wafer to a room temperature of about 23 ° C., an SOG liquid is applied on the semiconductor wafer by a spin coating method, and then the semiconductor wafer is baked to form a second-layer SOG film. 16 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device and a semiconductor manufacturing apparatus, and more particularly, to a method for electrically insulating a semiconductor element from a wiring layer or between upper and lower wiring layers. The present invention relates to a technique which is effective when applied to a semiconductor integrated circuit device having an interlayer insulating film.

[0002]

2. Description of the Related Art An SOG (Spin On Glass) film is formed to be thick at a low base pattern and thin at a high base pattern. It is an indispensable film as an interlayer insulating film in a wiring process of a circuit device.

The SOG film is usually formed of a silicon compound [R _n S
i (OH) _4-n ; silanol] and an additive are dissolved in an organic solvent, and an SOG solution is applied on the semiconductor wafer by a spin coating method, followed by baking the semiconductor wafer. You. The OH groups in the SOG solution disappear during the baking process, and finally an SOG film composed of silicon oxide (SiO ₂ ) is obtained.

The SOG film is described in, for example, “Monthly Semiconductor World” published by Press Journal.
1989, extra edition, pages 291 to P295, or "LSI Process Engineering" issued by Ohmsha, issued on August 20, 1991, page 144.

[0005]

Further, in order to improve the flatness of the SOG film, a method of forming the SOG film into a laminated structure in which, for example, two layers are stacked has been studied. However, after performing the first SOG liquid application and the first baking process to form the first SOG film, the second SOG film is formed.
While waiting for the application of the solution, impurities or moisture in the air adhere to the surface of the first SOG film and the first SOG film is removed.
This deteriorates the wettability of the surface of the OG film. For this reason,
When the second SOG liquid is applied to the surface of the first SOG film, a region where the SOG liquid is repelled and cannot be applied is formed, causing a problem that the flatness of the second SOG film is deteriorated. Would.

An object of the present invention is to provide a technique for improving the flatness of an SOG film in a wiring technique of a semiconductor integrated circuit device.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, an interlayer insulating film provided between a semiconductor element and a wiring layer or a part of an interlayer insulating film provided between upper and lower wiring layers is formed. When forming a stacked SOG film,
A step of performing a pre-bake treatment on the semiconductor wafer, a step of cooling the semiconductor wafer, a step of applying a coating liquid containing a silicon compound as a main component on the semiconductor wafer by a spin coating method, and a step of performing a bake treatment on the semiconductor wafer It has.

According to the above-described means, impurities or moisture in the air attached to the surface of the lower SOG film are sublimated by the pre-bake treatment, and the wettability of the surface of the lower SOG film is improved. Even if an SOG liquid for forming the upper SOG film is applied to the surface of the SOG film, the repelling of the SOG liquid on the surface of the lower SOG film can be prevented, and the flatness of the upper SOG film can be improved. Can be improved.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) A method of forming an SOG film having a two-layer structure according to an embodiment of the present invention is shown in FIG.
Schematic diagram of the unit of the coating apparatus, and step 1 shown in FIG.
This will be described with reference to steps 00 to 107.

First, as shown in FIG. 1, a mechanism for loading and unloading a semiconductor wafer (a loading section and an unloading section), a mechanism for performing a pre-bake process on a semiconductor wafer (a pre-bake section), and a mechanism for cooling a semiconductor wafer. (Cooling unit), a mechanism (coating unit) for applying the SOG liquid onto the semiconductor wafer,
The semiconductor wafer is transported to an SOG coating apparatus equipped with a mechanism (bake unit) for performing a baking process on the semiconductor wafer (step 100). Thereafter, the SOG liquid is applied to the semiconductor wafer by a spin coating method (Step 101), and then the semiconductor wafer is baked (Step 10).
2) A first-layer SOG film is formed. The baking process is performed by gradually increasing the temperature. For example, a semiconductor wafer is first heat-treated at a temperature of 80 ° C. for 120 seconds, subsequently at a temperature of 200 ° C. for 120 seconds, and finally at a temperature of 450 ° C. for 30 seconds. It is applied to

Next, for example, 80 to 23
After performing a pre-bake treatment at a temperature of 0 ° C. for 60 to 120 seconds (step 103), the semiconductor wafer is cooled and returned to a room temperature of about 23 ° C. (step 104). Next, after applying the SOG liquid on the semiconductor wafer by the spin coating method (Step 10).
5) A baking process is performed on the semiconductor wafer (step 106) to form a second-layer SOG film. The conditions for the baking process for the second-layer SOG film are the same as the conditions for the baking process for the first-layer SOG film.

As described above, according to the first embodiment, 1
Impurities or moisture in the air attached to the surface of the first layer of SOG film are sublimated by pre-baking to improve the wettability of the surface of the first layer of SOG film.
Even if the SOG liquid is applied to the surface of the OG film, the first layer of SOG
Repelling of the SOG liquid on the surface of the film can be prevented, and the flatness of the second-layer SOG film can be improved.

Next, the two-layered S
CMOSFET (Compleme) to which the method of forming an OG film is applied
ntary Metal Oxide Semiconductor Field Effect Trans
The manufacturing method of istor) will be described with reference to FIGS. In the figure, Q ₁ is an n-channel MISFET (Metal In
sulator Semiconductor FET), Q ₂ is a p-channel type M
ISFET.

First, as shown in FIG. 3, a p-type well 2 and an n-type well 3 are formed on a main surface of a semiconductor substrate 1 made of n-type silicon single crystal by a self-alignment method. A thickness of about 400 n for element isolation on the surface of each of the second and n-type wells 3
An m field insulating film 4 is formed.

Next, a p-type impurity (for example, boron (B)) is introduced into each channel region of the p-type well 2 and the n-type well 3 to form the threshold voltage control layer 5, and then the semiconductor is formed. A gate insulating film 6 is formed on the surface of the substrate 1 and then a CVD (Chemical Vapor Depos) is formed on the semiconductor substrate 1.
A polycrystalline silicon film (not shown) to which phosphorus (P) is added is deposited by the ition method.

Next, the polycrystalline silicon film is etched using the patterned photoresist as a mask,
A gate electrode 7 made of a polycrystalline silicon film is formed.

Next, as shown in FIG. 4, an n-type impurity (for example, P) is added to the p-type well 2 using the gate electrode 7 as a mask.
To form a low-concentration n ⁻ -type semiconductor region 8 that forms part of the source region and the drain region of the n-channel MISFET Q ₁ . Similarly, using the gate electrode 7 as a mask, a p-type impurity (for example, boron fluoride (BF ₂ )) is introduced into the n-type well 3 to form a p-channel MISFET Q ₂
A low concentration p ⁻ -type semiconductor region 9 constituting a part of the source region and the drain region is formed.

Next, the silicon oxide film deposited on the semiconductor substrate 1 by the CVD method is etched by the RIE (Reactive Ion Etching) method to form a sidewall spacer 10 on the side wall of the gate electrode 7.

Next, an n-type impurity (for example, arsenic (As)) is introduced into the p-type well 2 using the gate electrode 7 and the sidewall spacer
A source region of ISFETQ _1, to form a high-concentration n ⁺ -type semiconductor region 11 constituting the other part of the drain region.

Similarly, using the gate electrode 7 and the sidewall spacer 10 as a mask, a p-type impurity (for example, BF ₂ ) is introduced into the n-type well 3 to form a p-channel MIS.
A source region of the FETs Q _2, to form a high-concentration p ⁺ -type semiconductor region 12 constituting the other part of the drain region.

Next, a titanium film (not shown) having a thickness of 30 to 50 nm is deposited on the semiconductor substrate 1 by a sputtering method or a CVD method. Then, in a nitrogen atmosphere, 60
Heat treatment (first annealing) is performed at a temperature of 0 to 700 ° C. By this first annealing, a high-resistance titanium silicide film (TiSi _x (0 <x <2)) is converted into an n-channel type M
Surface of gate electrode 7 and surface of n ⁺ type semiconductor region 11 of ISFET Q ₁ , and p-channel type MISFET
Surface of gate electrode 7 of Q ₂ and p ⁺ type semiconductor region 12
Formed on the surface of

Next, the unreacted titanium film is replaced with H ₂ O ₂ : NH
After removal with ₄ OH: H ₂ O solution, 800
Heat treatment (second annealing) at a temperature of ~ 900 ° C;
The high-resistance titanium silicide film is changed to a low-resistance titanium silicide film (TiSi ₂ ) 13.

Next, TEOS (Tetra Ethyl Ortho Silicon)
cate; Si (OC ₂ O ₅ ) ₄ )) A lower silicon oxide film 14 is deposited on the semiconductor substrate 1 by a plasma CVD method using a gas as a raw material. Next, the first embodiment
After the first-layer SOG film 15 and the second-layer SOG film 16 were sequentially formed on the semiconductor substrate 1 by using the two-layer SOG film formation method described above, TEOS gas was again used as a raw material. An upper silicon oxide film 17 is deposited on the semiconductor substrate 1 by a plasma CVD method. As a result, an interlayer insulating film having a laminated structure including the upper silicon oxide film 17, the second SOG film 16, the first SOG film 15, and the lower silicon oxide film 14 is formed.

The second-layer SOG film 16 and the first-layer SOG film
The G film 15 is formed by forming an upper silicon oxide film 17 and a lower silicon oxide film 14 formed by a plasma CVD method.
By sandwiching the SOG film, it is possible to reinforce the properties of the SOG film, which is porous and inferior in terms of dielectric strength or mechanical strength.

The thicknesses of the upper silicon oxide film 17 and the lower silicon oxide film 14 are, for example, 60
0 nm and 350 nm, and the second SOG film 16
And the total thickness of the first-layer SOG film 15 is, for example, about 200 n.
m.

Thereafter, as shown in FIG. 5, using the patterned photoresist as a mask, the upper silicon oxide film 17, the second SOG film 16, the first SOG film 1
After the interlayer insulating film having a laminated structure including the silicon oxide film 5 and the lower silicon oxide film 14 is etched to form contact holes 18 on the gate electrode 7, the n ⁺ type semiconductor region 11 and the p ⁺ type semiconductor region 12, By etching a metal film (not shown) deposited on the interlayer insulating film to form the wiring layer 19, the two-layer structure S of the first embodiment is formed.
A CMOSFET to which the OG film forming method is applied is completed.

In the first embodiment, the second-layer SOG film 1
6, the pre-baking process and the cooling were performed before the SOG liquid was applied. However, as shown in FIG. 6, the pre-baking was performed before the SOG liquid was applied when the first SOG film 15 was formed. Processing and cooling may be performed.

(Embodiment 2) A method of forming an SOG film having a two-layer structure according to another embodiment of the present invention will be described with reference to steps 100 to 108 shown in FIG.

First, similarly to the first embodiment, after the semiconductor wafer is transferred to the SOG coating apparatus (step 100),
An SOG liquid is applied onto a semiconductor wafer by a spin coating method (Step 101), and then the semiconductor wafer is baked (Step 102) to form a first-layer SOG film.

Next, as in the first embodiment, when forming the second-layer SOG film, as shown in FIG. 7, a pre-bake treatment (step 10) is performed before the step 106 of applying the SOG liquid.
4) and cooling (step 105), but irradiating the semiconductor wafer with far ultraviolet rays before the pre-bake processing 103
Is added.

As described above, according to the second embodiment, 1
Impurities or moisture in the air adhering to the surface of the first SOG film are sublimated by the pre-bake treatment, and further irradiation with far ultraviolet light is used to add carbon-based adhering to the surface of the first SOG film. Impurities are easily removed.

In the second embodiment, far-ultraviolet irradiation, pre-bake treatment, and cooling were performed before applying the SOG liquid when forming the second-layer SOG film. However, as shown in FIG. Irradiation with far ultraviolet rays, pre-bake treatment, and cooling may be performed before applying the SOG liquid when forming the SOG film of the eyes.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0038]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the impurities or moisture in the air attached to the surface of the lower SOG film are sublimated, and the wettability of the surface of the lower SOG film is improved. Even if an SOG solution for forming an upper SOG film is applied to the surface of
The repelling of the G solution can be prevented, and the flatness of the upper SOG film can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic view of a unit of an SOG coating apparatus according to an embodiment of the present invention.

FIG. 2 shows a two-layer SOG according to an embodiment of the present invention.
It is a process drawing explaining the formation method of a film.

FIG. 3 shows a two-layer SOG according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a CMOSFET using a film.

FIG. 4 shows a two-layer SOG according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a CMOSFET using a film.

FIG. 5 shows a two-layer SOG according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a CMOSFET using a film.

FIG. 6 shows a two-layer SOG according to an embodiment of the present invention.
It is a process drawing explaining the formation method of a film.

FIG. 7 shows a two-layered SO according to another embodiment of the present invention.
FIG. 4 is a process diagram illustrating a method for forming a G film.

FIG. 8 shows a two-layer SO according to another embodiment of the present invention.
FIG. 4 is a process diagram illustrating a method for forming a G film.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 p-type well 3 n-type well 4 field insulating film 5 threshold voltage control layer 6 gate insulating film 7 gate electrode 8 n ^- type semiconductor region 9 p ^- type semiconductor region 10 sidewall spacer 11 n ⁺ type semiconductor Region 12 p ⁺ type semiconductor region 13 Titanium silicide film 14 Lower silicon oxide film 15 First SOG film 16 Second SOG film 17 Upper silicon oxide film 18 Contact hole 19 Wiring layer

Claims (8)

[Claims] 1. A semiconductor integrated circuit device for forming a stacked SOG film constituting a part of an interlayer insulating film provided between a semiconductor element and a wiring layer or an interlayer insulating film provided between upper and lower wiring layers. The step of performing a pre-bake treatment on a semiconductor wafer when forming the SOG film of each layer, a step of cooling the semiconductor wafer, and a step of applying a coating liquid containing a silicon compound as a main component on the semiconductor wafer. A method for manufacturing a semiconductor integrated circuit device, comprising a step of applying and a step of baking the semiconductor wafer. 2. A semiconductor integrated circuit device for forming a stacked SOG film constituting a part of an interlayer insulating film provided between a semiconductor element and a wiring layer or an interlayer insulating film provided between upper and lower wiring layers. The method of manufacturing, when forming the SOG film of each layer other than the lowermost layer, a step of performing a pre-bake treatment on a semiconductor wafer, a step of cooling the semiconductor wafer, and a silicon compound as a main component on the semiconductor wafer A method for manufacturing a semiconductor integrated circuit device, comprising: a step of applying a coating liquid obtained by the above-described method; and a step of baking the semiconductor wafer. 3. A semiconductor integrated circuit device for forming a stacked SOG film constituting a part of an interlayer insulating film provided between a semiconductor element and a wiring layer or an interlayer insulating film provided between upper and lower wiring layers. A method of irradiating a semiconductor wafer with far ultraviolet rays when forming an SOG film of each layer; and a step of performing a pre-bake treatment on the semiconductor wafer;
A semiconductor integrated circuit device, comprising: a step of cooling the semiconductor wafer; a step of applying a coating liquid containing a silicon compound as a main component on the semiconductor wafer; and a step of baking the semiconductor wafer. Manufacturing method. 4. A semiconductor integrated circuit device for forming a stacked SOG film constituting a part of an interlayer insulating film provided between a semiconductor element and a wiring layer or an interlayer insulating film provided between upper and lower wiring layers. A method of irradiating a semiconductor wafer with far ultraviolet rays when forming the SOG film of each layer other than the lowermost layer, a step of performing a pre-bake treatment on the semiconductor wafer, and a step of cooling the semiconductor wafer. A method of applying a coating liquid containing a silicon compound as a main component on the semiconductor wafer, and a step of baking the semiconductor wafer. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a temperature and a time of said pre-bake processing are 80 to 230 ° C. and 60 to 120 seconds, respectively. A method for manufacturing a semiconductor integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the temperature of the baking process is 80 ° C. to 450 ° C. Manufacturing method. 7. A semiconductor manufacturing apparatus for forming an SOG film constituting a part of an interlayer insulating film provided between a semiconductor element and a wiring layer or an interlayer insulating film provided between upper and lower wiring layers, A mechanism for performing a pre-bake process on the semiconductor wafer, a mechanism for cooling the semiconductor wafer, a mechanism for applying a coating liquid on the semiconductor wafer, and a mechanism for performing a bake process on the semiconductor wafer. Semiconductor manufacturing equipment. 8. A semiconductor manufacturing apparatus for forming an SOG film constituting a part of an interlayer insulating film provided between a semiconductor element and a wiring layer or an interlayer insulating film provided between upper and lower wiring layers, A mechanism for irradiating the semiconductor wafer with far ultraviolet light, a mechanism for performing a pre-bake process on the semiconductor wafer,
A semiconductor manufacturing apparatus comprising: a mechanism for cooling the semiconductor wafer; a mechanism for applying a coating liquid on the semiconductor wafer; and a mechanism for baking the semiconductor wafer.