KR100799100B1 - Method for measuring polysilicon depletion rate and manufacturing test pattern therefor - Google Patents
Method for measuring polysilicon depletion rate and manufacturing test pattern therefor Download PDFInfo
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Abstract
본 발명은 폴리실리콘공핍율 측정이 간단하면서, 시간 및 자본을 줄일 수 있는 폴리실리콘공핍율 측정방법 및 그를 위한 테스트 패턴의 제조방법을 제공하기 위한것이다. 본 발명은 n+폴리실리콘 및 p+폴리실리콘의 듀얼폴리게이트가 형성된 MOS 캐패시터 소자를 형성하는 단계, 상기 캐패시터 소자의 C-V측정을 통하여 일정 게이트 전압에서의 각각의 축적용량을 구하는 단계, 상기 축적용량의 비율을 이용하여 폴리실리콘공핍율을 구하는 단계를 포함하고, 본 발명은 폴리실리콘공핍율 측정 및 그를 위한 테스트패턴의 제조방법은 공정이 단축되어 시간, 자본 및 노력을 감소시키는 효과가 있다.The present invention is to provide a polysilicon depletion rate measurement method and a method of manufacturing a test pattern for the polysilicon depletion rate is simple, and can reduce time and capital. The present invention provides a method of forming a MOS capacitor device having dual poly gates of n + polysilicon and p + polysilicon, obtaining respective storage capacitances at a constant gate voltage through CV measurement of the capacitor elements, and the ratio of the storage capacitances. Including the step of obtaining a polysilicon depletion rate using the present invention, the polysilicon depletion rate measurement and the method of manufacturing a test pattern therefor has the effect of reducing the time, capital and effort to shorten the process.
폴리실리콘공핍율, 듀얼폴리게이트, 캐패시터, 테스트패턴 Polysilicon Depletion Rate, Dual Polygate, Capacitor, Test Pattern
Description
도 1은 기존의 p+폴리실리콘게이트 PMOS캐패시터의 C-V(Capacitance-Voltage) 에너지밴드그래프.1 is a capacitance-voltage (C-V) energy band graph of a conventional p + polysilicon gate PMOS capacitor.
도 2는 기존의 폴리실리콘공핍율측정을 위한 테스트패턴의 구조를 설명하기 위해 도시된 도면.2 is a view illustrating a structure of a test pattern for measuring a conventional polysilicon depletion rate.
도 3은 기존의 폴리실리콘공핍율측정을 위한 테스트패턴의 제조공정을 설명하기 위한 순서도.Figure 3 is a flow chart for explaining the manufacturing process of the test pattern for the conventional polysilicon depletion rate measurement.
도 4는 본 발명의 바람직한 실시예에 따른 p+폴리실리콘게이트 NMOS캐패시터의 에너지밴드그래프.4 is an energy band graph of a p + polysilicon gate NMOS capacitor according to a preferred embodiment of the present invention.
도 5는 본 발명의 바람직한 실시예에 따른 p+폴리실리콘게이트 및 n+폴리실리콘게이트 NMOS캐패시터의 C-V그래프.5 is a C-V graph of a p + polysilicon gate and an n + polysilicon gate NMOS capacitor according to a preferred embodiment of the present invention.
도 6은 본 발명의 바람직한 실시예에 따른 폴리실리콘공핍율측정을 위한 테스트패턴의 구조를 설명하기 위해 도시된 도면.6 is a view illustrating a structure of a test pattern for measuring polysilicon depletion rate according to a preferred embodiment of the present invention.
도 7은 본 발명의 바람직한 실시예에 따른 폴리실리콘공핍율측정을 위한 테스트패턴의 제조공정을 설명하기 위한 순서도.Figure 7 is a flow chart for explaining the manufacturing process of the test pattern for polysilicon depletion rate measurement in accordance with a preferred embodiment of the present invention.
도 8은 본 발명의 바람직한 실시예에 따른 폴리실리콘공핍율값과 기존 발명의 폴리실리콘공핍율값의 비교 그래프.8 is a graph comparing the polysilicon depletion rate value and the polysilicon depletion rate value of the conventional invention according to a preferred embodiment of the present invention.
본 발명은 반도체 소자에 관한 것으로, 특히 폴리실리콘공핍율 측정방법과 그를 위한 테스트패턴의 제조방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a polysilicon depletion rate measuring method and a test pattern manufacturing method therefor.
반도체 소자가 100㎚이하로 점점 소형화, 직접화 됨에 따라, 숏채널효과(short channel effect)를 감소시키기 위해 종래의 매립형채널(buried channel : BC)을 대신하여 표면채널(surface channel : SC)을 사용하는 디바이스가 제시되었다. 예를 들어, 표면채널-pMOSFET을 구현하기 위해서는 기존 n+폴리실리콘 대신 p+폴리실리콘을 pMOSFET의 게이트전극으로 적용해야 한다. 이때, 상기 p+폴리실리콘에는 B, BF, BF2 등의 보론(boron)을 포함한 이온을 폴리실리콘에 주입하여 p+폴리실리콘을 형성하였다.As semiconductor devices become increasingly smaller and smaller than 100 nm, surface channels (SCs) are used in place of conventional buried channels (BCs) to reduce short channel effects. A device is presented. For example, to implement a surface channel-pMOSFET, p + polysilicon should be applied as a gate electrode of the pMOSFET instead of the existing n + polysilicon. In this case, p + polysilicon was implanted with ions including boron such as B, BF, and BF 2 into polysilicon to form p + polysilicon.
상기 보론이 주입된 p+폴리실리콘의 경우, 인 또는 비소가 주입된 n+폴리실리콘과 달리 원자 크기가 매우 작은 보론(B)이 확산거동이 매우 빠르기 때문에 기존 SiO2를 게이트산화막으로 적용할 경우, p+폴리실리콘게이트로부터 게이트산화막을 통과하여 반도체 기판의 채널부분까지 보론(B)이 확산되어 문턱전압(threshold voltage : Vt) 증가와 같은 문제를 야기시킨다.When used as a conventional SiO 2 as a gate oxide film due to the boron in the case of implanted p + polysilicon, phosphorus or arsenic is the n + poly is the atomic size very little Boron (B) a diffusion behavior very fast unlike silicone injection, p + Boron (B) diffuses from the polysilicon gate through the gate oxide film to the channel portion of the semiconductor substrate, causing problems such as an increase in threshold voltage (Vt).
또한, p+폴리실리콘 게이트를 적용할 경우, 후속 고온 열처리시 반전용량(inversion capacitance)이 작아지는 문제가 발생한다. 이는 p+폴리실리콘내에 주입된 보론(B)이 후속 열공정에 의해 폴리실리콘 상부 또는 측면을 통해 외보론의 확산이 발생하기 때문이다. 특히, 상부에 실리사이드(silicide)가 있는 Wsix/poly-Si 게이트의 경우 Wsix를 통해, 매우 많은 보론(B)이 빠져나간다. 즉, 이러한 보론의 손실은 pMOSFET의 반전모드 (inversion)에서 게이트 폴리실리콘의 공핍율을 증가시키며, 이로 인해 반전용량이 감소하게 된다. 이러한 폴리실리콘이 공핍율은 게이트산화막에 걸리는 게이트전극필드(electric filed)가 커질수록 증가하기 때문에, 게이트산화막 두께가 작아질수록 폴리실리콘공핍문제가 심각해진다.In addition, in the case of applying the p + polysilicon gate, there is a problem that the inversion capacitance is reduced during the subsequent high temperature heat treatment. This is because boron (B) injected into p + polysilicon causes diffusion of the external boron through the polysilicon top or side by a subsequent thermal process. In particular, in the case of the Wsix / poly-Si gate having silicide on the top, a lot of boron (B) is drawn out through the Wsix. That is, the loss of boron increases the depletion rate of the gate polysilicon in the inversion mode of the pMOSFET, thereby reducing the inversion capacity. Since the polysilicon depletion rate increases as the gate electrode field (electric filed) applied to the gate oxide film increases, the polysilicon depletion problem becomes serious as the gate oxide film thickness decreases.
상기한 폴리실리콘공핍율 측정을 위해 밀러패턴(Miller patern)에서의 C-V(Capacitance-Voltage)측정이 필요하다. 도 1은 p+폴리실리콘 PMOS 밀러패턴(Miller patern)에서의 C-V측정그래프와 반전모드 및 충전모드의 에너지밴드 그래프를 도시하였다. 상기 반전용량을 충전용량으로 나누어 100을 곱한 값을 폴리실리콘공핍율(poly-depletion ration : PDR)이라고 정의한다. 상기 폴리실리콘공핍율은 0에 가까울수록 폴리실리콘공핍이 많이 발생하는 것을 의미한다.Capacitance-Voltage (C-V) measurement in the Miller pattern is required to measure the polysilicon depletion rate. 1 shows a C-V measurement graph and an energy band graph of an inversion mode and a charging mode in a p + polysilicon PMOS Miller pattern. The inversion capacity divided by the charging capacity and multiplied by 100 is defined as poly-depletion ratio (PDR). The polysilicon depletion rate means that the polysilicon depletion occurs as the nearer to zero.
도 2는 상기 폴리실리콘공핍율 측정을 위한 밀러패턴(Miller patern)을 도시하였다. 상기 패턴은 1㎛이하의 게이트길이 및 소스/드레인 정션등을 갖춘 특수한 테스트 패턴으로 게이트 패터닝 후 금속배선공정까지 실시해야 측정이 가능하므로 폴리실리콘공핍율을 평가하기 위한 시간과 자본이 많이 들어가는 문제점이 있다.2 illustrates a Miller pattern for measuring the polysilicon depletion rate. The pattern is a special test pattern with a gate length of less than 1 μm and a source / drain junction, etc., which requires measurement until the metal wiring process is performed after the gate patterning. Therefore, it takes a lot of time and capital to evaluate the polysilicon depletion rate. have.
따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 폴리실리콘공핍율 측정이 간단하면서, 시간 및 자본을 줄일 수 있는 폴리실리콘공핍율 측정방법 및 그를 위한 테스트 패턴의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been proposed to solve the above problems of the prior art, and the polysilicon depletion rate measurement method and the method of manufacturing a polysilicon depletion rate and a test pattern therefor that can reduce the time and capital is simple. The purpose is to provide.
상기한 목적을 달성하기 위한 본 발명은, n+폴리실리콘 및 p+폴리실리콘의 듀얼폴리게이트가 형성된 MOS 캐패시터 소자를 형성하는 단계, 상기 캐패시터 소자의 C-V측정을 통하여 일정 게이트 전압에서의 각각의 축적용량을 구하는 단계, 상기 축적용량의 비율을 이용하여 폴리실리콘공핍율을 구하는 단계를 포함하는 폴리실리콘공핍율 측정방법과 그를 위한 테스트패턴의 제조방법을 제공한다.According to the present invention for achieving the above object, forming a MOS capacitor device having a dual poly gate of n + polysilicon and p + polysilicon, each storage capacitance at a constant gate voltage through CV measurement of the capacitor element It provides a polysilicon depletion rate measuring method comprising the step of obtaining, the polysilicon depletion rate using the ratio of the storage capacity and a method of manufacturing a test pattern therefor.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도 4를 참조하면, p+폴리실리콘게이트 NMOS캐패시터의 에너지밴드 그래프에서 n+폴리실리콘게이트와 달리 p+폴리실리콘게이트의 경우 게이트 산화막과의 계면 근처에서 페미레벨(Fermi-level)이 컨덕션밴드(conduction band : Ec)쪽으로 움직 일 수 있으므로, 축적모드에서도 폴리공핍이 발생함을 확인할 수 있다. Referring to FIG. 4, unlike n + polysilicon gates in an energy band graph of a p + polysilicon gate NMOS capacitor, in the case of p + polysilicon gates, a femi-level has a conduction band near the interface with a gate oxide layer. : Ec), it can be seen that poly depletion occurs in accumulation mode.
도 5를 참조하면, n+폴리실리콘게이트와 p+폴리실리콘게이트를 갖는 듀얼 폴리 MOS캐패시터의 C-V(Capacitance-Voltage)측정 그래프에서 축적용량을 확인할 수 있다. 본 발명의 폴리실리콘공핍율측정은 상기 n+폴리실리콘게이트와 p+폴리실리콘게이트를 갖는 듀얼 폴리 MOS캐패시터를 형성하여, 상기 캐패시터 소자의 C-V측정을 통하여 일정 게이트 전압에서의 각각의 축적용량을 구한다. 상기 축적용량의 비율을 이용하여 폴리실리콘공핍율을 구할 수 있다.
또한, 폴리실리콘공핍율로 부터 MOSFET소자의 인버전캐패시턴스(inversion capacitance)값을 구할 수 있다.Referring to FIG. 5, the storage capacity can be confirmed in a CV (Capacitance-Voltage) measurement graph of a dual poly MOS capacitor having an n + polysilicon gate and a p + polysilicon gate. The polysilicon depletion ratio measurement of the present invention forms a dual poly MOS capacitor having the n + polysilicon gate and the p + polysilicon gate, and obtains the respective storage capacitances at a constant gate voltage through CV measurement of the capacitor element. The polysilicon depletion rate can be obtained using the ratio of the accumulation capacity.
In addition, the inversion capacitance value of the MOSFET device can be obtained from the polysilicon depletion rate.
예를 들어, 보론이 도핑된 p+폴리실리콘게이트의 폴리실리콘공핍율은 듀얼폴리를 갖는 NMOS캐패시터의 기판을 이용하여 구할 수 있는데, p+폴리실리콘게이트의 축적용량을 n+폴리실리콘게이트의 축적용량 값으로 나눈 후 100을 곱하여 PDR(poly depletion ratio)값을 얻는다.For example, the polysilicon depletion rate of the boron-doped p + polysilicon gate can be obtained using a substrate of an NMOS capacitor having dual poly, and the accumulation capacity of the p + polysilicon gate is defined as the accumulation capacity of the n + polysilicon gate. Divide and multiply by 100 to get the poly depletion ratio (PDR).
또한, 인 또는 비소가 도핑된 n+폴리실리콘게이트의 폴리실리콘공핍율은 듀얼폴리를 갖는 PMOS캐패시터의 기판을 이용하여 구할 수 있는데, n+ 폴리실리콘게이트를 p+폴리실리콘게이트의 축적용량으로 나눈 후 100을 곱한 값이 PDR이 된다.In addition, the polysilicon depletion rate of the n + polysilicon gate doped with phosphorus or arsenic can be obtained using a substrate of a PMOS capacitor having a dual poly, and the n + polysilicon gate is divided by the storage capacity of the p + polysilicon gate and 100 is obtained. The product is the PDR.
도 6을 참조하면, 상기한 폴리실리콘공핍율 측정을 위한 에어리어타입(Area-type)의 테스트패턴을 형성할 수 있다. 상기 테스트패턴은 활성영역이 정의된 반도체 기판상에 도핑된 폴리실리콘게이트가 형성된 것으로, C-V측정이 가능한 30×30㎛2 이상의 크기로 형성할 수 있다.Referring to FIG. 6, an area-type test pattern for measuring the polysilicon depletion rate may be formed. The test pattern is formed of a doped polysilicon gate on a semiconductor substrate in which the active region is defined, and may be formed to a size of 30 × 30㎛ 2 or more capable of CV measurement.
도 7을 참조하면, 상기 폴리실리콘공핍율 측정을 위한 테스트패턴의 제조방 법을 설명할 수 있다. 반도체 기판에 활성영역을 정의하고, 상기 활성영역이 정의된 상기 반도체 기판에 소스/드레인 불순물 영역을 형성한다. 이때, 상기 반도체 기판은 실리콘기판 대신 Si1 - xGex, Ge, Silicon-on-insulator(SOI), Germanium-on-insulator(GOI)또는 strained-Si중에서 선택된 어느 하나의 물질로 이루어진 반도체 기판을 사용할 수있다. 이때, x값은 0.01∼1.00이 될 수 있다.Referring to FIG. 7, a method of manufacturing a test pattern for measuring the polysilicon depletion rate may be described. An active region is defined in the semiconductor substrate, and a source / drain impurity region is formed in the semiconductor substrate in which the active region is defined. In this case, the semiconductor substrate is a semiconductor substrate made of any one material selected from Si 1 - x Ge x , Ge, Silicon-on-insulator (SOI), Germanium-on-insulator (GOI), or strained-Si instead of a silicon substrate. Can be used At this time, the x value may be 0.01 to 1.00.
이후에, 상기 소스/드레인 영역의 주변부를 덮는 게이트산화막 및 도핑된 폴리실리콘패턴을 순차적으로 적층시킨 게이트스택을 형성한다. 이때, 상기 폴리실리콘패턴은 Wsix/poly-Si, NiSix/poly-Si, CoSix/poly-Si, HfSix/poly-Si, CrSix/poly-Si 또는 TiSix/poly-Si중에서 선택된 어느 하나의 폴리사이드(polycide)구조를 사용할 수 있다. 여기서, x값은 0.5∼2.0이 될 수 있다. 또한, 상기 폴리실리콘패턴은 W/WNx/poly-Si, W/WNx/WSiy/poly-Si, W/WNx/TiN/Ti/poly-Si 또는 W/WNx/CoSiy/poly-Si중에서 선택된 어느하나의 폴리메탈(polymetal)구조를 사용할 수 있다. 여기서, x, y값은 0.1∼10이 될 수 있다. 상기 폴리사이드 및 폴리메탈 구조에서 poly-Si 대신 poly-Si1 - xGex(x=0.01∼0.99)을 사용할 수 있다. 또한, 상기 폴리실리콘패턴은 Wsix, NiSix, CoSix, HfSix, CrSix 또는 TiSix중에서 선택된 어느 하나의 풀리실리사이드(fully-silicide:FUSI)를 사용할 수 있다. Thereafter, a gate stack in which a gate oxide film covering the periphery of the source / drain region and a doped polysilicon pattern are sequentially stacked is formed. In this case, the polysilicon pattern is any one polyside selected from Wsix / poly-Si, NiSix / poly-Si, CoSix / poly-Si, HfSix / poly-Si, CrSix / poly-Si, or TiSix / poly-Si ( polycide) structure can be used. Here, the x value may be 0.5 to 2.0. The polysilicon pattern may be any one selected from W / WNx / poly-Si, W / WNx / WSiy / poly-Si, W / WNx / TiN / Ti / poly-Si, or W / WNx / CoSiy / poly-Si. Polymetal structure of can be used. Here, x and y values may be 0.1 to 10. In the polyside and polymetal structure, poly-Si 1 - x Ge x (x = 0.01 to 0.99) may be used instead of poly-Si. In addition, the polysilicon pattern may use any one of fully-silicide (FUSI) selected from Wsix, NiSix, CoSix, HfSix, CrSix, or TiSix.
이후에, 상기 폴리실리콘패턴 상부에 하드마스크용 Si3N4, SiO2 또는 SiON중에서 선택된 어느 하나의 절연막을 500∼3000Å두께로 형성할 수 있다.Subsequently, an insulating film selected from Si 3 N 4 , SiO 2, or SiON for hard mask may be formed on the polysilicon pattern to have a thickness of 500˜3000 μm.
이후에, 게이트패터닝 및 열처리를 실시할 수 있다. 상기 게이트패터닝시 30 ×30㎛2 이상의 에어리어타입(area-type) MOS캐패시터 형성을 위해, i-line을 사용하여 패터닝을 수행할 수 있다. Thereafter, gate patterning and heat treatment may be performed. In order to form an area-type MOS capacitor of 30 × 30 μm 2 or more during the gate patterning, patterning may be performed using an i-line.
이후에, 게이트에 프로빙(probing)을 위해 상기 하드마스크에 마스크 및 식각공정을 실시한다. 상기 마스크 및 식각공정은 상기 하드마스크와 같은 절연층이 있는 경우 수행하며, 상기 게이트패턴이 모두 전도성 물질로 되어 있는 경우에는 마스크 및 식각공정을 스킵할 수 있다.Thereafter, a mask and an etching process are performed on the hard mask for probing the gate. The mask and the etching process may be performed when there is an insulating layer such as the hard mask, and when the gate patterns are all made of a conductive material, the mask and the etching process may be skipped.
이후에, H2/N2 포밍어닐(forming anneal)을 실시하여 MOS캐패시터 소자를 완성한다.Thereafter, H 2 / N 2 forming anneal is performed to complete the MOS capacitor device.
도 8을 참조하면, 상기한 기존발명(Miller pattern)에서의 폴리실리콘공핍율과 본 발명의 n+/p+ 폴리 NMOS캐패시터 구조에서 측정된 폴리실리콘공핍율을 비교할 수 있다.Referring to FIG. 8, the polysilicon depletion rate of the conventional invention (Miller pattern) and the polysilicon depletion rate measured in the n + / p + poly NMOS capacitor structure of the present invention can be compared.
상기한 본 실시예는 게이트패턴이 형성될 활성영역을 평평한(flat) 플라나(planar)타입 대신 RCAT(Recessed channel array transistor)와 같은 트렌치타입 또는 FinFET과 같은 핀타입 등으로 형성할 수 있다.According to the present exemplary embodiment, the active region in which the gate pattern is to be formed may be formed in a trench type such as a recessed channel array transistor (RCAT) or a fin type such as a FinFET instead of a flat planar type.
진술한 바와 같이, 소자분리영역과 게이트패턴구조만 형성하여 폴리실리콘공핍율을 측정한 본 실시예는 금속배선공정까지 끝난 후 폴리실리콘공핍율 측정이 가능했던 종래의 문제점을 해결하면서, 폴리실리콘공핍율 측정이 간단하고, 공정이 단축되어 시간과 자본을 낮출 수 있는 장점을 가지고 있다.As stated, this embodiment, in which the polysilicon depletion rate was measured by forming only the device isolation region and the gate pattern structure, solved the conventional problem that the polysilicon depletion rate could be measured after the metal wiring process was completed. The pip rate measurement is simple and the process is shortened to save time and capital.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으 나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명에 의한 폴리실리콘공핍율 측정 및 그를 위한 테스트패턴의 제조방법은 공정이 단축되어 시간, 자본 및 노력을 감소시키는 효과가 있다.The polysilicon depletion rate measurement and a test pattern manufacturing method therefor according to the present invention has the effect of reducing the time, capital and effort to shorten the process.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH07307442A (en) * | 1994-03-18 | 1995-11-21 | Seiko Instr Inc | Semiconductor device and manufacturing method thereof |
| KR20020046967A (en) * | 2000-12-12 | 2002-06-21 | 마찌다 가쯔히꼬 | Apparatus and method for analyzing capacitance of insulator |
| US6472233B1 (en) | 1999-08-02 | 2002-10-29 | Advanced Micro Devices, Inc. | MOSFET test structure for capacitance-voltage measurements |
| US6888157B1 (en) | 2001-07-27 | 2005-05-03 | Advanced Micro Devices, Inc. | N-Gate/N-Substrate or P-Gate/P-Substrate capacitor to characterize polysilicon gate depletion evaluation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH07307442A (en) * | 1994-03-18 | 1995-11-21 | Seiko Instr Inc | Semiconductor device and manufacturing method thereof |
| US6472233B1 (en) | 1999-08-02 | 2002-10-29 | Advanced Micro Devices, Inc. | MOSFET test structure for capacitance-voltage measurements |
| KR20020046967A (en) * | 2000-12-12 | 2002-06-21 | 마찌다 가쯔히꼬 | Apparatus and method for analyzing capacitance of insulator |
| US6888157B1 (en) | 2001-07-27 | 2005-05-03 | Advanced Micro Devices, Inc. | N-Gate/N-Substrate or P-Gate/P-Substrate capacitor to characterize polysilicon gate depletion evaluation |
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