KR100854875B1 - Manufacturing Method of Flash Memory Device - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory device, comprising: forming a floating gate pattern in which a tunnel oxide film, a first conductive layer, and a nitride film are stacked in a first region of a semiconductor substrate, and forming an isolation layer in a second region of the semiconductor substrate Forming; Etching the device isolation layer by a predetermined thickness after removing the nitride layer; And forming a dielectric gate, a second conductive layer, and a hard mask layer on the entire structure, and then patterning a control gate, and etching the floating gate pattern using the control gate as a mask to form a floating gate. A method of manufacturing a flash memory device capable of preventing damage to side and top portions of a conductive layer for a floating gate during an etching process of an isolation layer for controlling an effective field oxide height, thereby improving device reliability.

EFH, Device Separators, Dry Etch, Nitride

Description

Method of manufacturing a flash memory device

1 (a) to 1 (d) are cross-sectional views of a device for sequentially explaining a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

101 semiconductor substrate 102 tunnel oxide film

103: first conductive layer 104: buffer oxide film

105 nitride film 106 device isolation film

107 dielectric film 108 second conductive layer

109: hard mask film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to fabricate a flash memory device capable of preventing damage to side and top portions of a conductive layer for a floating gate during an etching process of an isolation layer for controlling EFH. It is about a method.

NAND-type flash memory devices perform data programs by injecting electrons into floating gates using a Fowler-Nordheim (FN) tunneling phenomenon to provide a large capacity and high integration.

The NAND type flash memory device is composed of a plurality of cell blocks. One cell block includes a plurality of cell strings in which a plurality of cells for storing data are connected in series to form a single string, a drain select transistor and a source select transistor formed between the cell string and the drain and the cell string and the source, respectively. do. In addition, there are peripheral circuit regions in which a plurality of circuit elements are formed to generate and transmit predetermined biases for program, erase and read operations of the cell. Here, the NAND type flash memory cell forms a device isolation film in a predetermined region on the semiconductor substrate, and then forms a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on the semiconductor substrate, and a junction part at both sides of the gate. It is formed by forming.

However, in the manufacturing process of a NAND type flash memory device of 60 nm or less, a floating gate conductive layer is formed high in order to secure overlap margin between the floating gate and the active region and to prevent tunnel oxide thinning. In addition, a method of performing a trench etching process for forming an isolation layer at the same time as the conductive layer etching process is used. In this process, in order to increase the junction area between the dielectric film and the floating gate, the process of controlling the effective field oxide height (EFH) by etching the device isolation film to a predetermined depth.

However, since the etching process of the device isolation layer for controlling the EFH uses a wet etching process, the side surface of the conductive layer exposed by etching the device isolation layer is damaged. In addition, a nitride film is used as a hard mask for trench etching. The nitride film is etched to a predetermined thickness and then removed by a wet etching process using phosphoric acid (H ₃ PO ₄ ). However, when the nitride film is removed, a portion of the upper portion of the conductive layer for the floating gate is damaged. The damage of the conductive layer for the floating gate generated during the etching of the device isolation layer and the removal of the nitride layer not only causes damage to the active region during the gate etching in the future, but also reduces the volume of the floating gate, which causes a serious problem in the data storage function of the floating gate. That is, not only the storage capacity decreases due to the volume reduction of the floating gate, but also the thickness of the dielectric film formed on the damaged floating gate becomes nonuniform, causing threshold voltage change or leakage of stored electrons, thereby causing a critical problem in device operation. Will be generated.

An object of the present invention is to provide a method of manufacturing a flash memory device capable of preventing damage to the side and the top of the conductive layer for the floating gate during etching of the nitride film and the device isolation film.

Another object of the present invention is to etch the nitride film after the device isolation layer etching process for controlling the EFH by performing a dry etching process of etching only the device isolation layer without etching the conductive layer of the conductive layer for the floating gate side and top To provide a method of manufacturing a flash memory device that can prevent the damage.

A method of manufacturing a flash memory device according to an embodiment of the present invention forms a floating gate pattern in which a tunnel oxide film, a first conductive layer, and a nitride film are stacked in a first region of a semiconductor substrate, and in the second region of the semiconductor substrate. Forming a separator; Etching the device isolation layer by a predetermined thickness after removing the nitride layer; And forming a dielectric layer, a second conductive layer, and a hard mask layer on the entire structure, and then patterning the control gate, and etching the floating gate pattern using the control gate as a mask to form a floating gate.

The floating gate pattern and the device isolation layer may be formed by sequentially forming the tunnel oxide layer, the first conductive layer, and the nitride layer on the semiconductor substrate; Forming a floating gate pattern by etching a predetermined region of the nitride layer to the tunnel oxide layer by a photolithography and an etching process using an isolation mask to form a trench by etching the semiconductor substrate to a predetermined depth; Forming an insulating film on the entire structure to fill the trench; And forming the device isolation layer by polishing the insulating layer to expose the nitride layer.

The insulating film is formed of an HDP oxide film or a stacked HDP oxide film and an SOD film.

The method may further include removing the device isolation layer by the thickness of the nitride layer before removing the nitride layer.

The dry etching process may be performed under the condition that only the device isolation layer is etched without the first conductive layer being etched.

The dry etching process is performed using a mixed gas containing CF ₄ or CHF ₃ gas.

The dry etching process is performed using ICP type equipment or MERIE equipment.

The dry etching process using the ICP type equipment is performed by applying a pressure of 3 to 100 mTorr and a source and a bias power of 500 to 1000 W.

Dry etching process using the MERIE equipment is carried out by applying a pressure of 10 to 200mTorr and a source and bias power of 100 to 1000W.

The dielectric film is formed using an ONO structure or a high dielectric material.

The high dielectric material is Al ₂ O ₃ , HfO ₂ , ZrO ₂ , SiON, La ₂ O ₃ , Y ₂ O ₃ , TiO ₂ , CeO ₂ , N ₂ O ₃ , Ta ₂ O ₅ , BaTiO ₃ , SrTiO ₃ , Materials of BST or PZT and mixed oxides HfxAlyOz, ZrxAlyOz, HfSiO ₄ or ZrSiO ₄ .

The hard mask film is formed using an oxide film, amorphous carbon, or the like.

In addition, according to another embodiment of the present invention, a method of manufacturing a flash memory device may include stacking a tunnel oxide film, a first conductive layer, and a nitride film in a first region of a semiconductor substrate, and forming an isolation layer in a second region of the semiconductor substrate. step; Etching the device isolation layer by a predetermined thickness after removing the nitride layer; Forming a floating gate pattern by forming a second conductive layer on the first conductive layer to partially overlap the device isolation layer; And forming a dielectric layer, a third conductive layer, and a hard mask layer on the entire structure, and then patterning the control gate, and etching the floating gate pattern using the control gate as a mask to form a floating gate.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 (a) to 1 (d) are cross-sectional views of a device for sequentially describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1A, the tunnel oxide film 102, the first conductive layer 103, the buffer oxide film 104, and the nitride film 105 are sequentially formed on the semiconductor substrate 101. The first conductive layer 103 is formed to a thickness of 500 to 2000 GPa using a polysilicon film. Preferably, the undoped polysilicon film and the dope polysilicon film are laminated. In order to determine the active region and the field region, the nitride layer 105 is patterned by a photolithography and an etching process using an isolation mask. A trench is formed by etching the buffer oxide film 104, the first conductive layer 103, the tunnel oxide film 102, and the semiconductor substrate 101 to a predetermined depth by using the patterned nitride film 105 as an etching mask. The trench is formed in the field region, and the active region and the field region are determined in parallel. In the active region, the first conductive layer 103 is patterned to determine the floating gate pattern. In addition, an insulating film is formed over the entire structure to fill the trench, and then a CMP process is performed to expose the nitride film 105 to form an isolation layer 106. Here, the device isolation film 106 is formed by using an HDP oxide film or by stacking an HDP oxide film and an SOD film.

Referring to FIG. 1B, after partially etching the device isolation layer 106, the nitride layer 105 is removed by a wet etching process using phosphoric acid (H ₃ PO ₄ ). The device isolation layer 106 is etched to the thickness of the nitride film 105 so that the height of the device isolation layer 106 and the buffer oxide film 104 is approximately the same after the nitride film 105 is etched. Here, the buffer oxide film 104 serves to protect the first conductive layer 103 when the nitride film 105 is removed.

Referring to FIG. 1C, the device isolation layer 106 is etched by a predetermined thickness in a dry etching process in which the first conductive layer 103 is not etched and only the device isolation layer 106 is etched. This adjusts the effective field oxide height (EFH) of the device isolation layer 106. In this case, as the isolation layer 106 is etched, the buffer oxide layer 104 is also etched. The etching process of the device isolation layer 106 is performed using a mixed gas containing CF ₄ and / or CHF ₃ gas, preferably using a mixed gas of CF ₄ , CHF ₃ , Ar, and oxygen (O ₂ ). do. Here, argon gas is introduced in a small amount on the order of 0 to 50 sccm. Meanwhile, the etching process of the device isolation layer 106 may be performed using ICP type equipment or MERIE equipment. When using ICP type equipment, apply pressure of 3 ~ 100mTorr and source and bias power of 500 ~ 1000W, and when using MERIE equipment, apply pressure of 10 ~ 200mTorr and source and bias power of 100 ~ 1000W do. In particular, in the MERIE type oxide etching chamber, it is possible to secure a higher etching selectivity with respect to the conductive layer than other etching chambers, and by using a low bias, the collision effect of ions can be minimized, so that the first conductive layer is formed by sputtering. (103) Damage to the upper part can be prevented.

Referring to FIG. 1D, a dielectric film 107, a second conductive layer 108, and a hard mask film 109 are formed over the entire structure. The dielectric film 107 is formed using an ONO structure film or a high dielectric material. High dielectric materials include Al ₂ O ₃ , HfO ₂ , ZrO ₂ , SiON, La ₂ O ₃ , Y ₂ O ₃ , TiO ₂ , CeO ₂ , N ₂ O ₃ , Ta ₂ O ₅ , BaTiO ₃ , SrTiO ₃ , HfAlO, ZrAlO, HfSiO ₄ or ZrSiO ₄ which are mixed oxides with a material of BST or PZT are used. On the other hand, the second conductive layer 107 is formed using a single layer of a polysilicon film or a laminated structure of a polysilicon film and a tungsten silicide film. The hard mask film 109 is formed using an oxide film, amorphous carbon, or the like. After the hard mask layer 109 is patterned by a photolithography and an etching process using a control gate mask, the second conductive layer 108 is etched to form a control gate in a direction perpendicular to the device isolation layer 106. In a subsequent etching process, a predetermined region of the dielectric film 107 to the tunnel oxide film 102 is etched to form a floating gate.

Meanwhile, in the above embodiment, the process of forming the conductive layer for the floating gate as a single layer has been described, but the present invention is not limited thereto, and the sidewalls of the semiconductor substrate are exposed by etching the device isolation layer of the exposed region when the control gate and the floating gate are formed. It can also be used for other processes. For example, it may be used in a so-called Self Aligned Shallow Trench Isolation (SA-STI) process in which a floating gate is formed using a stacked structure of first and second conductive layers, and the process will be described below. After the tunnel oxide film, the first conductive layer, the buffer oxide film, and the nitride film are formed on the semiconductor substrate, trenches are formed by etching the predetermined region and the semiconductor substrate to a predetermined depth. After the trench is formed to form the device isolation layer, the device isolation layer is etched to a predetermined thickness, and after removing the nitride film, the process of etching the device isolation layer to control the EFH is a dry etching process having excellent etching selectivity with respect to the first conductive layer. Conduct. The second conductive layer is formed to overlap the device isolation layer, thereby forming a floating gate pattern including the first and second conductive layers. Since the process is the same as the process described with reference to the drawings. Here, the first conductive layer is formed to a thickness of 100 to 1000 GPa, and the second conductive layer is formed to a thickness of 200 to 1500 GPa.

As described above, according to the present invention, after removing the nitride film serving as an etching mask for forming the trench, the device isolation film etching process for controlling EFH is performed by dry etching under the condition that only the device isolation film is etched without the conductive layer being etched. By doing so, damage to the side and top of the conductive layer for floating gates can be prevented, thereby improving the reliability of the device.

Claims (14)

Forming a floating gate pattern in which a tunnel oxide film, a first conductive layer, and a nitride film are stacked in a first region of the semiconductor substrate, and forming an isolation layer in a second region of the semiconductor substrate; Etching the device isolation layer by a predetermined thickness after removing the nitride layer; And Forming a dielectric gate, a second conductive layer, and a hard mask layer over the entire structure, and then patterning the control gate, and etching the floating gate pattern using the control gate as a mask to form a floating gate. Method of manufacturing the device. The method of claim 1, wherein the floating gate pattern and the device isolation layer Sequentially forming the tunnel oxide film, the first conductive layer, and the nitride film on the semiconductor substrate; Forming a floating gate pattern by etching a predetermined region of the nitride layer to the tunnel oxide layer by a photolithography and an etching process using an isolation mask to form a trench by etching the semiconductor substrate to a predetermined depth; Forming an insulating film on the entire structure to fill the trench; And And forming the device isolation film by polishing the insulating film so that the nitride film is exposed. The method of claim 2, wherein the insulating film is formed of an HDP oxide film or a stacked HDP oxide film and an SOD film. The method of claim 1, further comprising removing the device isolation layer by the thickness of the nitride film before removing the nitride film. The method of claim 1, wherein the dry etching process is performed under a condition that only the device isolation layer is etched without the first conductive layer being etched. The method of claim 1, wherein the dry etching process is performed using a mixed gas containing CF ₄ or CHF ₃ gas. The method of claim 1, wherein the dry etching process is performed using ICP type equipment or MERIE equipment. The method of claim 7, wherein the dry etching process using the ICP type equipment is performed by applying a pressure of 3 to 100 mTorr and a source and a bias power of 500 to 1000 W. 9. The method of claim 7, wherein the dry etching process using the MERIE device is performed by applying a pressure of 10 to 200 mTorr, a source and a bias power of 100 to 1000 W. 9. The method of claim 1, further comprising performing a cleaning process before forming the dielectric layer, thereby etching the device isolation layer to a predetermined thickness. And the dielectric film is formed using an ONO structure or a high dielectric material. The method of claim 11, wherein the high dielectric material is Al ₂ O ₃ , HfO ₂ , ZrO ₂ , SiON, La ₂ O ₃ , Y ₂ O ₃ , TiO ₂ , CeO ₂ , N ₂ O ₃ , Ta ₂ O ₅ , A method of manufacturing a flash memory device comprising HfAlO, ZrAlO, HfSiO ₄ or ZrSiO ₄ , which is a mixed oxide of BaTiO ₃ , SrTiO ₃ , BST or PZT. The method of claim 1, wherein the hard mask film is formed using an oxide film or amorphous carbon. Stacking a tunnel oxide film, a first conductive layer, and a nitride film in a first region of the semiconductor substrate, and forming an isolation layer in the second region of the semiconductor substrate; Etching the device isolation layer by a predetermined thickness after removing the nitride layer; Forming a floating gate pattern by forming a second conductive layer on the first conductive layer to partially overlap the device isolation layer; And And forming a dielectric layer, a third conductive layer, and a hard mask layer over the entire structure, and patterning the control gate, and etching the floating gate pattern using the control gate as a mask to form a floating gate. Method of manufacturing the device.

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