KR101034602B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to an activation control technique of an internal voltage, and an object thereof is to provide a semiconductor memory device that is stable in terms of overall operation and low current consumption by efficiently controlling an activation time of an internal voltage. According to an aspect of the present invention, an internal column signal generation unit for generating an internal column signal that is activated when a command is applied, and an internal delay by reflecting a read latency or a write latency to the internal column signal. An internal delay column signal generator for generating a column signal, an activation signal generator for generating an internal voltage activation signal in response to the internal column signal, and an internal for generating an internal voltage in response to the internal voltage activation signal A semiconductor memory device having a voltage generator is provided.

Semiconductor memory device, internal voltage, current consumption, activation control, internal column signal

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor design technique, and to an activation control technique of an internal voltage.

The semiconductor memory device receives an external power supply voltage to generate an internal voltage having a voltage level required for a specific circuit in an internal voltage generation circuit. Since the internal circuit using the internal voltage operates only in a specific operation section, it is advantageous to generate the internal voltage only in the section in which the internal circuit operates to reduce current consumption.

1 is a block diagram of a semiconductor memory device of the prior art.

Referring to FIG. 1, the semiconductor memory device may include an activation signal generator 110 for generating an internal voltage activation signal V_EN in response to an active signal ROW_ACT <0: 7> that is activated when a low command is applied. The internal voltage generator 120 is configured to generate the internal voltage V_OUT in response to the voltage activation signal V_EN. Here, the internal voltage V_OUT is a voltage used during a read operation and a write operation period.

The semiconductor memory device configured as described above receives an active signal ROW_ACT <0: 7> for activating the corresponding bank BANK and is activated by the internal voltage activation signal V_EN when the bank BANK is activated. The internal voltage generator 120 generates the internal voltage V_OUT. When the internal voltage V_OUT is generated in this manner, the internal voltage V_OUT is generated too sooner than the time point at which the internal voltage V_OUT is used, resulting in a large current consumption.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the conventional problems as described above, and an object thereof is to provide a semiconductor memory device that is stable in terms of overall operation and has low current consumption by efficiently controlling the activation time of an internal voltage.

According to an aspect of the present invention for achieving the above technical problem, an activation signal generation unit for generating an internal voltage activation signal in response to the internal column signal is activated when the command is applied; And an internal voltage generator configured to generate an internal voltage in response to the internal voltage activation signal.

In addition, according to another aspect of the invention, the internal column signal generation unit for generating an internal column signal that is activated when a command is applied; An internal delay column signal generator for generating an internal delay column signal by reflecting a read latency or a write latency to the internal column signal; An activation signal generator for generating an internal voltage activation signal in response to the internal column signal; And an internal voltage generator configured to generate an internal voltage in response to the internal voltage activation signal.

The semiconductor memory device to which the present invention is applied improves power consumption and operational stability by efficiently controlling an internal voltage generation time.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . For reference, in the drawings and detailed description, terms, symbols, symbols, etc. used to refer to elements, blocks, etc. may be represented by detailed units as necessary, and therefore, the same terms, symbols, symbols, etc. are the same in the entire circuit. Note that it may not refer to.

In general, the logic signal of the circuit is divided into a high level (HIGH LEVEL, H) or a low level (LOW LEVEL, L) corresponding to the voltage level, and may be expressed as '1' and '0', respectively. In addition, it is defined and described that it may additionally have a high impedance (Hi-Z) state and the like. In addition, PMOS (P-channel Metal Oxide Semiconductor) and N-channel Metal Oxide Semiconductor (NMOS), which are terms used in the present embodiment, are known to be a type of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor). In addition, the clock signal CLOCK is a periodic pulse signal that toggles at a constant cycle. In general, the clock signal is used to determine the activation time of an internal circuit or an internal signal based on a rising edge or a falling edge. The clock signal is applied in a differential form between a positive clock signal and a subclock signal. Also used.

2 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 2, the semiconductor memory device generates an internal delay column signal generator for generating internal delay column signals CASP10RD and CASP10WT that are activated by reflecting a read latency or a write latency when a command is applied. An activation signal generator 220 for generating an internal voltage activation signal V_EN in response to the internal delay column signals CASP10RD and CASP10WT, and an internal voltage in response to the internal voltage activation signal V_EN. An internal voltage generator 230 for generating V_OUT).

Here, the internal voltage V_OUT is a voltage used during a read operation and a write operation period. The command may include a column series read command, a write command, and the like, and is a command for accessing a column COLUMN area of a semiconductor memory device. For reference, a row series command includes an active command, and is a command for accessing a ROW area of a semiconductor memory device.

The main operations of the semiconductor memory device configured as described above are as follows.

The internal delay column signal generator 210 is a column activated by a logical combination of a row address strobe signal (/ RAS), a column address strobe signal (/ CAS), and a chip select signal (/ CS). When a series read command is applied, a first internal delay column signal CASP10RD reflecting read latency is generated, and a row address strobe signal (Row Address Strobe (/ RAS)) and a column address strobe signal (Column) are generated. Generates the second internal delay column signal CASP10WT reflecting the write latency when the column sequence write command activated by the logical combination of the address strobe, / CAS) and the chip select signal / CS is applied. do.

The activation signal generator 220 activates the internal voltage activation signal V_EN when the first internal delay column signal CASP10RD or the second internal delay column signal CASP10WT is activated, and the internal voltage generator 230 internally. The internal voltage V_OUT is generated in response to the voltage activation signal V_EN. Therefore, since the internal voltage V_OUT is generated during the read or write operation section in which the internal voltage V_OUT is used, current consumption can be minimized.

3 is a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device may include an internal column signal generation unit 40 for generating an internal column signal CASP6 that is activated when a command is applied, and a read latency or a write latency when a command is applied. ) To generate the internal delayed column signal generator 30 for generating the internal delayed column signals CASP10RD and CASP10WT, and to generate the internal voltage activation signal V_EN in response to the internal column signal CASP6. An activation signal generator 50 and an internal voltage generator 60 for generating an internal voltage V_OUT in response to the internal voltage activation signal V_EN are provided.

Here, the internal voltage V_OUT is a voltage used during a read operation and a write operation period. The command may include a column series read command, a write command, and the like, and is a command for accessing a column COLUMN area of a semiconductor memory device. For reference, a row series command includes an active command, and is a command for accessing a ROW area of a semiconductor memory device.

The detailed configuration and main operations of the semiconductor memory device configured as described above are as follows.

The internal column signal generator 40 is a column sequence activated by a logical combination of a row address strobe signal (/ RAS), a column address strobe signal (/ CAS), and a chip select signal (/ CS). When a read command or a column series write command is applied, the internal column signal CASP6 is activated and output.

The internal delay column signal generation unit 30 is a column activated by a logical combination of a row address strobe signal (Row Address Strobe (/ RAS)), a column address strobe signal (Column Address Strobe (/ CAS)), and a chip select signal (/ CS). When a series read command is applied, a first internal delay column signal CASP10RD reflecting read latency is generated, and a row address strobe signal (Row Address Strobe (/ RAS)) and a column address strobe signal (Column) are generated. Generates the second internal delay column signal CASP10WT reflecting the write latency when the column sequence write command activated by the logical combination of the address strobe, / CAS) and the chip select signal / CS is applied. do. For reference, the internal delay column signals CASP10RD and CASP10WT may be generated by reflecting the read latency or the write latency in the internal column signal CASP6.

When the internal column signal CASP6 is activated and input, the activation signal generator 50 activates the internal voltage activation signal V_EN, and the internal voltage generator 60 responds to the internal voltage activation signal V_EN. Will generate (V_OUT). Therefore, since the internal voltage V_OUT is generated during the read or write operation section in which the internal voltage V_OUT is used, current consumption can be minimized. In the second embodiment of FIG. 3, unlike the first embodiment of FIG. 2, the internal column signal generator 40 does not use the internal delay column signals CASP10RD and CASP10WT of the internal delay column signal generator 30. The activation signal generator 50 is controlled using the internal column signal CASP6. That is, since the internal delay column signals CASP10RD and CASP10WT are signals generated by reflecting the read latency or the write latency, the activation time is delayed than the internal column signal CASP6. In consideration of this, it is more preferable to use the internal column signal CASP6 having a fast activation time.

Meanwhile, the internal column signal generator 40 will be described in detail as follows.

4 is a circuit diagram according to an embodiment of an internal column signal generator.

Referring to FIG. 4, the internal column signal generation unit may include a command processor 410 for outputting an internal signal CMD activated when a column series read command or a column series write command is applied, and a clock signal. The clock delay unit 420 for delaying CLK, the internal signal CMD, and the inverted signal / CMD of the internal signal are differential inputs, and the internal column is responsive to a signal output from the clock delay unit 420. The signal generator 430 is configured to generate the signal CASP6.

The command processor 410 may include a first inverter INV1 inputting a column address strobe signal / CAS and a second inverter INV2 inputting a chip select signal / CS. Output from the negative logical means (NAND) and the negative logical means (NAND) for inputting the output signals of the first and second inverters INV1 and INV2 and the row address strobe signal (/ RAS). It consists of the 3rd inverter INV3 which makes an input signal.

When a column sequence read command or a column sequence write command is applied to the command processor 410, the column address strobe signal (Column Address Strobe, / CAS) and the chip select signal (/ CS) are brought to a low level. When activated, the internal signal CMD is output at a high level. The clock delay unit 420 outputs the output clock CLKD by delaying the clock signal CLK for a predetermined time in consideration of the internal signal CMD, and the signal generator 430 outputs the output clock CLKD and the internal signal. The internal column signal CASP6 is generated in response to the CMD.

5 is a circuit diagram according to another embodiment of an internal column signal generator.

Referring to FIG. 5, the internal column signal generation unit may include a command processor 510 for outputting an internal signal CMD that is activated when a column sequence read command or a column sequence write command is applied, and a clock signal. A switching unit 520 for selectively transferring the internal signal CMD in response to CLK, and an internal column signal CASP6 corresponding to an output signal of the switching unit 520 in response to the clock signal CLK. It consists of an output unit 530 for outputting.

The command processor 510 may include a first inverter INV1 inputting a column address strobe signal / CAS and a second inverter INV2 inputting a chip select signal / CS. Negative logical means (NAND1) and negative logic means (NAND1) for inputting the output signals of the first and second inverters INV1 and INV2 and the row address strobe signal (/ RAS). It consists of the 3rd inverter INV3 which makes an input signal.

In addition, the switching unit 520 outputs the internal signal CMD in response to the inverter INV4 inputting the clock signal CLK, and the output signal CLKB of the clock signal CLK and the inverter INV4. It consists of a transmission gate (TG) for.

In addition, the output unit 530 is a delay unit 531 for delaying the signal output from the switching unit 520, and negative logic means for inputting the clock signal CLK and the output signal of the delay unit 531 as input. NAND2 and an inverter INV7 for inverting the output signal of the negative logical means NAND2. Here, the delay unit 531 includes a plurality of inverters INV5 and INV6 connected in series with each other.

When the column sequence read command or the column sequence write command is applied to the command processor 510, the internal column signal generation unit configured as described above may generate a column address strobe signal and a chip. The select signal / CS is activated at a low level so that the internal signal CMD is output at a high level. The switching unit 520 selectively outputs the internal signal CMD under the control of the clock signal CLK, and finally outputs the internal column signal CASP6 from the output unit 530. FIG. 5 shows that the internal column signal generator is applied with the clock signal CLK and the internal column signal CASP6 is output immediately after the delay times of the two inverters INV5 and INV6. The generation time of the internal column signal CASP6 is fast.

As described above, the semiconductor memory device to which the present invention is applied generates an internal voltage activation signal in response to an internal column signal activated when a command such as a column series read command or a write command is applied. In response to the activation signal, an internal voltage generated during a read operation or a write operation period is generated.

In the above, the specific description was made according to the embodiment of the present invention. Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the configuration of an active high or an active low to indicate an activation state of a signal and a circuit may vary according to embodiments. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary. In addition, the configuration of the logic gate may be changed as necessary to implement the same function. That is, the negative logical means, the negative logical sum means, etc. may be configured through various combinations such as NAND GATE, NOR GATE, and INVERTER. Such a change in the circuit is too many cases, and the change can be easily inferred by a person skilled in the art, so the enumeration thereof will be omitted.

1 is a block diagram of a semiconductor memory device of the prior art.

2 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

3 is a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

4 is a circuit diagram according to an embodiment of an internal column signal generator.

5 is a circuit diagram according to another embodiment of an internal column signal generator.

* Explanation of symbols for the main parts of the drawings

410, 510: command processing unit

430: signal generator

520: switching unit

530: output unit

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (17)

delete delete delete delete delete An internal column signal generator for generating an internal column signal activated when a command is applied; An internal delay column signal generator for generating an internal delay column signal by reflecting a read latency or a write latency to the internal column signal; An activation signal generator for generating an internal voltage activation signal in response to the internal column signal; And An internal voltage generator for generating an internal voltage in response to the internal voltage activation signal; A semiconductor memory device having a. The method of claim 6, And the command includes a column series read command and a write command. The method of claim 7, wherein And the column sequence read command includes a row address strobe signal, a column address strobe signal, and a chip select signal. The method of claim 7, wherein The column write command includes a row address strobe signal, a column address strobe signal, and a chip select signal. The method according to any one of claims 6 to 9, And wherein the internal voltage is used during a read operation or a write operation period. The method of claim 6, The internal column signal generator, A command processor for outputting an internal signal activated when the command is applied; A switching unit for selectively transferring the internal signal in response to a clock signal; And And an output unit for outputting the internal column signal corresponding to the output signal of the switching unit in response to the clock signal. The method of claim 11, The command processing unit, A first inverter for inputting a column address strobe signal; A second inverter configured to receive a chip select signal; Negative logical means for inputting output signals and row address strobe signals of the first and second inverters; And And a third inverter for accepting a signal output from the negative logical means. The method of claim 11, The switching unit, An inverter configured to receive the clock signal; And And a transmission gate for outputting the internal signal in response to the clock signal and an output signal of the inverter. The method of claim 11, The output unit, A delay unit for delaying a signal output from the switching unit; Negative logical means for inputting the clock signal and the output signal of the delay unit; And And an inverter for inverting the output signal of the negative logical means. The method of claim 14, The delay unit includes a plurality of inverters connected in series with each other. The method of claim 6, The internal column signal generator, A command processor for outputting an internal signal activated when the command is applied; A clock delay unit for delaying a clock signal; And And a signal generator configured to generate the internal column signal in response to a signal output from the clock delay unit as a differential input using the internal signal and the inverted signal of the internal signal as differential inputs. The method of claim 16, The command processing unit, A first inverter for inputting a column address strobe signal; A second inverter configured to receive a chip select signal; Negative logical means for inputting output signals and row address strobe signals of the first and second inverters; And And a third inverter for accepting a signal output from the negative logical means.

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