KR20120053907A - Semiconductor memory device - Google Patents

Abstract

Embodiments of the present invention relate to a semiconductor memory device, and in particular, a technique for stably driving a word line of a memory device having a sub word line driver. Embodiments of the present invention provide a mat including a word line, a main word line, a word line driver selectively driving a word line corresponding to a driving signal in response to a first selection signal, and a word line driver based on a mat. It is provided on the opposite side and includes a voltage supply for supplying a word line driving voltage to the word line in the active operation.

Description

Semiconductor memory device

Embodiments of the present invention relate to a semiconductor memory device and a technology related to a semiconductor memory device including a sub word line driver.

The semiconductor memory device includes a word line, a bit line, and a memory cell, among which a word line uses a boost voltage VPP as a gate input.

Thus, the semiconductor memory device includes a word line driver corresponding to the number of word lines to drive the word lines.

1 is a block diagram of a semiconductor memory device according to the prior art.

The semiconductor memory device according to the prior art includes a plurality of word line drivers WD1 to WD4 and a mat MAT.

The mat MAT, which is a group of memory cells, includes a plurality of word lines WL0 to WL6, and the plurality of word line drivers WD1 to WD4 are connected to the plurality of word lines WL0 to WL6, respectively.

Each of the word line drivers WD1 to WD4 includes a PMOS transistor P1 and NMOS transistors N1 and N2.

Here, the PMOS transistor P1 is connected between the driving signal FX <0> applying end and the word line WL0 so that the gate terminal is connected to the main word line MWLB. The NMOS transistor N1 is connected between the PMOS transistor P1 and the ground voltage terminal VSSW so that the gate terminal is connected to the main word line MWLB. In addition, the NMOS transistor N2 is connected between the word line WL0 and the ground voltage terminal VSSW, and the selection signal FXb <0> is applied through the gate terminal.

The PMOS transistor P1 selectively drives the word line WL0 in response to the activation state of the main wordline MWLB. The NMOS transistor N1 selectively drives the word line WL0 in response to the activation state of the main word line MWLB. In addition, the NMOS transistor N2 selectively drives the word line WL0 in response to the activation state of the selection signal FXb <0>.

The PMOS transistor P1 is connected to the drive signal FX <0> having the level of the boosted voltage VPP. The drive signal FX <0> corresponds to the inverted signal of the selection signal FXb <0>.

That is, the plurality of word line drivers WD1 to WD4 generate the drive signal FX by inverting the input selection signal FXb, and drive the word line WL using the word line drive signal FX.

In such a conventional semiconductor memory device, word line drivers WD1 to WD4 are arranged only on one side of the word lines WL0, WL2, WL4, and WL6, that is, the left side of the mat MAT.

However, in the active operation, the cell farthest from the word line drivers WD1 to WD4 lacks the delay of the boost voltage VPP and the supply capability of the boost voltage VPP.

In this case, the time for the word line WL to reach the normal boosted voltage VPP level is longer in the cell farther from the word line driver WD1 to WD4 than the cell close to the word line drivers WD1 to WD4.

In addition, during the precharge operation, the cells farthest from the wordline drivers WD1 to WD4 are more likely to be delayed to the ground voltage VSSW level than the cells close to the wordline drivers WD1 to WD4.

In this case, the cell farthest from the wordline drivers WD1 to WD4 is vulnerable in terms of Delta V because the voltage level of the data output through the gate is relatively lower than that of the close cell.

In addition, the possibility of a failure of tRCD (RAS to CAS Delay Time) is increased, and the possibility of a tRP failure due to a delay time when the word line WL is turned off increases.

Here, tRCD means a time from when the word line is driven by applying an active command until the read strobe signal is activated in response to the read command.

In addition, tRP means a time from when a precharge command is input to when a next active command is input.

Currently, semiconductor devices are making great efforts to reduce the line widths of gates and bit lines due to improved productivity and higher integration.

In addition, the mat size is increasing in order to increase the number of net dies in the same tech. As the size of the mat increases, the cells farthest from the wordline drivers WD1 to WD4 are more likely to encounter tRCD and tRP failures.

Embodiments of the present invention have the following features.

First, the present invention is connected to a voltage supply controlled by the main word line (MWLb) and the selection signal (FXb) at the end of the word line opposite the word line driver, so that the cell at the end of the word line driver in the active operation is stable. It has a characteristic that can supply a boosted voltage VPP.

Second, the present invention is characterized by separating the selection signal FXb into two signals and differently activating time points of the two signals, thereby stably securing the tRP characteristic during the precharge operation.

A semiconductor memory device according to an embodiment of the present invention, a mat comprising a word line; A word line driver selectively driving a word line corresponding to the driving signal in response to the main word line and the first selection signal; And a voltage supply unit provided opposite to the word line driver based on the mat and supplying a word line driving voltage to the word line during an active operation.

An embodiment of the present invention has the following effects.

First, an embodiment of the present invention connects a voltage supply to an end of a word line opposite to a word line driver to supply a stable boost voltage (VPP) to a cell located at the end of the word line driver during active operation, thereby preventing tRCD failure. To help.

Second, the embodiment of the present invention separates the selection signal FXb into two signals and changes the activation time of the two signals, thereby providing an effect of stably securing the tRP characteristic during the precharge operation.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is a block diagram of a conventional semiconductor memory device.
2 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.
3 is a configuration diagram of a selection signal generation unit for generating first and second selection signals in FIG.
4 is a circuit diagram of a control signal generator of FIG. 3.
FIG. 5 is a timing diagram for each signal in the control signal generator of FIG. 3. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

An embodiment of the present invention includes a plurality of word line drivers WD5 to WD8, a mat MAT and a plurality of voltage supply units 100 to 130.

The mat MAT, which is a group of memory cells, includes a plurality of word lines WL0 to WL6. In the exemplary embodiment of the present invention, the even word lines WL0 to WL6 are included in the mat MAT as an example. However, the present invention is not limited thereto, and the odd word lines may be included in the mat MAT.

The plurality of word line drivers WD5 to WD8 are connected to the plurality of word lines WL0 to WL6, respectively. The word line drivers WD5 to WD8 described in the embodiment of the present invention mean sub word line drivers.

Here, the word line driver WD5 includes a PMOS transistor P2 and NMOS transistors N3 and N4.

The PMOS transistor P2 is connected between the driving signal FX <0> applying terminal and the word line WL0 so that the gate terminal is connected to the main word line MWLB. PMOS transistor P2 selectively drives wordline WL0 in response to the activation state of main wordline MWLB.

The NMOS transistor N3 is connected between the PMOS transistor P2 and the ground voltage terminal VSSW so that the gate terminal is connected to the main word line MWLB. The NMOS transistor N3 selectively drives the word line WL0 in response to the activation state of the main word line MWLB.

In addition, the NMOS transistor N4 is connected between the word line WL0 and the ground voltage terminal VSSW, and the selection signal FXb1 <0> is applied through the gate terminal. The NMOS transistor N3 selectively drives the word line WL0 in response to the activation state of the selection signal FXb1 <0>.

The word line driver WD6 includes a PMOS transistor P3 and NMOS transistors N5 and N6.

The PMOS transistor P3 is connected between the driving signal FX <2> applying end and the word line WL2 so that the gate terminal is connected to the main word line MWLB. PMOS transistor P3 selectively drives wordline WL2 in response to the activation state of main wordline MWLB.

The NMOS transistor N5 is connected between the PMOS transistor P3 and the ground voltage terminal VSSW so that the gate terminal is connected to the main word line MWLB. The NMOS transistor N5 selectively drives the word line WL2 in response to the activation state of the main word line MWLB.

In addition, the NMOS transistor N6 is connected between the word line WL2 and the ground voltage terminal VSSW, and the selection signal FXb1 <2> is applied through the gate terminal. The NMOS transistor N6 selectively drives the word line WL2 in response to the activation state of the selection signal FXb1 <2>.

The word line driver WD7 includes a PMOS transistor P4 and NMOS transistors N7 and N8.

The PMOS transistor P4 is connected between the driving signal FX <4> applying end and the word line WL4 so that the gate terminal is connected to the main word line MWLB. The PMOS transistor P4 selectively drives the wordline WL4 in response to the activation state of the main wordline MWLB.

The NMOS transistor N7 is connected between the PMOS transistor P4 and the ground voltage terminal VSSW so that the gate terminal is connected to the main word line MWLB. The NMOS transistor N7 selectively drives the word line WL4 in response to the activation state of the main word line MWLB.

In addition, the NMOS transistor N8 is connected between the word line WL4 and the ground voltage terminal VSSW, and the selection signal FXb1 <4> is applied through the gate terminal. The NMOS transistor N8 selectively drives the word line WL4 in response to the activation state of the selection signal FXb1 <4>.

The word line driver WD8 also includes a PMOS transistor P5 and NMOS transistors N9 and N10.

The PMOS transistor P5 is connected between the driving signal FX <6> applying end and the word line WL6 so that the gate terminal is connected to the main word line MWLB. PMOS transistor P5 selectively drives wordline WL6 in response to the activation state of main wordline MWLB.

The NMOS transistor N9 is connected between the PMOS transistor P5 and the ground voltage terminal VSSW so that the gate terminal is connected to the main word line MWLB. The NMOS transistor N10 selectively drives the word line WL6 in response to the activation state of the main word line MWLB.

In addition, the NMOS transistor N10 is connected between the word line WL6 and the ground voltage terminal VSSW, and the selection signal FXb1 <6> is applied through the gate terminal. The NMOS transistor N10 selectively drives the word line WL6 in response to the activation state of the selection signal FXb1 <6>.

The voltage supply unit 100 includes PMOS transistors P6 and P7 and an NMOS transistor N11.

The PMOS transistors P6 and P7 are connected in series between the word line WL0 and the boost voltage VPP applying terminal. The PMOS transistor P6 has a gate terminal connected to the main word line MWLb. The PMOS transistor P7 receives the selection signal FXb <0> through the gate terminal. Here, the boosted voltage VPP corresponds to a word line driving voltage. The PMOS transistor P7 corresponds to a first driver for selectively supplying a boosted voltage VPP to the word line WL0.

The NMOS transistor N11 is connected between the word line WL0 and the back bias voltage VBB so that the selection signal FXb2 <0> is applied through the gate terminal. Here, the NMOS transistor N11 corresponds to the second driver which selectively supplies the back bias voltage VBB to the word line WL0.

The voltage supply unit 110 includes PMOS transistors P8 and P9 and an NMOS transistor N12.

The PMOS transistors P8 and P9 are connected in series between the word line WL2 and the boost voltage VPP applying terminal. The PMOS transistor P8 has a gate terminal connected to the main word line MWLb. The PMOS transistor P9 receives the selection signal FXb <2> through the gate terminal.

The NMOS transistor N12 is connected between the word line WL2 and the back bias voltage VBB so that the selection signal FXb2 <2> is applied through the gate terminal.

In addition, the voltage supply unit 120 includes PMOS transistors P10 and P11 and an NMOS transistor N13.

The PMOS transistors P10 and P11 are connected in series between the word line WL4 and the boost voltage VPP applying terminal. The PMOS transistor P10 has a gate terminal connected to the main word line MWLb. The selection signal FXb <4> is applied to the PMOS transistor P11 through the gate terminal.

The NMOS transistor N13 is connected between the word line WL4 and the back bias voltage VBB so that the selection signal FXb2 <4> is applied through the gate terminal.

In addition, the voltage supply unit 130 includes PMOS transistors P12 and P13 and an NMOS transistor N14.

The PMOS transistors P12 and P13 are connected in series between the word line WL6 and the boost voltage VPP applying terminal. The PMOS transistor P12 has a gate terminal connected to the main word line MWLb. The selection signal FXb <6> is applied to the PMOS transistor P13 through the gate terminal.

The NMOS transistor N14 is connected between the word line WL6 and the back bias voltage VBB so that the selection signal FXb2 <6> is applied through the gate terminal.

FIG. 3 is a block diagram of the selection signal generator 200 for generating the selection signals FXb1 and FXb2 of FIG. 2.

The selection signal generator 200 includes a driver 210 and a control signal generator 220.

Here, the driver 210 is a block for generating a selection signal FXb for selecting a word line.

The control signal generator 220 differently adjusts delay times of the selection signal FXb1 and the selection signal FXb2 according to the selection signal FXb.

4 is a detailed circuit diagram illustrating the control signal generator 220 of FIG. 3.

The control signal generator 220 includes a plurality of inverters IV1 to IV11 and a plurality of NAND gates ND1 and ND2.

Here, the plurality of inverters IV1 to IV4 delay non-inverting the selection signal FXb for the delay time D1. The NAND gate ND1 performs a NAND operation on the selection signal FXb and the output of the inverter IV4. Inverter IV5 inverts the output of NAND gate ND1 and outputs selection signal FXb1. NAND gate ND1 and inverter IV5 correspond to the first logical combination part.

Although the number of inverters IV1 to IV4 has been described as four in the embodiment of the present invention, the number of inverters in the embodiment of the present invention is not limited to four, but may include an even number of inverters for non-inverting delay of the selection signal FXb.

The plurality of inverters IV6 to IV10 delay invert the selection signal FXb for the delay time D2. The NAND gate ND2 performs a NAND operation on the selection signal FXb and the output of the inverter IV10. The inverter IV11 inverts the output of the NAND gate ND2 and outputs the selection signal FXb2. NAND gate ND2 and inverter IV11 correspond to the 2nd logical combination part.

In the embodiment of the present invention, the number of inverters IV6 to IV10 has been described as five, but in the embodiment of the present invention, the number of inverters is not limited to five, but may include an odd number of inverters inverting the selection signal FXb.

FIG. 5 is a timing diagram for each selection signal in the control signal generator 220 of FIG. 3.

The selection signal FXb maintains a low level in the T1 period, and is activated to a high level in the T2 period when the word line WL is selected.

The selection signal FXb2 is activated to a high level in the same manner as the selection signal FXb in the T2 section. Then, the selection signal FXb2 transitions to the low level after maintaining the high level for the delay time D1.

In addition, the selection signal FXb1 maintains the low level for the delay time D2 after the selection signal FXb is enabled at the high level in the T2 period. After the selection signal FXb is enabled at the high level, the signal transitions to the high level when the delay time D2 passes. Here, the delay time D2 should be shorter than the delay time D1.

At this time, the section from the selection signal FXb1 to the high level until the selection signal FXb2 becomes the low level corresponds to the section T3. In other words, the T3 section corresponds to the delay time D1 minus the delay time D2.

An operation process of the semiconductor memory device according to the embodiment of the present invention having such a configuration will be described with reference to Table 1 below.

In the embodiment of the present invention, a case where the word line driver WD5 and the voltage supply unit 100 are selected will be described as an example.

section FXb FXb2 FXb1 condition T1 L L L WL ON T2 H H L
WL OFF
T3 H H H T4 H L H

First, all selection signals FXb, FXb2, and FXb1 maintain a low level in the T1 section in which the active operation is performed. At this time, when the selection signal FXb is at the low level, the driving signal FX is at the boosted voltage VPP level. Accordingly, when the main word line MWLB becomes low when the word line is selected, the PMOS transistor P2 is turned on, and the word line WL0 becomes the boosted voltage VPP level.

In addition, when the selection signal FXb is at a low level, only the PMOS transistor P7 is turned on, and both the NMOS transistors N11 and N14 are turned off. Accordingly, when the main word line MWLB becomes low, the PMOS transistor P6 is turned on, and the word line WL0 is at the boosted voltage VPP level.

Accordingly, the boosted voltage VPP can be stably supplied to the cell close to the word line driver WD5.

In addition, the step-up voltage VPP can be stably supplied to the cell far from the word line driver WD5 by the voltage supply unit 100 to prevent tRCD failure due to a lack of delta V. In addition, even if the size of the mat is increased due to a net die problem, the boosted voltage VPP is supplied to both sides of the word line WL, so that the DRAM cell can be stably driven.

Thereafter, in the T2 section in which the precharge operation is performed, the selection signals FXb and FXb2 become high levels, and the selection signals FXb1 become low levels. Then, the PMOS transistor P7 and the NMOS transistor N4 are turned off and the NMOS transistor N11 is turned on. Accordingly, the word line WL becomes the back bias voltage VBB level at the boosted voltage VPP level.

At this time, if the selection signal FXb is at a high level, the selection signal FX is at a low level, and the word line WL is in an inactive state.

Subsequently, in the T3 section, the selection signals FXb, FXb2, and FXb1 all become high levels. Then, the PMOS transistor P7 is turned off and the NMOS transistors N4 and N11 are turned on. As a result, the word line WL becomes the back bias voltage VBB level.

At this time, if the selection signal FXb is at a high level, the selection signal FX is at a low level, and the word line WL is in an inactive state.

Next, in the T4 section, the selection signals FXb and FXb1 become high levels, and the selection signals FXb2 transition to low levels. Then, the PMOS transistor P7 and the NMOS transistor N11 are turned off and the NMOS transistor N4 is turned on. As a result, the word line WL becomes the ground voltage VSSW level. Here, the ground voltage VSSW level may be the same as the back bias voltage VBB, or may be a high voltage level.

At this time, if the selection signal FXb is at a high level, the selection signal FX is at a low level, and the word line WL is in an inactive state.

In the embodiment of the present invention, the select signal FXb2 is first activated to a high level in the T2 period to shorten the word line WL0 to the back bias voltage VBB level.

After a predetermined time (delay time D1), the selection signal FXb1 is activated to a high level in the T4 section to precharge the word line WL0 to the ground voltage VSSW level, thereby maintaining the tRP time stably.

Claims (15)

A mat comprising a word line;
A word line driver for selectively driving the word line corresponding to the driving signal in response to a main word line and a first selection signal; And
And a voltage supply unit provided opposite to the word line driver based on the mat and supplying a word line driving voltage to the word line during an active operation. The method of claim 1, wherein the voltage supply unit
And selectively supplying the word line driving voltage to the word line by the main word line, the second selection signal, and the third selection signal. The semiconductor memory device of claim 2, wherein the word line driving voltage is at a boost voltage level. The semiconductor memory device of claim 2, wherein the driving signal is an inversion signal of the second selection signal. The semiconductor memory device of claim 2, further comprising a control signal generator configured to selectively delay the second selection signal for a predetermined time and selectively activate the first selection signal and the third selection signal at different timings. . The method of claim 5, wherein the control signal generator
A first delay unit for delaying the second selection signal for a first delay time;
A first logic combining unit for logically combining the output of the first delay unit and the second selection signal to output the first selection signal;
A second delay unit configured to delay the second selection signal for a second delay time longer than the first delay time; And
And a second logical combination unit configured to logically combine the output of the second delay unit and the second selection signal to output the third selection signal. 7. The semiconductor memory device of claim 6, wherein the first delay unit includes an even number of inverters.  7. The semiconductor memory device of claim 6, wherein the second delay unit comprises an odd number of inverters. The semiconductor memory device of claim 2, wherein the second selection signal maintains a low level during an active operation and is activated to a high level during a precharge operation. The semiconductor memory device of claim 2, wherein the third selection signal maintains a high level for a first delay time when the second selection signal is activated. The semiconductor memory device of claim 2, wherein the first selection signal is activated to a high level after a second delay time after the second selection signal is activated. The method of claim 2, wherein the voltage supply unit
A first driver configured to supply the word line driving voltage to the word line by the second selection signal during the active operation when the main word line is activated; And
And a second driver configured to supply a first voltage to the word line by the third selection signal during a precharge operation. 13. The semiconductor memory device of claim 12, wherein the first voltage has a back bias voltage level. 3. The display device of claim 2, wherein the first voltage is supplied to the word line by the third selection signal during a precharge operation, and has a second level different from the first voltage by the first selection signal after a predetermined time. And a voltage is supplied to the word line. 15. The semiconductor memory device of claim 14, wherein the second voltage has a ground voltage level.

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