KR20250127577A - Display device - Google Patents

Abstract

A display device according to one embodiment of the present specification includes a substrate on which a plurality of sub-pixels are defined, a light-emitting element disposed in each of the plurality of sub-pixels, and a first connection electrode in contact with a side surface of the light-emitting element, wherein the light-emitting element includes a first semiconductor layer on the substrate, a light-emitting layer on the first semiconductor layer, a second semiconductor layer on the light-emitting layer, a first electrode on a lower surface of the first semiconductor layer, a second electrode on an upper surface of the second semiconductor layer, an expansion electrode surrounding the first electrode, the side surface and the lower surface of the first semiconductor layer, the side surface of the light-emitting layer, and a portion of the side surface of the second semiconductor layer, and an encapsulation film disposed between the expansion electrode and the first semiconductor layer, between the expansion electrode and the light-emitting layer, and between the expansion electrode and the second semiconductor layer, wherein the first connection electrode is in contact with the side surface of the expansion electrode. Therefore, by forming the expansion electrode having a larger area than the first electrode on the light-emitting element, the first connection electrode and the light-emitting element can be more easily electrically connected.

Description

DISPLAY DEVICE

This specification relates to a display device, and more specifically, to a display device using an LED (Light Emitting Diode).

Display devices used in computer monitors, TVs, and cell phones include organic light-emitting displays (OLEDs) that emit light on their own, and liquid crystal displays (LCDs) that require a separate light source.

The application range of display devices is expanding beyond computer monitors and TVs to include personal mobile devices, and research is being conducted on display devices that have a large display area while also having reduced volume and weight.

Furthermore, display devices incorporating LEDs have recently been attracting attention as next-generation display devices. Because LEDs are made of inorganic rather than organic materials, they boast superior reliability and a longer lifespan than liquid crystal displays or organic light-emitting diode displays. Furthermore, LEDs not only light up quickly, but also boast superior luminous efficiency, high impact resistance, and stability, enabling them to display high-brightness images.

The problem that this specification seeks to solve is to provide a display device that minimizes short circuits of a connecting electrode that contacts the side of a light-emitting element.

Another problem that the present specification seeks to solve is to provide a display device including a light-emitting element with an expanded electrode area.

Another problem that the present specification seeks to solve is to provide a display device in which a light-emitting element and a first connection electrode can be easily electrically connected by forming an enlarged electrode having a larger area on the light-emitting element.

Another problem that the present specification seeks to solve is to provide a display device including a light-emitting element manufactured using an enlarged electrode as a mask.

Another problem that the present specification seeks to solve is to provide a display device in which a protrusion of a second semiconductor layer is arranged on the upper surface of the enlarged electrode, thereby reducing short-circuit defects between the enlarged electrode and the connection electrode.

Another problem that the present specification seeks to solve is to provide a display device in which the side surface of the second semiconductor layer is positioned inward from the side surface of the expansion electrode, thereby reducing the short-circuit defect between the second semiconductor layer and the first connection electrode.

Another problem that the present specification seeks to solve is to provide a display device in which the light extraction efficiency of a light-emitting element is improved by forming a reflective layer on the light-emitting element.

Another problem that this specification seeks to solve is to provide a display device in which the light extraction efficiency of a light emitting element is improved by forming a patterned layer with a rough structure on the upper surface of the light emitting element.

Another challenge that this specification seeks to address is to provide a display device that minimizes electrode connection failure due to alignment errors of light-emitting elements.

The tasks of this specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to one embodiment of the present specification includes a substrate on which a plurality of sub-pixels are defined, a light-emitting element disposed in each of the plurality of sub-pixels, and a first connection electrode in contact with a side surface of the light-emitting element, wherein the light-emitting element includes a first semiconductor layer on the substrate, a light-emitting layer on the first semiconductor layer, a second semiconductor layer on the light-emitting layer, a first electrode on a lower surface of the first semiconductor layer, a second electrode on an upper surface of the second semiconductor layer, an expansion electrode surrounding the first electrode, the side surface and the lower surface of the first semiconductor layer, the side surface of the light-emitting layer, and a portion of the side surface of the second semiconductor layer, and an encapsulation film disposed between the expansion electrode and the first semiconductor layer, between the expansion electrode and the light-emitting layer, and between the expansion electrode and the second semiconductor layer, wherein the first connection electrode is in contact with the side surface of the expansion electrode. Therefore, by forming the expansion electrode having a larger area than the first electrode on the light-emitting element, the first connection electrode and the light-emitting element can be more easily electrically connected.

Specific details of other embodiments are included in the detailed description and drawings.

This specification can minimize the disconnection of the connecting electrode in contact with the side of the light-emitting element by making the side of the light-emitting element have a vertical plane or a tapered shape.

This specification expands the area of the electrode of the light-emitting element, thereby making it easier to electrically connect the light-emitting element and the connecting electrode.

This specification allows for easy manufacture of a light-emitting element using an enlarged electrode as a mask.

This specification can prevent a short circuit defect in which the expansion electrode and the second connection electrode are connected by forming a protrusion of a second semiconductor layer on the upper surface of the expansion electrode.

This specification can prevent a short circuit defect in which the second semiconductor layer and the first connection electrode are connected by arranging the side of the second semiconductor layer inward from the side of the expansion electrode.

This specification can reduce power consumption and drive a display device with low power by forming a reflective layer on a light-emitting element to improve the light extraction efficiency of the light-emitting element.

The present specification can provide a high-brightness display device by forming a patterned layer with a rough structure on the upper surface of a light-emitting element to improve the light extraction efficiency of the light-emitting element.

This specification can minimize electrode connection failure due to alignment error of the light emitting element by forming a plurality of contact holes on the light emitting element.

The effects according to this specification are not limited to the contents exemplified above, and more diverse effects are included in this specification.

FIG. 1 is a schematic diagram of a display device according to one embodiment of the present specification.
FIG. 2A is a partial cross-sectional view of a display device according to one embodiment of the present specification.
FIG. 2b is a perspective view of a tiling display device according to one embodiment of the present specification.
FIG. 3 is a cross-sectional view of a sub-pixel of a display device according to one embodiment of the present specification.
FIGS. 4A to 4F are process diagrams for explaining a method for manufacturing a light-emitting element of a display device according to one embodiment of the present specification.
FIGS. 4g to 4i are process diagrams for explaining a method of manufacturing a display device according to one embodiment of the present specification.
FIG. 5 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present specification.
FIG. 6 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present specification.
FIG. 7 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present specification.
FIG. 8 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present specification.

The advantages and features of this specification, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure the complete disclosure of this specification and to fully inform those skilled in the art of the invention of the scope of the invention.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative and are not limited to the matters illustrated in this specification. Like reference numerals refer to like components throughout the specification. In addition, in describing this specification, if a detailed description of a related known technology is judged to unnecessarily obscure the gist of this specification, the detailed description thereof will be omitted. When "includes," "has," "consists of," etc. are used in this specification, other parts may be added unless "only" is used. When a component is expressed in the singular, it includes a case where the plural is included unless there is a specifically explicit description.

When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

When describing a positional relationship, for example, when the positional relationship between two parts is described as 'on top of', 'upper part of', 'lower part of', 'next to', etc., one or more other parts may be located between the two parts, unless 'right away' or 'directly' is used.

When an element or layer is referred to as being "on" another element or layer, it includes both cases where the other element is directly on top of the other element or layer or where another layer or layer is interposed therebetween.

While terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Thus, a "first" component referred to below may also be a "second" component within the technical scope of this specification.

Identical reference numerals throughout the specification refer to identical components.

The area and thickness of each component shown in the drawing are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the component shown.

The individual features of the various embodiments of this specification may be partially or wholly combined or combined with each other, and may be technically linked and operated in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

Hereinafter, the present specification will be described with reference to the drawings.

Fig. 1 is a schematic diagram of a display device according to one embodiment of the present specification. For convenience of explanation, in Fig. 1, only a display panel (PN), a gate driver (GD), a data driver (DD), and a timing controller (TC) among various components of the display device (100) are illustrated.

Referring to FIG. 1, a display device (100) includes a display panel (PN) including a plurality of sub-pixels (SP), a gate driver (GD) and a data driver (DD) that supply various signals to the display panel (PN), and a timing controller (TC) that controls the gate driver (GD) and the data driver (DD).

A gate driver (GD) supplies multiple scan signals to multiple scan lines (SL) according to multiple gate control signals provided from a timing controller (TC). In Fig. 1, one gate driver (GD) is illustrated as being spaced apart from one side of a display panel (PN), but the number and arrangement of the gate drivers (GD) are not limited thereto.

The data driver (DD) supplies data voltages to a plurality of data lines (DL) according to a plurality of data control signals and image data provided from the timing controller (TC). The data driver (DD) can convert image data into data voltages using a reference gamma voltage and supply the converted data voltages to a plurality of data lines (DL).

The timing controller (TC) aligns image data input from the outside and supplies it to the data driver (DD). The timing controller (TC) can generate a gate control signal and a data control signal using externally input synchronization signals, such as a dot clock signal, a data enable signal, and a horizontal/vertical synchronization signal. In addition, the timing controller (TC) can supply the generated gate control signal and data control signal to the gate driver (GD) and the data driver (DD), respectively, to control the gate driver (GD) and the data driver (DD).

A display panel (PN) is configured to display an image to a user and includes a plurality of sub-pixels (SP). In the display panel (PN), a plurality of scan lines (SL) and a plurality of data lines (DL) may intersect each other, and a plurality of sub-pixels (SP) may be formed at the intersections of the scan lines (SL) and the data lines (DL).

A display panel (PN) can have a display area (AA) and a non-display area (NA) defined.

The display area (AA) is an area in which an image is displayed in the display device (100). In the display area (AA), a plurality of sub-pixels (SP) constituting a plurality of pixels (PX) and pixel circuits for driving the plurality of sub-pixels (SP) may be arranged. The plurality of sub-pixels (SP) are the minimum units constituting the display area (AA), and n sub-pixels (SP) may form one pixel (PX). Thin film transistors for driving a plurality of light-emitting elements may be arranged in each of the plurality of sub-pixels (SP). The plurality of light-emitting elements may be defined differently depending on the type of the display panel (PN). For example, when the display panel (PN) is an inorganic light-emitting display panel, the light-emitting elements may be light-emitting diodes (LEDs) or micro light-emitting diodes (micro LEDs).

In the display area (AA), a plurality of signal wires for transmitting various signals to a plurality of sub-pixels (SP) are arranged. For example, the plurality of signal wires may include a plurality of data wires (DL) for supplying data voltages to each of the plurality of sub-pixels (SP), a plurality of scan wires (SL) for supplying scan signals to each of the plurality of sub-pixels (SP), etc. The plurality of scan wires (SL) may extend in one direction in the display area (AA) and be connected to the plurality of sub-pixels (SP), and the plurality of data wires (DL) may extend in a direction different from the one direction in the display area (AA) and be connected to the plurality of sub-pixels (SP). In addition, low-potential power wires, high-potential power wires, etc. may be further arranged in the display area (AA), but are not limited thereto.

The non-display area (NA) is an area where no image is displayed, and can be defined as an area extending from the display area (AA). Link wiring and pad electrodes for transmitting signals to sub-pixels (SPs) in the display area (AA), or driver ICs such as gate driver ICs and data driver ICs, can be placed in the non-display area (NA).

Meanwhile, the non-display area (NA) may be located on the back surface of the display panel (PN), i.e., on a surface without sub-pixels (SP), or may be omitted, and is not limited to that shown in the drawing.

Meanwhile, driving units such as the gate driver (GD), data driver (DD), and timing controller (TC) can be connected to the display panel (PN) in various ways. For example, the gate driver (GD) can be mounted in the non-display area (NA) in a gate-in-panel (GIP) manner, or can be mounted in the display area (AA) between multiple sub-pixels (SP) in a gate-in-active area (GIA) manner.

For example, the data driver (DD) and the timing controller (TC) are formed on separate flexible films and printed circuit boards, and the display panel (PN) and the data driver (DD) and the timing controller (TC) can be electrically connected by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area (NA) of the display panel (PN).

For another example, when a gate driver (GD) is mounted inside a display area (AA) in a GIA manner, and a side wire (SRL) is formed to connect a signal wire on the front surface of the display panel (PN) to a pad electrode on the back surface of the display panel (PN), and a flexible film and a printed circuit board are bonded to the back surface of the display panel (PN), the non-display area (NA) on the front surface of the display panel (PN) can be minimized. Accordingly, when the gate driver (GD), the data driver (DD), and the timing controller (TC) are connected to the display panel (PN) in the above manner, a zero bezel implementation in which a bezel practically does not exist can be possible, and a more detailed description will be given with reference to FIGS. 2A and 2B.

FIG. 2A is a partial cross-sectional view of a display device according to one embodiment of the present disclosure. FIG. 2B is a perspective view of a tiling display device according to one embodiment of the present disclosure.

A plurality of pad electrodes are arranged in a non-display area (NA) of a display panel (PN) to transmit various signals to a plurality of sub-pixels (SP). For example, a first pad electrode (PAD1) that transmits signals to a plurality of sub-pixels (SP) is arranged in a non-display area (NA) on the front surface of the display panel (PN), and a second pad electrode (PAD2) that is electrically connected to driving components such as a flexible film and a printed circuit board is arranged in a non-display area (NA) on the back surface of the display panel (PN).

In this case, although not shown in the drawing, various signal wires connected to a plurality of sub-pixels (SP), such as scan wires (SL) or data wires (DL), may extend from the display area (AA) to the non-display area (NA) and be electrically connected to the first pad electrode (PAD1).

And a side wiring (SRL) is arranged along the side of the display panel (PN). The side wiring (SRL) can electrically connect a first pad electrode (PAD1) on the front surface of the display panel (PN) and a second pad electrode (PAD2) on the back surface of the display panel (PN). Accordingly, a signal from a driving component on the back surface of the display panel (PN) can be transmitted to a plurality of sub-pixels (SP) through the second pad electrode (PAD2), the side wiring (SRL), and the first pad electrode (PAD1). Accordingly, a signal transmission path is formed from the front surface of the display panel (PN) to the side and back surfaces, thereby minimizing the area of the non-display area (NA) on the front surface of the display panel (PN).

And referring to Fig. 2b, a tiling display device (TD) having a large screen can be implemented by connecting a plurality of display devices (100). In this case, when the tiling display device (TD) is implemented using a display device (100) with a minimized bezel as illustrated in Fig. 2a, the seam area where an image is not displayed between the display devices (100) can be minimized, thereby improving the display quality.

For example, a plurality of sub-pixels (SP) can form one pixel (PX), and the interval (D1) between the outermost pixel (PX) of one display device (100) and the outermost pixel (PX) of another adjacent display device (100) can be implemented to be the same as the interval (D1) between pixels (PX) within one display device (100). Accordingly, the interval between pixels (PX) between display devices (100) can be configured to be constant, so that the deep area can be minimized.

However, FIGS. 2A and 2B are exemplary, and the display device (100) according to one embodiment of the present specification may be a general display device having a bezel, but is not limited thereto.

Hereinafter, the display panel (PN) of the display device (100) according to one embodiment of the present specification will be described in more detail.

FIG. 3 is a cross-sectional view of a sub-pixel of a display device according to one embodiment of the present specification.

Referring to FIG. 3, a sub-pixel (SP) of a display device (100) according to one embodiment of the present specification includes a substrate (110), a gate insulating layer (111), an interlayer insulating layer (112), a first passivation layer (113), an organic insulating layer (114), a second passivation layer (115), an adhesive layer (116), a first planarization layer (117), a second planarization layer (118), a driving transistor (DT), a power wiring (PL), a first reflective electrode (RE1), a second reflective electrode (RE2), a first connection electrode (CE1), a second connection electrode (CE2), and a light-emitting element (120).

The substrate (110) is a structure for supporting various components included in the display device (100) and may be made of an insulating material. For example, the substrate (110) may be made of glass or resin, etc. In addition, the substrate (110) may be made of a polymer or plastic, or may be made of a material having flexibility.

In each of the plurality of sub-pixels (SP), a driving transistor (DT) is arranged on a substrate (110). The driving transistor (DT) includes an active layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

An active layer (ACT) is disposed on a substrate (110). The active layer (ACT) may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

A gate insulating layer (111) is disposed on the active layer (ACT). The gate insulating layer (111) is an insulating layer for insulating the active layer (ACT) and the gate electrode (GE), and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A gate electrode (GE) is disposed on the gate insulating layer (111). The gate electrode (GE) may be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

An interlayer insulating layer (112) is disposed on the gate electrode (GE). Contact holes are formed in the interlayer insulating layer (112) for connecting the source electrode (SE) and the drain electrode (DE) to the active layer (ACT), respectively. The interlayer insulating layer (112) is an insulating layer for protecting the structure below the interlayer insulating layer (112), and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A source electrode (SE) and a drain electrode (DE) electrically connected to an active layer (ACT) are disposed on an interlayer insulating layer (112). The source electrode (SE) and the drain electrode (DE) may be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

Meanwhile, although not shown in the drawing, a buffer layer may be further disposed between the substrate (110) and the driving transistor (DT) depending on the type of the substrate (110) or the type of the transistor. The buffer layer may reduce the penetration of moisture or impurities through the substrate (110). The buffer layer may be composed of, for example, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

Next, a power line (PL) is arranged on the interlayer insulating layer (112) in each of the plurality of sub-pixels (SP). The power line (PL) is electrically connected to the light-emitting element (120) together with the driving transistor (DT) to cause the light-emitting element (120) to emit light. The power line (PL) may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

A first passivation layer (113) is placed on the power wiring (PL). The first passivation layer (113) is an insulating layer for protecting the structure under the first passivation layer (113), and may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

An organic insulating layer (114) is disposed on the first passivation layer (113). The organic insulating layer (114) can planarize the upper portion of the substrate (110) on which the driving transistor (DT) is disposed. The organic insulating layer (114) may be composed of a single layer or multiple layers, and may be made of, for example, photoresist or an acrylic-based organic material, but is not limited thereto.

In each of the plurality of sub-pixels (SP), a first reflective electrode (RE1) and a second reflective electrode (RE2) spaced apart from each other are disposed on an organic insulating layer (114). The first reflective electrode (RE1) and the second reflective electrode (RE2) disposed in each of the plurality of sub-pixels (SP) can electrically connect the light-emitting element (120) to the driving transistor (DT) and the power line (PL) and at the same time function as a reflector that reflects light emitted from the light-emitting element (120). The plurality of first reflective electrodes (RE1) and the plurality of second reflective electrodes (RE2) are formed of a conductive material having excellent reflective properties, so that the light emitted from the plurality of light-emitting elements (120) can be reflected to the upper portion of the substrate (110). For example, the plurality of first reflective electrodes (RE1) and the plurality of second reflective electrodes (RE2) may be made of a metal material having excellent reflective properties, such as aluminum (Al), silver (Ag), copper (Cu), palladium (Pd), or an alloy thereof, but are not limited thereto.

The first reflective electrode (RE1) can electrically connect the light emitting element (120) to the driving transistor (DT). The first reflective electrode (RE1) can be electrically connected to either the source electrode (SE) or the drain electrode (DE) of the driving transistor (DT) through a contact hole formed in the organic insulating layer (114) and the first passivation layer (113). In addition, the first reflective electrode (RE1) can also be electrically connected to the first electrode (124) of the light emitting element (120) through the first connection electrode (CE1). Therefore, the first electrode (124) of the light emitting element (120) and the driving transistor (DT) can be electrically connected to each other through the first reflective electrode (RE1) and the first connection electrode (CE1).

The second reflective electrode (RE2) can electrically connect the power wiring (PL) and the light-emitting element (120). The second reflective electrode (RE2) can be electrically connected to the power wiring (PL) through a contact hole formed in the organic insulating layer (114) and the first passivation layer (113). In addition, the second reflective electrode (RE2) can be electrically connected to the second connection electrode (CE2) and the second electrode (126) of the light-emitting element (120) through contact holes of the second passivation layer (115), the adhesive layer (116), the first planarization layer (117), and the second planarization layer (118). Therefore, the second electrode (126) of the light-emitting element (120) and the power wiring (PL) can be electrically connected through the second reflective electrode (RE2) and the second connection electrode (CE2).

A second passivation layer (115) is disposed on a plurality of first reflective electrodes (RE1) and a plurality of second reflective electrodes (RE2). The second passivation layer (115) is an insulating layer for protecting the structure under the second passivation layer (115), and may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

An adhesive layer (116) is disposed on the second passivation layer (115). The adhesive layer (116) is formed on the entire surface of the substrate (110) and can fix the light emitting element (120) disposed on the adhesive layer (116). The adhesive layer (116) may be selected from, for example, any one of adhesive polymer, epoxy resist, UV resin, polyimide series, acrylate series, urethane series, and polydimethylsiloxane (PDMS), but is not limited thereto.

A plurality of light-emitting elements (120) are arranged on each of a plurality of sub-pixels (SP) on an adhesive layer (116). The plurality of light-emitting elements (120) are elements that emit light by current, and may include light-emitting elements (120) that emit red light, green light, blue light, etc., and a combination of these may implement light of various colors, including white. For example, the plurality of light-emitting elements (120) may be, but are not limited to, LEDs (Light Emitting Diodes) or micro LEDs.

The light-emitting element (120) includes a first semiconductor layer (121), a light-emitting layer (122), a second semiconductor layer (123), a first electrode (124), an expansion electrode (125), a second electrode (126), and a sealing film (127).

A first semiconductor layer (121) is disposed on the adhesive layer (116), and a second semiconductor layer (123) is disposed on the first semiconductor layer (121). The first semiconductor layer (121) and the second semiconductor layer (123) may be semiconductor layers doped with n-type and p-type impurities. For example, each of the first semiconductor layer (121) and the second semiconductor layer (123) may be layers doped with n-type and p-type impurities in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. The p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc., but is not limited thereto.

Meanwhile, the second semiconductor layer (123) includes a protrusion (123a) protruding outward from the first semiconductor layer (121) and the light-emitting layer (122). The protrusion (123a) of the second semiconductor layer (123) may be positioned above the expansion electrode (125). The protrusion (123a) of the second semiconductor layer (123) may be disposed on the upper surface of the expansion electrode (125). Due to the protrusion (123a), the side surface of the upper portion of the second semiconductor layer (123) may protrude more than the side surface of the lower portion. The second semiconductor layer (123) may be formed of an upper portion having a relatively wide width and a lower portion having a relatively narrow width. The side surface of the protrusion (123a) of the second semiconductor layer (123) may be disposed on the same line as the side surface of the expansion electrode (125).

A light-emitting layer (122) is disposed between a first semiconductor layer (121) and a second semiconductor layer (123). The light-emitting layer (122) can emit light by receiving holes and electrons from the first semiconductor layer (121) and the second semiconductor layer (123). The light-emitting layer (122) can be formed of a single layer or a multi-quantum well (MQW) structure, and can be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

A first electrode (124) is arranged on the lower surface of the first semiconductor layer (121). The first electrode (124) can be in contact with the lower surface of the first semiconductor layer (121). The first electrode (124) can be electrically connected to the first reflective electrode (RE1) and the driving transistor (DT) together with the expanding electrode (125). The first electrode (124) can be made of, but is not limited to, an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a combination of an opaque conductive material and a transparent conductive material.

The sealing film (127) is arranged to cover the first semiconductor layer (121), the light-emitting layer (122), the second semiconductor layer (123), and at least a portion of the first electrode (124). The sealing film (127) can cover the edge portion of the first electrode (124), the side surface and the lower surface of the first semiconductor layer (121), the side surface of the light-emitting layer (122), the side surface of the lower portion of the second semiconductor layer (123), and the lower surface of the protrusion (123a) of the second semiconductor layer (123). The sealing film (127) can function as an insulating layer to protect the light-emitting layer (122) and the second semiconductor layer (123) so that a short circuit defect does not occur when the light-emitting layer (122) and the second semiconductor layer (123) come into contact with the expansion electrode (125). The sealing film (127) may be disposed between the light-emitting layer (122) and the expansion electrode (125), between the second semiconductor layer (123) and the expansion electrode (125), and between the first semiconductor layer (121) and the expansion electrode (125). In addition, a portion of the first electrode (124) may be exposed from the sealing film (127) so that the first electrode (124) and the expansion electrode (125) may be electrically connected. The sealing film (127) may be made of any one of an insulating material, for example, an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

The enlarged electrode (125) is arranged to surround a portion of the first electrode (124), the first semiconductor layer (121), the light-emitting layer (122), and the second semiconductor layer (123) on which the sealing film (127) is formed. The enlarged electrode (125) is arranged to surround a lower portion of the first electrode (124), a side surface and a lower surface of the first semiconductor layer (121), a side surface of the light-emitting layer (122), and a lower portion of the second semiconductor layer (123). At this time, the enlarged electrode (125) may be electrically connected to the first electrode (124) by contacting a portion of the lower surface of the first electrode (124) exposed from the sealing film (127). In addition, the enlarged electrode (125) may be separated from the first semiconductor layer (121), the light-emitting layer (122), and the second semiconductor layer (123) by the sealing film (127). The side surface of the enlarged electrode (125) may be arranged on the same plane as the side surface of the protrusion (123a) of the upper portion of the second semiconductor layer (123). Accordingly, the side surface of the light-emitting element (120) may be formed of the side surface of the enlarged electrode (125) and the side surface of the second semiconductor layer (123). The enlarged electrode (125) may be formed of a conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

The enlarged electrode (125) can enlarge the contact area with the first connection electrode (CE1) so that the first connection electrode (CE1) and the light-emitting element (120) can be easily electrically connected. In addition, the enlarged electrode (125) can prevent the side surface of the light-emitting element (120) from having a reverse taper shape, thereby preventing the disconnection of the first connection electrode (CE1). The angle of the side surface of the enlarged electrode (125) formed on the side surface of the light-emitting element (120) can be vertical or acute. Accordingly, the side surface of the light-emitting element (120) can be a vertical plane or a tapered shape. In this case, the first connection electrode (CE1) surrounding the side surface of the light-emitting element (120) can be more easily fixed to the side surface of the light-emitting element (120), and disconnection can be minimized.

A second electrode (126) is arranged on the upper surface of the second semiconductor layer (123). The second electrode (126) is an electrode for electrically connecting the second connection electrode (CE2) and the second semiconductor layer (123). The second electrode (126) may be made of a transparent conductive material so that light emitted from the light-emitting layer (122) can be directed upwards of the substrate (110), i.e., upwards of the light-emitting element (120). For example, the second electrode (126) may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

A first connection electrode (CE1) is disposed on the adhesive layer (116). The first connection electrode (CE1) is an electrode for electrically connecting the light emitting element (120) and the driving transistor (DT) in each of the plurality of sub-pixels (SP). The first connection electrode (CE1) can be electrically connected to the first reflective electrode (RE1) through a contact hole formed in the adhesive layer (116) and the second passivation layer (115). Therefore, the first connection electrode (CE1) can be electrically connected to either the source electrode (SE) or the drain electrode (DE) of the driving transistor (DT) through the first reflective electrode (RE1). In addition, the first connection electrode (CE1) is disposed to surround a side surface of the light emitting element (120) and can be in contact with the expansion electrode (125) of the light emitting element (120). The first connection electrode (CE1) may be in contact with the side of the light-emitting element (120), that is, the side of the expansion electrode (125), and may be electrically connected to the expansion electrode (125). Accordingly, the expansion electrode (125) and the first electrode (124) of the light-emitting element (120) may be electrically connected to the driving transistor (DT) through the first connection electrode (CE1). The first connection electrode (CE1) may be formed of, but is not limited to, an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a combination of an opaque conductive material and a transparent conductive material.

A first planarization layer (117) is disposed on the first connection electrode (CE1) and the light-emitting element (120), and a second planarization layer (118) is disposed on the first planarization layer (117). The first planarization layer (117) and the second planarization layer (118) planarize the upper portion of the substrate (110) on which the light-emitting element (120) is disposed, and together with the adhesive layer (116), the light-emitting element (120) can be fixed on the substrate (110) while protecting the light-emitting element (120). In addition, the first planarization layer (117) and the second planarization layer (118) are disposed to surround the light-emitting element (120) including the first connection electrode (CE1) and the expansion electrode (125), so as to protect the first connection electrode (CE1) and the expansion electrode (125) and the second connection electrode (CE2) from being connected to each other. The first planarization layer (117) and the second planarization layer (118) may be composed of a single layer or multiple layers, and may be made of, for example, photoresist or an acrylic-based organic material, but are not limited thereto.

A second connection electrode (CE2) is disposed on the second planarization layer (118). The second connection electrode (CE2) is an electrode for electrically connecting the light emitting element (120) and the power wiring (PL). The second connection electrode (CE2) can be electrically connected to the second reflective electrode (RE2) through a contact hole formed in the second planarization layer (118), the first planarization layer (117), the adhesive layer (116), and the second passivation layer (115). Accordingly, the second connection electrode (CE2) can be electrically connected to the power wiring (PL) through the second reflective electrode (RE2). In addition, the second connection electrode (CE2) can be electrically connected to the second electrode (126) of the light emitting element (120) by coming into contact with the second electrode (126) exposed from the second planarization layer (118). Accordingly, the second electrode (126) of the light-emitting element (120) and the power wiring (PL) can be electrically connected to each other through the second connection electrode (CE2) and the second reflective electrode (RE2).

Meanwhile, although not shown in the drawing, a bank and a protective layer may be further disposed on the second planarization layer (118) and the second connection electrode (CE2). The bank may be disposed at a boundary between adjacent sub-pixels (SP) to reduce color mixing of light emitted from the light emitting elements (120) of each of the plurality of sub-pixels (SP). The bank may be disposed at a predetermined distance from the light emitting elements (120). The bank may cover a portion of the second connection electrode (CE2). The bank may be made of an opaque material to reduce color mixing between the plurality of sub-pixels (SP), and may be made of, for example, black resin, but is not limited thereto.

The protective layer placed on the entire surface of the substrate (110) on the bank is a layer for protecting the structure under the protective layer. The protective layer may be composed of a single layer or multiple layers, and may be made of, for example, benzocyclobutene (BCB), a light-transmitting epoxy, a photoresist, or an acrylic organic material, but is not limited thereto.

Hereinafter, a method for manufacturing a display device (100) according to one embodiment of the present specification will be described with reference to FIGS. 4a to 4i.

FIGS. 4A to 4F are process diagrams for explaining a method for manufacturing a light-emitting element of a display device according to one embodiment of the present disclosure. FIGS. 4G to 4I are process diagrams for explaining a method for manufacturing a display device according to one embodiment of the present disclosure.

Referring to Fig. 4a, an epi layer is grown on a wafer (WF), and a metal layer (ML) is formed on the entire surface of the epi layer.

First, the wafer (WF) is a substrate on which a plurality of light-emitting elements (120) are formed. For example, the wafer (WF) may be made of, but is not limited to, sapphire, silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), etc.

The epilayer is a crystal layer grown from a material such as gallium nitride (GaN) or indium gallium nitride (InGaN) that constitutes a plurality of light-emitting elements (120). The epilayer can be patterned into a plurality of pieces and electrodes can be formed to form a plurality of light-emitting elements (120). The epilayer includes an undoped semiconductor layer (UDL), a second semiconductor material layer (123m), a light-emitting material layer (122m), and a first semiconductor material layer (121m) that are sequentially formed on a wafer (WF). The epilayer can be formed through a process such as a metal organic chemical vapor deposition (MOCVD) process, molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), vapor phase epitaxy (VPE), or the like, but is not limited thereto.

The undoped semiconductor layer (UDL) may be gallium nitride (u-GaN) that is not doped with impurities. The undoped semiconductor layer (UDL) is a layer that buffers the lattice mismatch and the difference in thermal expansion coefficient between the second semiconductor material layer (123m), the light-emitting material layer (122m), and the first semiconductor material layer (121m) formed on the undoped semiconductor layer (UDL) and the wafer (WF).

A second semiconductor material layer (123m) is disposed on an undoped semiconductor layer (UDL), a light-emitting material layer (122m) is disposed on the second semiconductor material layer (123m), and a first semiconductor material layer (121m) is disposed on the light-emitting material layer (122m). The second semiconductor material layer (123m), the light-emitting material layer (122m), and the first semiconductor material layer (121m) are layers that form the second semiconductor layer (123), the light-emitting layer (122), and the first semiconductor layer (121) of the light-emitting element (120), respectively. In a subsequent process, the second semiconductor material layer (123m), the light-emitting material layer (122m), and the first semiconductor material layer (121m) may be patterned into multiple pieces to form a plurality of light-emitting elements (120) including the second semiconductor layer (123), the light-emitting layer (122), and the first semiconductor layer (121).

A metal layer (ML) is formed over the entire upper surface of the first semiconductor material layer (121m). The metal layer (ML) is a layer for forming a first electrode (124), and the first electrode (124) can be formed by patterning the metal layer (ML). The first electrode (124) may be formed of, for example, an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a combination of an opaque conductive material and a transparent conductive material, but is not limited thereto.

Referring to FIGS. 4b and 4c, the epi layer and the metal layer (ML) are mesa-etched to form a first semiconductor layer (121), a light-emitting layer (122), and a first electrode (124). The metal layer (ML) can be etched to form the first electrode (124). In addition, the first semiconductor material layer (121m) and the light-emitting material layer (122m) can be etched to form the first semiconductor layer (121) and the light-emitting layer (122).

At this time, the planar shape of the first semiconductor layer (121) and the light-emitting layer (122) can be formed into various shapes. For example, as illustrated in FIG. 4c, the planar shape of the first semiconductor layer (121) and the light-emitting layer (122) can be formed into a circle or a square. In addition, the planar shape of the first semiconductor layer (121) and the light-emitting layer (122) can be formed into an elliptical or polygonal shape, but is not limited thereto.

Meanwhile, the second semiconductor material layer (123m) may be partially etched. Only the upper portion of the second semiconductor material layer (123m) adjacent to the light-emitting layer (122) may be partially etched, and the lower portion of the second semiconductor material layer (123m) adjacent to the undoped semiconductor layer (UDL) may remain unetched. The second semiconductor material layer (123m') of which the upper portion is partially etched may be processed into a protrusion (123a) of the second semiconductor layer (123) in a subsequent process.

Next, referring to FIGS. 4b and 4d, a sealing film (127) and an expansion electrode (125) are formed on the first electrode (124), the first semiconductor layer (121), and the light-emitting layer (122) of the light-emitting element (120) and the partially etched second semiconductor material layer (123m') of the epi layer.

First, an insulating layer (IL) can be formed on the entire surface of the wafer (WF). The insulating layer (IL) can cover the partially etched second semiconductor material layer (123m'), the light-emitting layer (122), the first semiconductor layer (121), and the first electrode (124). In addition, a contact hole exposing the first electrode (124) can be formed in the insulating layer (IL). The insulating layer (IL) covering the first electrode (124) is partially opened so that the first electrode (124) can be electrically connected to an expansion electrode (125) to be formed later.

Next, an enlarged electrode (125) is formed on the insulating layer (IL). A conductive material forming the enlarged electrode (125) can be formed on the entire surface of the wafer (WF) and etched to form the enlarged electrode (125). The enlarged electrode (125) can be arranged to surround the side surfaces of the upper portion of the first electrode (124), the first semiconductor layer (121), the light-emitting layer (122), and the partially etched second semiconductor material layer (123m'). In addition, the enlarged electrode (125) can cover the upper surface of the lower portion of the partially etched second semiconductor material layer (123m'). At this time, since an insulating layer (IL) is arranged between the enlarged electrode (125) and the light-emitting layer (122) and between the enlarged electrode (125) and the partially etched second semiconductor material layer (123m'), a short circuit defect caused by the enlarged electrode (125) can be prevented.

Next, the insulating layer (IL), the partially etched second semiconductor material layer (123m'), and the undoped semiconductor layer (UDL) are etched to form a sealing film (127), a second semiconductor layer (123), and an undoped semiconductor pattern (UDL'). By performing an isolation process of etching the insulating layer (IL), the partially etched second semiconductor material layer (123m'), and the undoped semiconductor layer (UDL) using the expansion electrode (125) as a mask, a light-emitting element (120) including the sealing film (127) and the second semiconductor layer (123), and an undoped semiconductor pattern (UDL') that partially remains only under the light-emitting element (120) can be formed. A portion of the insulating layer (IL) overlapping the enlarged electrode (125), a portion of the partially etched second semiconductor material layer (123m'), and a portion of the undoped semiconductor layer (UDL) are left, and the remaining portion of the insulating layer (IL) not overlapping the enlarged electrode (125), the remaining portion of the partially etched second semiconductor material layer (123m'), and the remaining portion of the undoped semiconductor layer (UDL) can be etched and removed. Accordingly, the sealing film (127) and the second semiconductor layer (123) formed using the enlarged electrode (125) as a mask can be arranged so that their side surfaces are on the same plane as the side surfaces of the enlarged electrode (125). At this time, the undoped semiconductor pattern (UDL') remaining between the second semiconductor layer (123) and the wafer (WF) can be removed in a subsequent process.

Next, referring to FIG. 4e, an organic film (OL) is formed on the entire surface of a wafer (WF), and a plurality of light-emitting elements (120) are transferred from the wafer (WF) to a first temporary substrate (TS1).

First, before separating the plurality of light-emitting elements (120) from the wafer (WF), an organic film (OL) can be formed on the entire surface of the wafer (WF). The organic film (OL) can be arranged to cover the plurality of light-emitting elements (120). The organic film (OL) surrounding the plurality of light-emitting elements (120) can fix and protect the plurality of light-emitting elements (120) separated from the wafer (WF) in a subsequent process. The organic film (OL) can be made of a viscous material, for example, benzocyclobutene (BCB), but is not limited thereto.

Next, a plurality of light-emitting elements (120) can be separated from the wafer (WF) while the first temporary substrate (TS1) is bonded on top of the wafer (WF) on which the organic film (OL) is applied. For example, the plurality of light-emitting elements (120) can be separated from the wafer (WF) through a laser lift-off (LLO) process in which a laser is irradiated onto the back side of the wafer (WF).

Referring to FIG. 4f, the undoped semiconductor pattern (UDL') is removed, the second electrode (126) is formed, and a portion of the organic film (OL) is removed.

A plurality of light emitting elements (120) transferred to a first temporary substrate (TS1) may have an undoped semiconductor pattern (UDL') positioned on the upper side, and an expansion electrode (125) and a first electrode (124) positioned on the lower side. When a plurality of light emitting elements (120) are transferred to the first temporary substrate (TS1), the undoped semiconductor pattern (UDL') may be exposed to the outside, and the undoped semiconductor pattern (UDL') may be removed by etching.

Next, the undoped semiconductor pattern (UDL') is removed, and a second electrode (126) is formed on the upper surface of the second semiconductor layer (123) exposed to the outside. By forming the second electrode (126) on the upper surface of the second semiconductor layer (123), the manufacturing process of a plurality of light-emitting elements (120) including the first semiconductor layer (121), the light-emitting layer (122), the second semiconductor layer (123), the first electrode (124), the expansion electrode (125), the second electrode (126), and the sealing film (127) can be completed.

Next, a portion of the organic film (OL) covering the side surfaces of the plurality of light-emitting elements (120) may be removed to form an organic film pattern (OL'). The remaining organic film (OL) except for a portion of the organic film (OL) positioned between the plurality of light-emitting elements (120) and the first temporary substrate (TS1) may be removed. A portion of the organic film (OL) overlapping the plurality of light-emitting elements (120) may remain to form the organic film pattern (OL'), and the remaining portion of the organic film (OL) not overlapping the plurality of light-emitting elements (120) may be removed. For example, the organic film (OL) may be removed through an ashing process using a vacuum plasma process. Accordingly, the side surfaces of the plurality of light-emitting elements (120), particularly, the side surfaces of the expansion electrodes (125), may be exposed to the outside from the organic film (OL). The expansion electrodes (125) may be exposed from the organic film (OL) and may be easily electrically connected to the first connection electrodes (CE1) formed in the display panel (PN) later.

Next, referring to FIG. 4g, a plurality of light-emitting elements (120) are transferred from a first temporary substrate (TS1) to a second temporary substrate (TS2). The second temporary substrate (TS2) is placed on top of the plurality of light-emitting elements (120), and the plurality of light-emitting elements (120) can be transferred from the first temporary substrate (TS1) to the second temporary substrate (TS2). By transferring the plurality of light-emitting elements (120) from the first temporary substrate (TS1) to the second temporary substrate (TS2), the directions of the plurality of light-emitting elements (120) can be aligned so that the first electrode (124) and the expansion electrode (125) of the light-emitting elements (120) are attached to the adhesive layer (116) of the display panel (PN).

At this time, an organic film pattern (OL') may exist as a residual film on the upper portion of the plurality of light-emitting elements (120) transferred to the second temporary substrate (TS2). The organic film pattern (OL') may or may not be removed depending on the design. For example, when transferring the plurality of light-emitting elements (120) to the second temporary substrate (TS2), the organic film pattern (OL') may be arranged at the top, and the organic film pattern (OL') may be removed through an ashing process. As another example, the plurality of light-emitting elements (120) on which the organic film pattern (OL') is formed may be transferred as is to the display panel (PN). When the organic film pattern (OL') is not removed and is transferred to the display panel (PN) together with the light-emitting elements (120), the organic film pattern (OL') may be arranged between the light-emitting elements (120) and the adhesive layer (116).

In the following description, it is assumed that the organic film pattern (OL') is removed through an ashing process, but the present invention is not limited thereto.

Next, referring to FIG. 4h, a plurality of light-emitting elements (120) are transferred from a second temporary substrate (TS2) onto an adhesive layer (116) of a display panel (PN). The display panel (PN) may be formed with a driving transistor (DT), a power line (PL), a first reflective electrode (RE1), a second reflective electrode (RE2), a gate insulating layer (111), an interlayer insulating layer (112), a first passivation layer (113), an organic insulating layer (114), a second passivation layer (115), and an adhesive layer (116). Then, the plurality of light-emitting elements (120) may be transferred onto the adhesive layer (116). The plurality of light-emitting elements (120) may be separated from the second temporary substrate (TS2) and transferred to the display panel (PN) while the adhesive layer (116) of the display panel (PN) and the plurality of light-emitting elements (120) of the second temporary substrate (TS2) are arranged to face each other. A plurality of light-emitting elements (120) transferred onto the adhesive layer (116) can have an expansion electrode (125) in contact with the adhesive layer (116).

Next, referring to FIG. 4i, a first connection electrode (CE1), a first planarization layer (117), a second planarization layer (118), and a second connection electrode (CE2) are formed.

A first connection electrode (CE1) surrounding the side surfaces of a plurality of light-emitting elements (120) can be formed on the adhesive layer (116). The first connection electrode (CE1) can be formed by forming a conductive material on the adhesive layer (116) and the light-emitting element (120), and removing the conductive material covering the upper portion of the light-emitting element (120), that is, the second electrode (126) and the second semiconductor layer (123). The first connection electrode (CE1) can be in contact with the side surface of the lower portion of the light-emitting element (120), that is, the side surface of the expansion electrode (125). In addition, the first connection electrode (CE1) can be electrically connected to the first reflective electrode (RE1) through the contact hole of the adhesive layer (116) and the second passivation layer (115).

Next, a first planarization layer (117) can be formed on the adhesive layer (116), the first connection electrode (CE1), and the light-emitting element (120), and a second planarization layer (118) can be formed on the first planarization layer (117). By forming the first planarization layer (117) and the second planarization layer (118) on the entire surface of the substrate (110), a plurality of light-emitting elements (120) can be fixed and protected. In addition, by forming the first planarization layer (117) and the second planarization layer (118) on the entire surface of the substrate (110), the first connection electrode (CE1) can be protected from a short circuit defect by coming into contact with the second connection electrode (CE2) formed later.

Next, a second connection electrode (CE2) can be formed on the second planarization layer (118). The second connection electrode (CE2) can be in contact with the second electrode (126) exposed from the second planarization layer (118). The second connection electrode (CE2) can be electrically connected to the second reflective electrode (RE2) through a contact hole of the second planarization layer (118), the first planarization layer (117), the adhesive layer (116), and the second passivation layer (115).

Accordingly, the manufacturing process of the display device (100) can be completed by transferring the light emitting element (120) onto the adhesive layer (116) and sequentially forming the first connection electrode (CE1), the first planarization layer (117), the second planarization layer (118), and the second connection electrode (CE2).

Accordingly, in the display device (100) according to one embodiment of the present specification, an enlarged electrode (125) is formed on the light-emitting element (120), so that the light-emitting element (120) and the first connection electrode (CE1) can be electrically connected more easily. By forming the enlarged electrode (125) on the lower side of the light-emitting element (120), a contact area between the enlarged electrode (125) and the first connection electrode (CE1) can be secured. Accordingly, the first connection electrode (CE1) of the light-emitting element (120) and the enlarged electrode (125) can be electrically connected easily.

In a display device (100) according to one embodiment of the present specification, the enlarged electrode (125) is formed only to an area below the protrusion (123a) of the second semiconductor layer (123), thereby preventing a defect in which the second connection electrode (CE2) and the enlarged electrode (125) are connected. The protrusion (123a) of the second semiconductor layer (123) may cover the upper surface of the enlarged electrode (125). In this case, even if the contact hole formation position of the second planarization layer (118) is misaligned with the light emitting element (120), a defect in which the second connection electrode (CE2) is connected to the enlarged electrode (125) through the contact hole can be prevented. Therefore, a short circuit defect between the enlarged electrode (125) and the second connection electrode (CE2) can be prevented by forming the enlarged electrode (125) so that at least a portion thereof does not protrude beyond the second semiconductor layer (123).

In a display device (100) according to one embodiment of the present specification, a widening electrode (125) covering a side surface of a first semiconductor layer (121) having a reverse tapered shape can be formed to prevent a short circuit of the first connection electrode (CE1). Since the widening electrode (125) is arranged to surround the first semiconductor layer (121) and the light-emitting layer (122) and a portion of the second semiconductor layer (123) having a side surface of a reverse tapered shape, the widening electrode (125) can be arranged on the outer surface of the light-emitting element (120). At this time, the side surface of the widening electrode (125) can be formed in a vertical plane or a tapered shape. If the side surface of the light-emitting element (120) that contacts the first connection electrode (CE1) is formed in a reverse tapered shape, it may be difficult to deposit the first connection electrode (CE1) on the side surface of the light-emitting element (120), and the first connection electrode (CE1) may be short circuited. Accordingly, the side of the light-emitting element (120) in contact with the first connection electrode (CE1) can be configured with a vertical or tapered expanded electrode (125) instead of a first semiconductor layer (121) in a reverse tapered shape, thereby preventing the disconnection of the first connection electrode (CE1).

Fig. 5 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present specification. The display device (500) of Fig. 5 is substantially the same as the display device (100) of Fig. 3 except that the light-emitting element (520) further includes a pattern layer (528), and therefore, a duplicate description thereof will be omitted.

Referring to FIG. 5, the light-emitting element (520) further includes a pattern layer (528) disposed on the upper surface of the second semiconductor layer (123). The pattern layer (528) and the second electrode (126) may be disposed together on the upper surface of the second semiconductor layer (123). The pattern layer (528) may have a rough structure and may provide a rough surface on the upper surface of the light-emitting element (520) from which light emitted from the light-emitting layer (122) is extracted. The rough structure of the pattern layer (528) may have various shapes, such as a sawtooth shape, a triangular wave shape, a square wave shape, a sinusoidal wave shape, or an irregular shape. In addition, the rough structure of the pattern layer (528) may be formed of roughnesses of various heights, but is not limited thereto.

The pattern layer (528) with a rough structure can extract light totally reflected inside the light emitting element (520) to the outside of the light emitting element (520). Therefore, the pattern layer (528) with a rough structure is formed on the upper surface of the light emitting element (520) where light emitted from the light emitting layer (122) is extracted, so that the light extraction efficiency of the light emitting element (520) can be improved.

The pattern layer (528) may be formed from an undoped semiconductor layer (UDL) formed on a wafer (WF) during the manufacture of the light emitting element (520). As described with reference to FIG. 4F, when the light emitting element (520) is transferred from the wafer (WF) to the first temporary substrate (TS1), the undoped semiconductor pattern (UDL') may be positioned at the top. At this time, instead of completely removing the undoped semiconductor pattern (UDL'), the undoped semiconductor pattern (UDL') may be partially etched to form a pattern layer (528) having a rough structure. The surface of the undoped semiconductor pattern (UDL') may be irregularly etched to form the pattern layer (528).

In addition, since the pattern layer (528) is formed using an undoped semiconductor pattern (UDL'), there is no need to use a pattern wafer. Specifically, the pattern wafer is a wafer having a pattern formed on the surface, and may be, for example, a patterned sapphire substrate (PSS). The epi layer grown on the surface of the pattern wafer may have a rough structure corresponding to the pattern. However, more energy may be required in the LLO process for separating a plurality of light-emitting elements (520) from the surface of the pattern wafer. Since the contact area between the pattern wafer and the light-emitting elements (520) is larger than the contact area between the non-patterned wafer (WF) and the light-emitting elements (520), more energy is required to separate the pattern wafer and the light-emitting elements (520) than the energy required to separate the non-patterned wafer (WF) and the light-emitting elements (520).

Accordingly, in a display device (500) according to another embodiment of the present specification, a light emitting element (520) may be transferred to a first temporary substrate (TS1) to position an undoped semiconductor pattern (UDL') at the top, and the undoped semiconductor pattern (UDL') may be irregularly etched to form a pattern layer (528) having a rough structure. Therefore, a wafer (WF) without a pattern may be used, and the wafer (WF) and the light emitting element (520) may be easily separated with relatively low energy.

In addition, in a display device (500) according to another embodiment of the present specification, a pattern layer (528) is formed on the light extraction surface of the light emitting element (520), so that light that is not extracted due to total reflection inside the light emitting element (520) can be extracted to the outside of the light emitting element (520), thereby improving the efficiency of the light emitting element (520). Accordingly, the brightness of the display device (500) can be improved, and low-power operation can be enabled.

Fig. 6 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present specification. The display device (600) of Fig. 6 is substantially the same as the display device (500) of Fig. 5 except that the light-emitting element (620) further includes a reflective layer (629), and therefore, a duplicate description thereof will be omitted.

Referring to FIG. 6, the light-emitting element (620) further includes a reflective layer (629) disposed between the sealing film (127) and the expanding electrode (125). The reflective layer (629) is disposed between the sealing film (127) and the expanding electrode (125) to cover the lower surface of the protrusion (123a) of the second semiconductor layer (123), the side surface of the lower portion of the second semiconductor layer (123), the side surface of the light-emitting layer (122), and the side surface and the lower surface of the first semiconductor layer (121). The reflective layer (629) can reflect light emitted from the light-emitting layer (122) toward the lower portion of the light-emitting element (620) toward the upper portion of the light-emitting element (620). Therefore, some of the light directed toward the lower portion of the light-emitting element (620) can be emitted to the outside of the display device (600) by the reflective layer (629), and the light extraction efficiency of the light-emitting element (620) can be improved.

The reflective layer (629) can be formed before forming the expansion electrode (125). Specifically, as described in FIG. 4b, an insulating layer (IL) is formed on the first electrode (124), the first semiconductor layer (121), the light-emitting layer (122), and the partially etched second semiconductor material layer (123m'), and in a subsequent process, the insulating layer (IL) can be etched to form a sealing film (127). At this time, when forming the insulating layer (IL), the material forming the reflective layer (629) can be formed together on the insulating layer (IL). Subsequently, the material forming the reflective layer (629) and the insulating layer (IL) can be partially etched to expose the first electrode (124) to the outside. And as described in FIG. 4d, an expansion electrode (125) is formed on the material forming the reflective layer (629) and the insulating layer (IL), and the material forming the reflective layer (629) and the insulating layer (IL) are etched together using the expansion electrode (125) as a mask to form the reflective layer (629) and the sealing film (127) together.

Accordingly, in a display device (600) according to another embodiment of the present specification, a reflective layer (629) is formed between the sealing film (127) of the light-emitting element (620) and the expansion electrode (125), so that light directed toward the lower portion of the light-emitting element (620) can be reflected toward the upper portion of the light-emitting element (620). Therefore, some of the light that is not extracted to the outside of the display device (600) can be extracted to the outside of the display device (600) by the reflective layer (629), and the brightness of the display device (600) can be improved.

Fig. 7 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present specification. The display device (700) of Fig. 7 is substantially the same as the display device (600) of Fig. 6 except that the second semiconductor layer (723) of the light-emitting element (720) is different, and therefore, a duplicate description thereof will be omitted.

Referring to FIG. 7, the second semiconductor layer (723) of the light-emitting element (720) may not include a protrusion (123a). The entire side surface of the second semiconductor layer (723) may be disposed on the same plane as the side surface of the light-emitting layer (122) and the side surface of the first semiconductor layer (121). In this case, as in the processes of FIGS. 4E and 4F, when the undoped semiconductor pattern (UDL') is removed, the protrusion (123a) of the second semiconductor layer (723) may also be etched together. That is, the protrusion (123a) of the second semiconductor layer (723) may be removed by etching a portion of the second semiconductor layer (723) that protrudes outward from the light-emitting layer (122) and the first semiconductor layer (121) and is disposed on the upper surface of the expansion electrode (125).

As the protrusion (123a) of the second semiconductor layer (723) is removed, the side surface of the enlarged electrode (125) and the side surface of the second semiconductor layer (723) can be arranged on different planes. The side surface of the enlarged electrode (125) can be arranged further outward than the side surface of the second semiconductor layer (723). The enlarged electrode (125) can include a portion that protrudes outward from the second semiconductor layer (723).

Meanwhile, a sealing film (127) may be placed on the upper surface of the protruding portion of the enlarged electrode (125). Accordingly, even if the contact hole of the second planarization layer (118) and the position of the light-emitting element (720) are misaligned and the upper surface of the enlarged electrode (125) overlaps the contact hole, a short circuit defect between the enlarged electrode (125) and the second connection electrode (CE2) can be prevented by the sealing film (127) covering the upper surface of the enlarged electrode (125).

Accordingly, in the display device (700) according to another embodiment of the present specification, the second semiconductor layer (723) is disposed on the inner side of the enlarged electrode (125), so that a short circuit defect in which the first connection electrode (CE1) comes into contact with the second semiconductor layer (723) can be prevented. When the side surfaces of the enlarged electrode (125) and the second semiconductor layer (723) are disposed on the same plane, a defect in which the first connection electrode (CE1) in contact with the side surface of the enlarged electrode (125) also comes into contact with the side surface of the second semiconductor layer (723) is likely to occur, and thus a short circuit defect between the enlarged electrode (125) and the second semiconductor layer (723) may occur. Therefore, the protrusion (123a) of the second semiconductor layer (723) disposed on the protruding portion of the enlarged electrode (125) can be removed so that the side surface of the second semiconductor layer (723) is disposed inside the side surface of the enlarged electrode (125). Accordingly, by arranging the side surface of the second semiconductor layer (723) on a different plane from the side surface of the expansion electrode (125), it is possible to minimize the defect of the first connection electrode (CE1) coming into contact with the side surface of the second semiconductor layer (723).

Fig. 8 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present specification. The display device (800) of Fig. 8 is substantially the same as the display device (600) of Fig. 6 except for a different contact hole of the second planarization layer (818), and therefore, a duplicate description thereof will be omitted.

Referring to FIG. 8, the second planarization layer (818) includes a plurality of contact holes overlapping one light-emitting element (620). A plurality of contact holes are formed on one light-emitting element (620), and the light-emitting element (620) and the second connection electrode (CE2) can be connected to each other through at least one of the plurality of contact holes. For example, the second electrode (126) may be exposed through some of the plurality of contact holes, and the upper surface of the second semiconductor layer (123) may be exposed through other contact holes. At this time, the pattern layer (528) of the light-emitting element (620) may be patterned together when the contact holes of the second planarization layer (818) are formed, so that the upper surface of the second semiconductor layer (123) may be exposed through the contact holes. Accordingly, the second connection electrode (CE2) can be in contact with the second electrode (126) and the second semiconductor layer (123) of the light-emitting element (620).

At this time, since the upper surface of the enlarged electrode (125) is positioned below the protrusion (123a) of the second semiconductor layer (123), only the second semiconductor layer (123) and the second electrode (126) can be exposed in the plurality of contact holes. Since the protrusion (123a) of the second semiconductor layer (123) is positioned on the enlarged electrode (125), the enlarged electrode (125) cannot be exposed in the plurality of contact holes, and a defect in the connection between the enlarged electrode (125) and the second connection electrode (CE2) can be prevented.

Meanwhile, since the enlarged electrode (125) is formed on the lower portion of the partially etched second semiconductor material layer (123m') as described with reference to FIGS. 4b and 4d, the enlarged electrode (125) can be placed in the region between the lower surface of the protrusion (123a) of the second semiconductor layer (123) and the adhesive layer (116). That is, by forming the enlarged electrode (125) before etching the lower portion of the second semiconductor material layer (123m'), a structure can be formed in which the protrusion (123a) formed from the lower portion of the second semiconductor material layer (123m') covers the upper surface of the enlarged electrode (125).

However, in the process of FIG. 4b, if the expansion electrode (125) is formed while the lower portion of the second semiconductor material layer (123m') that is partially etched together with the first semiconductor material layer (121m) and the light-emitting material layer (122m) is etched entirely, the expansion electrode (125) can be formed to cover both the upper portion side surface and the lower portion side surface of the second semiconductor layer (123). Specifically, if the first semiconductor material layer (121m), the light-emitting material layer (122m), and the second semiconductor material layer (123m) are entirely etched to form the first semiconductor layer (121), the light-emitting layer (122), and the second semiconductor layer (123) in a trapezoidal shape, the side surfaces of the first semiconductor layer (121), the light-emitting layer (122), and the second semiconductor layer (123) can all be arranged on the same plane. And the enlarged electrode (125) formed in the subsequent process can be formed to cover both the side surface of the upper portion and the side surface of the lower portion of the second semiconductor layer (123). In this case, the light emitting element (620) can be arranged so that the edge of the enlarged electrode (125) is flush with the upper surface of the second semiconductor layer (123), and the edge of the enlarged electrode (125) may be exposed in at least some of the contact holes of the second planarization layer (818). And a short circuit defect may occur in which the second connection electrode (CE2) and the enlarged electrode (125) are connected to each other in the contact hole where the enlarged electrode (125) is exposed.

Accordingly, in a display device (800) according to another embodiment of the present specification, the protrusion (123a) of the second semiconductor layer (123) is arranged to cover the upper surface of the enlarged electrode (125), thereby preventing a defect in which the enlarged electrode (125) and the second connection electrode (CE2) are connected in at least some of the contact holes among the plurality of contact holes.

In addition, in a display device (800) according to another embodiment of the present specification, a plurality of contact holes are formed in the second planarization layer (818), so that the light emitting elements (620) and the second connection electrode (CE2) can be more easily electrically connected. The plurality of light emitting elements (620) can be transferred from the wafer (WF) to the display panel (PN) via the first temporary substrate (TS1) and the second temporary substrate (TS2). However, during the transfer process, an alignment error of the plurality of light emitting elements (620) may occur, so that the positions of the light emitting elements (620) transferred to the display panel (PN) may be misaligned. However, even if an alignment error of the plurality of light emitting elements (620) occurs, the second semiconductor layer (123) and the second electrode (126) of the light emitting elements (620) can be easily exposed in at least some of the contact holes formed in the second planarization layer (818). Accordingly, even if an alignment error occurs, the second connection electrode (CE2) and the light-emitting element (620) can be electrically connected, and defects in the sub-pixel (SP) can be minimized.

A display device according to various embodiments of the present specification may be described as follows.

A display device according to one embodiment of the present specification includes a substrate on which a plurality of sub-pixels are defined, a light-emitting element disposed in each of the plurality of sub-pixels, and a first connection electrode in contact with a side surface of the light-emitting element, wherein the light-emitting element includes a first semiconductor layer on the substrate, a light-emitting layer on the first semiconductor layer, a second semiconductor layer on the light-emitting layer, a first electrode on a lower surface of the first semiconductor layer, a second electrode on an upper surface of the second semiconductor layer, an expansion electrode surrounding the first electrode, the side surface and the lower surface of the first semiconductor layer, the side surface of the light-emitting layer, and a portion of the side surface of the second semiconductor layer, and a sealing film disposed between the expansion electrode and the first semiconductor layer, between the expansion electrode and the light-emitting layer, and between the expansion electrode and the second semiconductor layer, wherein the first connection electrode is in contact with a side surface of the expansion electrode.

According to another feature of the present specification, the enlarged electrode can contact a portion of the first electrode exposed from the sealing film.

According to another feature of the present specification, the second semiconductor layer may include a protrusion that protrudes outwardly from the light-emitting layer and the first semiconductor layer and covers the upper surface of the expansion electrode.

According to another feature of the present specification, the side surface of the protrusion can be arranged on the same plane as the side surface of the enlarged electrode.

According to another feature of the present specification, the side surface of the second semiconductor layer may be arranged inward relative to the side surface of the expansion electrode.

According to another feature of the present specification, the enlarged electrode includes a portion protruding outwardly from the second semiconductor layer, and the sealing film can cover the upper surface of the protruding portion of the enlarged electrode.

According to another feature of the present specification, the side surface of the first semiconductor layer may have a reverse taper shape, and the side surface of the expansion electrode may have a vertical plane or a tapered shape.

According to another feature of the present specification, the light emitting element may further include a reflective layer disposed between the sealing film and the expansion electrode.

According to another feature of the present specification, the light-emitting element may further include a patterned layer having a rough structure, the patterned layer being disposed on an upper surface of the second semiconductor layer.

According to another feature of the present specification, the second semiconductor layer may be a semiconductor layer doped with impurities, and the pattern layer may be a semiconductor layer not doped with impurities.

According to another feature of the present specification, the device may further include a first planarization layer disposed on the first connecting electrode and the light-emitting element, a second planarization layer disposed on the first planarization layer, and a second connecting electrode disposed on the second planarization layer and electrically connected to the second electrode through a contact hole of the second planarization layer.

According to another feature of the present specification, a plurality of contact holes of the second planarization layer may be arranged on one light-emitting element.

According to another feature of the present specification, the second electrode and the second connection electrode may be in contact with each other in some of the plurality of contact holes, and the upper surface of the second semiconductor layer and the second connection electrode may be in contact with each other in some of the other contact holes.

According to another feature of the present specification, the device further comprises an adhesive layer disposed between the first connecting electrode and the substrate, and between the light-emitting element and the substrate, wherein the expansion electrode can be in contact with the upper surface of the adhesive layer.

Although the embodiments of the present specification have been described in more detail with reference to the attached drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be implemented without departing from the technical spirit of the present specification. Accordingly, the embodiments disclosed in this specification are not intended to limit the technical spirit of the present specification, but rather to explain it, and the scope of the technical spirit of the present specification is not limited by these embodiments. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

TD: Tiling Display Device
GD: Gate driver
DD: Data Drive
TC: Timing Controller
PN: Display Panel
AA: Display Area
NA: Non-displayed area
PX: Pixel
SP: Sub-pixel
PAD1: First pad electrode
PAD2: Second pad electrode
SRL: Side wiring
100, 500, 600, 700, 800: Display devices
110: Substrate
111: Gate insulation layer
112: Interlayer insulation layer
113: First passivation layer
114: Organic insulating layer
115: Second passivation layer
116: Adhesive layer
117: First leveling layer
118, 818: Second leveling layer
DT: driving transistor
ACT: Active layer
GE: Gate electrode
SE: source electrode
DE: drain electrode
PL: Power wiring
RE1: First reflector electrode
RE2: Second reflector electrode
CE1: First connecting electrode
CE2: Second connecting electrode
120, 520, 620, 720: Light-emitting elements
121: First semiconductor layer
122: Emissive layer
123, 723: Second semiconductor layer
123a: Protrusion
124: First electrode
125: Magnifying electrode
126: Second electrode
127: Closing
528: Pattern layer
629: Reflective layer
WF: Wafer
TS1: First Temporary Board
TS2: Second Temporary Board
UDL: Undoped semiconductor layer
UDL: Undoped Semiconductor Pattern
121m: First semiconductor material layer
122m: luminescent material layer
123m, 123m': Second semiconductor material layer
ML: Metal layer
IL: Insulating layer
OL: Organic membrane
OL': Organic film pattern

Claims (14)

A substrate having multiple sub-pixels defined;
A light emitting element arranged in each of the plurality of sub-pixels; and
including a first connecting electrode in contact with the side surface of the light-emitting element;
The above light emitting element,
A first semiconductor layer on the substrate;
A light-emitting layer on the first semiconductor layer;
A second semiconductor layer on the above light-emitting layer;
A first electrode on the lower surface of the first semiconductor layer;
A second electrode on the upper surface of the second semiconductor layer;
An enlarged electrode surrounding the first electrode, the side surface and the lower surface of the first semiconductor layer, the side surface of the light-emitting layer, and a portion of the side surface of the second semiconductor layer; and
It includes a sealing film disposed between the expansion electrode and the first semiconductor layer, between the expansion electrode and the light-emitting layer, and between the expansion electrode and the second semiconductor layer,
A display device wherein the first connecting electrode is in contact with a side surface of the enlarged electrode. In the first paragraph,
A display device in which the above-mentioned enlarged electrode is in contact with a portion of the first electrode exposed from the sealing film. In the first paragraph,
A display device, wherein the second semiconductor layer includes a protrusion that protrudes outward from the light-emitting layer and the first semiconductor layer and covers the upper surface of the expansion electrode. In the third paragraph,
A display device in which the side surface of the above protrusion is arranged on the same plane as the side surface of the above enlarged electrode. In the first paragraph,
A display device, wherein the side surface of the second semiconductor layer is positioned closer to the side surface of the expansion electrode. In paragraph 5,
The above enlarged electrode includes a portion protruding outward from the second semiconductor layer,
A display device in which the above-mentioned sealing film covers the upper surface of the protruding portion of the above-mentioned enlarged electrode. In the first paragraph,
A display device, wherein the side surface of the first semiconductor layer has a reverse taper shape, and the side surface of the enlarged electrode has a vertical plane or a taper shape. In the first paragraph,
A display device, wherein the light-emitting element further includes a reflective layer disposed between the sealing film and the expansion electrode. In the first paragraph,
A display device, wherein the light-emitting element further includes a pattern layer having a rough structure and disposed on the upper surface of the second semiconductor layer. In paragraph 9,
A display device, wherein the second semiconductor layer is a semiconductor layer doped with impurities, and the pattern layer is a semiconductor layer not doped with impurities. In the first paragraph,
A first planarizing layer disposed on the first connecting electrode and the light emitting element;
a second planarization layer disposed on the first planarization layer; and
A display device further comprising a second connecting electrode disposed on the second planarization layer and electrically connected to the second electrode through a contact hole of the second planarization layer. In Article 11,
A display device in which a plurality of contact holes of the second planarization layer are arranged on one of the light-emitting elements. In paragraph 12,
A display device in which the second electrode and the second connection electrode are in contact with each other in some of the plurality of contact holes, and the upper surface of the second semiconductor layer and the second connection electrode are in contact with each other in some of the other contact holes. In the first paragraph,
Further comprising an adhesive layer disposed between the first connecting electrode and the substrate, and between the light emitting element and the substrate,
A display device in which the above-mentioned enlarged electrode is in contact with the upper surface of the adhesive layer.