Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
Baikady et al., 2021 - Google Patents
[go: Go Back, main page]

Baikady et al., 2021 - Google Patents

Area and Power Efficient Architecture for Direct Digital Frequency Synthesizer

Baikady et al., 2021

Document ID
1292438716483204740
Author
Baikady A
Uma B
Publication year
Publication venue
2021 10th International Conference on Internet of Everything, Microwave Engineering, Communication and Networks (IEMECON)

External Links

Snippet

Direct Digital Frequency Synthesis (DDFS) is a technique of creating analogue waveform by digitally modifying a fixed system clock and then processing the output through a DAC (Digital-to-Analog Converter). This enables for fine frequency resolution throughout a wide …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806—Computations with complex numbers
    • G06F7/4818—Computations with complex numbers using coordinate rotation digital computer [CORDIC]
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain
    • H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain by continuously permuting the elements used, i.e. dynamic element matching
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same information or similar information or a subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/02—Digital function generators

Similar Documents

Publication Publication Date Title
Yoo et al. A 2 GHz 130 mW direct-digital frequency synthesizer with a nonlinear DAC in 55 nm CMOS
Chren One-hot residue coding for low delay-power product CMOS design
De Caro et al. Direct digital frequency synthesizers with polynomial hyperfolding technique
De Caro et al. Direct digital frequency synthesizer using nonuniform piecewise-linear approximation
Baikady et al. Area and Power Efficient Architecture for Direct Digital Frequency Synthesizer
Yang et al. A 2.2-GHz configurable direct digital frequency synthesizer based on LUT and rotation
Kesoulis et al. Systematic methodology for designing low power direct digital frequency synthesisers
Al-Khaleel et al. Fast and compact binary-to-BCD conversion circuits for decimal multiplication
Chen et al. Implementation method of CORDIC algorithm to improve DDFS performance
CN102006066B (en) ROM-less DDS circuit structure
Bergeron et al. A 1-GHz direct digital frequency synthesizer in an FPGA
Alkurwy et al. A low power memoryless ROM design architecture for a direct digital frequency synthesizer
Ibrahim et al. Hardware Implementation of 32‐Bit High‐Speed Direct Digital Frequency Synthesizer
CN102006067B (en) A DDS circuit structure with waveform correction ROM
Alkurwy et al. Implementation of low power compressed ROM for direct digital frequency synthesizer
US11303289B2 (en) Frequency-multiplying direct digital synthesizer
Strollo et al. High-speed direct digital frequency synthesizers in 0.25-/spl mu/m CMOS
Meng Low-power phase accumulator for direct digital frequency synthesizers
Abbas Review of high-speed phase accumulator for direct digital frequency synthesizer
Guo et al. High speed high resolution direct digital frequency synthesizer with non-linear DAC coarse quantization and ROM-based piecewise linear interpolation
Stoica et al. A High-Speed, Area-Optimized, ROM-Less (Co) Sine Wave Synthesis Accelerator
Soudris et al. Alternative direct digital frequency synthesizer architectures with reduced memory size
Kim et al. Multiple trigonometric approximation of sine-amplitude with small ROM size for direct digital frequency synthesizers
Ashrafi et al. A 1GHz direct digital frequency synthesizer based on the quasi-linear interpolation method
Liu et al. A Direct Digital Frequency Synthesizer Based on Optimized Grouping Strategy of Multiple Parallel Excess-Four Rotations