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Geng et al., 2020 - Google Patents
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Geng et al., 2020 - Google Patents

CQNN: a CGRA-based QNN framework

Geng et al., 2020

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Document ID
7255252861616614083
Author
Geng T
Wu C
Tan C
Fang B
Li A
Herbordt M
Publication year
Publication venue
2020 IEEE high performance extreme computing conference (HPEC)

External Links

Snippet

Quantized Neural Networks (QNNs) have drawn tremendous attention since-when compared with Convolution Neural Networks (CNNs)-they often dramatically reduce computation, communication, and storage demands with negligible loss in accuracy. To find …
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Classifications

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    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
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    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
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    • G06F7/50Adding; Subtracting
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
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    • G06F15/80Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
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