SU1247890A2 - Device for determining phase of spectral components - Google Patents

Abstract

The invention relates to computing, in particular to specialized computing devices, for calculating the phase of spectral components in real time. The purpose of the invention is the expansion of the range. dividing the phase of the spectral components (by determining the phase in the range from 0 to 360). The goal is achieved by the fact that the device contains three registers, five elements UNACTAL, three triggers, three shift registers, seven multiplexers, four one-digit sums, a mator, a comparator unit, a subtractor, an IL element 1 and the corresponding connections between nodes devices. 1 il. Yo oo &

Description

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The invention relates to computing, in particular to specialized computing devices, designed to calculate the phase of the spectral components in real time and is an improvement of the known device according to the author. N 1080148,

The purpose of the invention is to expand the range of determining the phase of spectral components (by determining the phase in the range from 0 to 360 °).

The drawing shows the functional scheme of the device. I, -,. . The device contains 1T registers and 2,

elements 3 and 4 are UNEMATICAL, trigger 5, shift register 6, trigger 75 shift register 8, multiplexers 9 and 10, one-bit adders 11 and 12, block 13 comparison, multiplexer 14, one-bit adder 15, register 16, element 17. UNEQUAL DETAIL, trigger 18, shift register 19, multiplexer 20, one-digit adder 21, input 22 specifying the number of shifts, clock input 23, subtractor 24, elements UNABLE 25 and 26, multiplexers 27 and 28, logical element OR.29, multiplexer 30 gating inputs 31 and 32.

: The device works as follows.

The rectified Fourier transform coefficients A (k), B (k) in the serial binary code are entered in the least significant bits in registers 1 and 2. Element 3 UNACTITY analyzes two adjacent bits of the binary number A (k). With each discrepancy between bits on the output of element 3, a signal appears, allowing recording in register 6 of the contents of register 1, not including the high-order bit, as well as entering the next one; its most significant bit is in the trigger 5. The last entry has the place where the first sign and the next significant digit of the number are at the input of element 3. Thus, the number A (k) is normalized. The number B (k) is normalized in a similar manner. Under the control of element 4 NECALLARITY, the mantissa is inserted without the most significant unit in register 8 and following the most significant bit in trigger 7. When the process of entering numbers is finished

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Registers 6 and 8 contain significant parts (mantissas) of the numbers A (k), B (k) without the higher digits, and in triggers 5 and 7 contain the contents of the higher registers 6 and 8, respectively.

Simultaneously with the process of normalizing the numbers A (k) and B (k), their sum is normalized. The sequential code of the sum A (k) + B (k) from the output of the one-bit adder 15 is entered in the low-order bits in register 16. Then the sum is normalized by the described method simultaneously with the normalization of the numbers A (k).

5 B (k). Element 17 UNEQUALITY controls the entry of the sum of the mantissa without the highest significant unit and the next most significant bit of the mantissa in register 19 and trigger 18, respectively.

After the end of the input of numbers under the action of the signal at input 22, the registers 6.8 and 19 shift, during which the binary codes contained in these registers are corrected. Correction of register code 6 is carried out by bitwise summing, starting with the least significant bits, on the one-bit sum of the binary register code 11 with the direct correction code, if the contents of trigger 5 is zero, and backward, if it is equal to one. Direct or reverse, the amendment code is transmitted

 to adder 11 via multiplexer 9, which is controlled by trigger 5. The correction is equal to the binary code of register 6, shifted by 3 bits towards the lower bits.

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At the same time

the binary code of register 8 is corrected on adder 12, multiplexer 10, trigger 7, and binary register code 19 is corrected on adder 21, multiplexer 20 and trigger 18. Block 13 compares the absolute values of A (k) and B (k),. determines the larger one and controls the mx plexer 14 (at its output appears the corrected binary code of the mantissa of a larger number). On the adder 21, the sum mantissa is corrected simultaneously and the corrected mantissa is subtracted to a larger 55 number bitwise. The result obtained at the output of the adder 21 is pushed into the register 19 by successively entering the place of the higher bits.

45

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After n shifts, the correction process is over

, in register 10 is two-

M

, - if 1 IM i1,5;

45

7M -2M, + 3

if 1 M, 1.5; 1, + M, 2,. (1)

M, if 1.5 M, 1.5 M + M 2.

The code for this yrjra-, supplemented by the three most significant bits, depending on the signals 3HA (k), 3HB (k) and B (k) A (k), forms an 11-bit code (at) phase 0, the value of which varies in range from O to 360,

Phase detection from 0 to 360 ° is carried out as follows.

After the correction, the forward or reverse phase code is started from register 19. low bits forward through multiplexer 28. A forward or reverse code appears at the output of multiplexer 28, depending on the control input, which is formed by element 26 UNABILITY, comparing the signals 3HA (k) 3HB (k): and B (k) A (k). The signal 3HA (k) 9, 3HB (k) appears at the output of the element 25 UNEMATICAL, and the signal B (k) A (k) at the output of the one-bit subtractor 24, which implements the function A (k) - B (k) (the rectified values of the A (k), B (k) -sequential code of the low-order bits are sent to the input of the subtractor).

Next, the code from the output of the multiplexer 28 is fed to the first input of the multiplexer 30 and for the first. 8 clocks appear on the serial output of the device. In the ninth clock cycle, at the output of the Multiplexer 30, zero or one appears, respectively, appearing at the output of the multiplexer 28 of the forward or reverse phase code. The next 2 cycles to the output of the multiplexer 30 under the control of the element OR, 29 passes the value from the output of the multiplexer 27. During the operation of the signal at input 31, the signal from the first input of it passes through the signal at input 31, and from the second.

Thus, in the tenth and eleventh clocks under control of the signals at inputs 31 and 32 at the output

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egg code, proportional to the phase in

0-45,

the multiplexer 30 passes the value from the output of the multiplexer 27.

The table shows the phase code & in the range from O to 360 °, taking into account the signs of the spectral components A (k) ,. B (k), represented in Cartesian coordinates on the abscissa and ordinas, respectively. Elements 25 and 26 NECKNESS and multiplexers 27-3 implement the logic functions presented in the table. The code is determined by the formula (1).

The phase is calculated in real time as the Fourier coefficients A (k), B (k) are calculated.

Claims (1)

Invention Formula A device for determining the phase of the spectral components according to ed. No. 1080148, characterized in that, in order to expand the range of phase definitions, the fifth, sixth and seventh multiplexers, the fourth and fifth elements are introduced into it, the UNIQUENESS, the OR element and the subtractor, the output of which is connected to the first input of the fourth element UNCHARTERNESS, the output of which is connected to the control input of the fifth multiplexer, the output of which is connected to the first information input of the sixth multiplexer, the second information input of which is connected to the output of the seventh multiplexer, the first information The second input is combined with the second input of the fourth element UNEQUAL VALUE and connected to the output of the fifth element UNEQUAL VALUE, whose nfep input is combined with the second information input of the seventh multiplexer and is the input of the sign of the real part of the spectral component, the input the sign of the imaginary part of the spectral component of which is the second input of the fifth element INCOMPARANT, the first and The second control inputs of the seventh multiplexer are respectively the first and second gate inputs of the device and are connected respectively with the first and second inputs of the OR element, the output of which is connected to the control input of the sixth multiplexer, the output of which is the output of the device phase, the inputs real and imaginary parts of the spectral component of which are, respectively, the first and second inputs of the subtractor, and the information input of the fifth multiplexer is connected to the output of the n-th bit of the third shift of the register. Editor I. Rybchenko Compiled by A. Baranov Tehred M. Khodanich Proofreader E. Sirohman Order 4T28 / 50 Circulation 671; Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 St (yu51 about nMK) o (K