AU650963B2 - Distributed multiplexer for digital communication system - Google Patents

Description

iso ~09q%6 P/00/011 28/5/91 Regulation 3.2

AUSTRALIA

Patenits Act 1990 00 0

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT Invention Titlc: "DISTRIBUTED MULTIPLEXER FOR DIGITAL COMMUNICATION' SYSTEM" The following statemnirt is a 171ll1 deCscriptionl Of this invention, including the best method of pcrorming it knowvn to uIS:- 2 This inv\ention relaltcs to mu L Iti Iiipliigdcin Ui Ili plcxinlg tech niqucs for signals in digital1 commlUnicationl systems, paitcil iVIccom1 I U nication systems.

In diigital1 corn m n 1ica tionl Systems a plu ro ,'lily of signals may be corn bined or multiplexcd into a highcr rate aggrcga t signal for Iransmission from a transmit Ltrminal to a reccive tcrminal,. At thc rccixe terminal tho mu ltiplcxcd signals a ic scpaiated or clem ultiploxed by a coimipatIible dCii uItilcxcI' in to thc original scpa rato signi as.

011e of the Most C0o11iion1 Iiill l xiIlg/(lenU iplaxiiig techniqlucs is known as timc-division iii uItipeng (TD Ini TI M ,iniformia tioii from difeint input signals is placced in to d iffcren I tinic slots iii al (lfi iid framl St ructuric.

In, typical network( applicaions of owfy it is oftcii ncessary to implement mlti ~plexer-s/dem ILi ItiP lexers Wih clT arcfliCic nfly flex iblc to, aniong othecr thin gs, su pport a variety of ch ann iel comi biti bu also, it is Often i'CCq ired to provkie a iiumiber of separate mu Iiplexes in oiie 0(10pmcnt shelf. A typical multpkcer is partitoned into clhanniel Liiiits wh ichi pr-oxide intIerfaces for iiiform ationi signals to ~~multipleed, aiid a coiimnon Li t wvh lMal oins a Ill Li I tiplexeij/demllUtiplexer- and aggrega te signal initerface. Cli a i ni its am 0(111 1011 monilts niay typically be realised as ci rcu it cwas xwhichi arc fi ted in to a shellf in iiniumibeis to A~ t i nd vd iil i iplexiiig requirements.

A (Advia yuage of the above a pp'ocli is the I ivited flxi bi lily iniduLced by the iieed for a m ixtur e of cliann iel Lit s a i~nd m on Li il s iniai mlI Liuipmniit shelf. The shlf can typicall13 be wired to sLIPppoirtlt Ii cxc rs xxi th a fixed in adim iniumLIiiber h.of channels or a liild iiuimiiber of sepam at W iIilleXeis in a shia red sAlf The ~kiiown approacli becomes partiubt Ia rs w et i xc xvl',' it is (desired( to li pleiie 2s ii i tiplexers thiat suipport a ciii h i t i ni or clianiiiel types. Icir exai p ln voice and otlier service chiainnels.

~Ani object of Itle present iiivxeiition is to providle a niethiod anid arraligemen tl in Which lnuilItipeiCn&g anid dciiiu Ilxi ckng fAiuitioiis are realised inl a d istribuited way wNihout using a common IllLltilc.XCe/d]cmllec LI-PCC1 nit.

to the iii veu tiii there is provided a. methlod of mLi tiplexing/demultiplexing signals inl a digital1 comnlicationl System, saRid method0( comprisng the steps of providinig a pIl ia lity of chianne mi ieanos couipled to a coni nonl bus, each of sai chianiinel means ciiiprisinrg a signal transmit section aiid a sigiialI receive section, provide each signal receive section with receive frame alignmient m-eanlS for direct CIC~~lemu Iilig of recivd channel information, prvide each signal tranosmit section with means to generate a1 tr.1 ia n it framlc alignmnit signal, and Select one signal transmit scction to funoction as a iii ste synch ronkia tioii source upon thic goneratIon of said tra nsm it fin mec align micni signal.

A method according to the iiiet ion cli iiinates the need for sepa ratc rlultiplecr/demultilcxcr unit andl allow\s, flexibility in the number,)CI Of rnultiplexcr/deniu tiplexer groups in a shiared shelf'- in the assignnmcii t of cha nn1cls to theC groups; inl the ISSignlcn)ICI of timc slots or phaIses of a timec Slot to chalnels, in the physical posi tiojig of cline ii ls n id in i le li ia tcs/banrd wid huiiform atioii ca pacity of low Speed chiannrels.

In order tha t the i nvenitioni mayv he read ilv caried iii to ffec, cimibodlimenits thereof will be dlesciibed ini rea on to thle a ccompiinnyinig (lrawxi ngs, i& whiichi Figure I shows a block (Iiagram iiof aI chia nneli OWrfNc provid inrg thie d istribu ted iiuhtiplexing fctIionl Oif [lie prescint ix elitioli.

Figu iv 2 is a agra ii siWi rg 1hle reIntonrsli P betwe i timrie slots aniid dhi i nls in a first order multiplexer a pp 1 ica(ic ni of !hle p rescrit iii yndtori Pigu re 3 is a d iagramii sliowirg (hle relat ioiishiip between tirue slots anrd dianeris ~iii a zero order iiiuIti plexer a ppl ica i r W thre preseiit iniven tioni.

14-4 Figurie 4 shiows aniiother ciiihod irmrit of thle cliannelr iii rface shown iii Figure I 20 Referrinrg to Figu re 1 clianiiiiel iiIrf~cc I is pa rtitlion ed in to a tinrsriiit scctioii 2 anric a receive section 3. A clianiiiiel enird Or uiit i (11t shown1) WOUl( typicall 011oita iii a p-lurna Iiiy of such li aniirieli terfaces. [ilie Ira iisii scctioni 2 Outputs iii ornia tiori ~onto transmiit bus 4 vA a raisriit tiiie slt access arrangeriir I 5. A synchronlisation sourice 6 for the tranrsmiiit tiric slof access ara igenicrit m iay lie selected fromn a local frameii syiclironkiaorin source 7 (iiiaster synic mode), an ii a Gxer amnre sync sourc (Comnmnon sync mioce) froii the frain rueync bus 8, or a synch ronkiatioi sou rce 9 dcrivecl fromi the tin nsm it. bus (slnave sync rilodc). Iii the case ofslave niode openation a fGamer aI grinitarranrgemciit 10( is used to~ sense the frane aI gincn t patten of the tr-anSnmf It us 4SO thiat the tianisiiiit thie Mlot access arra nigenrt, 5 mlay Output inito the correct time slot. Thme tra is i chiannric input I I Iis processed b)y tra nsmnit channei iiierfacc 12 and focI to transiti l~uf loin store 13. A frame alignmnini, word genecrator 14 prod~uces a fRomre a]linniei pa Itm whiich is inserted inito specified tiue slots by On' transmiit time slo access arranogeumenit 5 if the cIransm-it section 2 is configured as a niastor. lIi comnmoi sync nioih oiie chine ndniust Stil be configured as the master.

In the receive section 3 a receive frame alignment arrangement 15 produces a receive frame synchronisation signal 16 enabling the receive time slot access arrangement 17 to access a specified time slot of receive bus 24. Information from the receive time slot access arrangement 17 is passed to receive buffer store 19 and then outputted by receive channel interface 23.

For the selection of programmable parameters, eg. synchronisation mode, a time slot may be selected via an external control interface 21 which may be connected to a microprocessor. Alternatively, the control interface may be connected to the time slot access arrangements 5, 17 with the control information carried in a dedicated time slot. In the case of the time slot access arrangements 5 and 17, the control interface may select the time slot(s) to be accessed. These time slots are located with reference to the frame synchronising signals 6 and 16 respectively.

The channel input 11 and output 22 signals may be digital or analogue at various bit rates or bandwidths. The channel interfaces 12 and 23 convert the signals S .15 to/from a digital form respectively. The buffer 13 and 19 provide temporary storage of the digital information.

The invention may be applied to a first order multiplexing application where -f different signals are multiplexed into different time slots on a bus, eg. time slots I 31 and the frame alignment pattern is in one time slot, eg. time slot 0. An example of such a multiplexing system is in CCITT specifications G.732 and G.737. Figure 2 shows an example of a first order multiplexing application. Channel I is the master and generates the frame alignment pattern (F bits) into time slot 0. Channel 1 also oS outputs data (D bits) into time slot 1. Channel 2 is a slave and in this example is programmed to output data into time slot Alternately the invention may be applied to zero order (sub-rate) multiplexing 0o. 0wherein different signals are multiplexed into the same time slot in different frames *1 (phases). In this case the sub-rate multiframe alignment signal may be contained in one bit of each time slot with data and/or control information in the remaining bits.

An example of such a multiplexing system is in CCITT specification X.50. Figure 3 shows an example of a zero order multiplexing application according to CCITT Each time slot contains an eight bit envelope consisting of a framing bit (F bit), six data bits (D bits) and a supervision bit (S bit). Channel 1 is the master and generates the frame alignment pattern in the first bit (F bit) of a specified time slot (TSn). TSn appears regularly on dhe bus and the master outputs successive bits of the frame alignment pattern into the first bit of successive time slots. In the case of X50 division 3 the frame pattern is 20 bits long and repeats after. 20 cnivclopes. In this cxamnple channel 1 Outputs dlata and supeivision into phase 0 and charnnel 2 outputs data and supervision into phase 7.

Thc invention may alIso be a pplied tO mul.1ti plcxing at morc thiani onc level. As V an example, a com biined zero ad 11 irst cw(1vr dIistribu tedl muIltilcxer' may be imlplcmncn ted by providling separate frarrme align mciit Circuits 10, 15S foi- cacli level aind pro- Miding the time slot access aiangemren s 59 aid 17 wvith both zero aind first order frame synchronising signals. The coii I l bus would then specify the zero order time slot (phase) and first order iii slot (phase) aiid fiost oirder tLme slot to the tini slot access circuit. The master foir each level or inulliplxinrg nleed niot be in the sa me channiel in terfae andl tli total funi t ioi Will norm allyv be dIistribut11edI The irintendton ean iiwk with. differeint frainig iiet hods atit each level of miiultiplexinrg.

wRfrrig to Figurie 4, the buises 25, 26 en nvr a Iiie-divisioii iiiLtileIXeCl sigiia I at 2.048 Mbit/s and coiita in 32 timie slots each with ii iiiformal iou capiacity of 64 kbit/s. Ini this emnbodimiii coinveiitioinal (ceniitalisecl) firot ordier muplexing usiiig 0a commiion Multiplexer uinit 27 is uIsed to multiplex 64 kbits cliumiils to CCITT G732 or G737 Formiat. In this ease the coinmon min tiplex'X~ addS the first Order fi'aiiie ~~lignie nt pattern iin the t Krisn it(I rlfion an iilociks on to the fir'st order fra mell alignment pattern in the ieceivye (Iirect ion. /v fioit ord~er fName synch roi ii ig pulse is outputtd onto bus 28 by the commniiin 1(11plexer unit. Ths pulse is used by the Mva loLIs chiaiiniel uiit on thle bus toi loate t me slots, Each 64kbit/s tiie s&l mn y be uwed to ca iv a niu mber of low speed signals multiplexed for examinple as ill CC ITT reconi nienidtion X.50. lIi this a pplica Lion the inventLion enables X5() mutltiplexed aggregae qigiials to tbe built Uip directly Onl given 64 kbit/s time Slots Of the buses 25, 0 ~~~The frst order fia me syiichironiisinig pukIe froii framiie syiiciniiig bus 28 is fed ~to the time slot access arraiigements 5, 17. The tiie slot access arrangements pass first order time slot specifyinig pulses 29, 30 to the zero Order frame alimnit arrangements 10, 115 The zero order frame sync signals; 6, 16 are fed back to the time s0 slot access arrangemenrts so that a specified zero orer phase vithiii a first order time slot may be accessed. The control bus 21 may be used to program the time slot access arrangemnrts for the required First order lMe slot aiid zCF( Order phip's.

One low speed channel iii each X50 muLltiplefx group is a1ssigned the Master function by selecting the master sync Source 7 and generates the X50 framei synchronisation pattern ini the specifmi 64 kbit/s tiiie slot. The other channel units 6 1 iltiplexing to Lhe saine X50 aggrcgatc time slot may be configurcd as slaves by seicting the slave sync source 10. IF the master channel Fails or is removed, a slave channel may be automatically re-configurilcd to take over the master function.

In this embodiment the channel interfaces I1, 22 may be, for example, CCITT X21 or X21 bis type. Allternatively the interfatce may be dliphase (Manchester) coded to a 2-wire or 4-wire interface for longer (distallce tra 1nsmission. In the case of 2-wire transmission the transmit and receive illnterfaces are combined using a hybrid coupler arrangement. The channel interFaces 12 23 convert betwccn the rcquirecl channel signal and the internal digital forim.

In the above arrangement X50 data ch ainel u ri its may sha re com mon buses with PCM voice channel units etc. aid mIv be fitted in uIIrICestricted combinations.

One X50 channel only is shown in Figure 4 for clarity. This embodiment of the invention provides distributed X50() sub-rate (ZCro orderICI multiplexing to 64 kbit/s time slots without the use of sepa 'a te sub-rate ii lt ip1XCI'r units. This arrangement offers S 15 substantial advantages in terms of space saviig, cost andl lexibility.

o: While the present invention has bccn ldescribed with regard to many particulars, it is understood that equivalents may he readily substituted without departing froni the scope of the invention.

Claims (9)

1. A method of multiplexing/demultiplexing signals in a digital communication system, said method comprising the steps of providing a plurality of channel means coupled to a common bus, each of said channel means comprising a signal transmit section which includes transmit time slot access via which information is coupled to a transmit bus, and a signal receive section which includes receive time slot access means via which information is received via a receive bus, provide each signal receive section with receive frame alignment means for direct demultiplexing of received channel information, provide each signal transmit section with means to generate a transmit frame alignment signal, and select one signal transmit section to on function as a master synchronisation source upon the generation of said transmit frame alignment signal.

2. An arrangement for multiplexing/demultiplexing signals in a digital communication system, said arrangement comprising a plurality of channel means coupled to a common bus, each said channel means comprising a signal transmit section and a signal receive section, each signal receive section including receive frame alignment means for direct demultiplexing of received channel information, means in each signal transmit section to generate a 0 20 transmit frame alignment signal, one signal transmit section being selected to function as a master synchronisation source upon the generation of said transmit frame alignment signal, and wherein each said signal transmit section o includes transmit time slot access means via which information is coupled to a transmit bus, and each signal receive section includes receive time slot access means via which information is received via a receive bus.

3. An arrangement as claimed in claim 2, wherein said transmit time slot access means is synchronised by a synchronisation source selected from a local frame synchronisation source, an external frame synchronisation source, or a synchronisation source dervied from said transmit bus.

4. An arrangement as claimed in claim 3, including a frame alignment arrangement for sensing the frame alignment pattern of said transmit bus when the said synchronisation source is derived therefrom.

I, c r N~ l-il ^1 8 An arrangement as claimed in any one of claims 2 to 4, adapted for first order multiplexing in which different signals are multiplexed into different time slots, the frame alignment pattein being in one time slot.

6. An arrangement as claimed in claim 5, wherein said first order multiplexing is in accordance with CCITT specifications G.732 and G.737.

7. An arrangement as claimed in any one of claims 2 to 6, adapted for zero order multiplexing wherein different signals are multiplexed into the same time slot in different frames.

8, An arrangement as claimed in claim 7, wherein said zero order multiplexing is in accordance with CCITT specifications

9. An arrangement as claimed in claim 8, wherein one low speed signal channel functions as said master synchronisation source, An arrangement for multiplexing/demultiplexing signals in a digital communication system, substantially as herein described with reference to 415 Figures 1 4 of the accompanying drawings. DATED THIS TWENTY-EIGHTH DAY OF APRIL, 1994 ALCATEL AUSTRALIA LIMITED O.N h ABSTRACT For frame synchronising in a TDM system, each channel can operate as a master sync source, in common sync mode, or as a slave. Each channel interface in- cludes on its transmission side a Frame alignment word generator which, when sc- lectecl, enables the channel to act as the mastcr. The interface includes a first alignment cxtraction circuit to extract the common sync signal rom the frame sync bus. A second alignment circuit is used to extract frame alignment from the transmit bus when the channel is in slave mode. Complcmcntary circuits are proviCCded on the rcccive silde of the interface. The distributed multiplexing oF the invention enables different clata formats to be multiplcxcd on a bus in a simple manner. OC C' 0 C" CCC 0 CC 00', i