JPH0337343B2 - - Google Patents

Description

Multiplexer 14 An individual signal insertion method characterized by comprising:

[Detailed description of the invention]

[Summary] A method for inserting individual signals in digital trunk line signal equipment, in which the individual signals are inserted in the clock system of the digital transmission line.

[Industrial application field]

The present invention relates to a data relay system, and more specifically, to an individual signal insertion system that ensures phase synchronization of frames on a transmission path in a digital trunk signal device included in a digital exchange and having an individual signal processing function. .

In the field of digital transmission, digital trunk signal devices based on individual signal processing are widely used, one of which is, for example, a digital trunk in a digital exchange.

FIG. 2 is a block diagram schematically showing a digital switching system including a digital trunk. In the same figure, the private branch exchange (PBX) 1 of office A is
Network (NW) 2, central control unit (CC) 3,
Network clock distribution section 4, digital trunk (#0) 5, digital trunk (#1) 6
It is equipped with

The network clock distribution section 4 includes a clock selection section 8 and a phase locked oscillator (PLO) 9. The digital trunk (#0) 5 performs individual signal processing on frames from the network (NW) 2 or the digital transport device (#0) 10. Digital (#1) 6 is network (NW) 2 or digital transport device (#1) 11
Perform individual signal processing on frames from .

The network synchronization clock distribution device 12 extracts frame synchronization bits from the digital transmission path 13 leading to the B station and the digital transmission path 14 leading to the C station, and based on this extracts the frame synchronization bits to the clock selection section 8 in the network clock distribution section 4. At the same time, the clock signal _CLT of the duplex transmission circuit system is applied to the digital transport device 1.
0 and 11 are also given the transmission line system clock signal _CLT .

The clock selection unit 8 selects a switching system clock signal based on the received transmission line system clock signal.
Create CL _X and give it to network (NW) 2.

In the individual signal processing in the digital trunks 5 and 6, a phase difference exists not only when the frequency water of the clock signal of the electric line system and the clock signal of the exchange system are different, but also even when the high frequencies are the same.
Buffer memory (e.g. elastic store)
The clock system is exchanged through something like this.

It is desirable that the frames on the transmission path do not become out of synchronization due to this clock system conversion.

[Conventional technology]

In conventional digital trunk line signal equipment, individual signals are inserted using the switching system clock signal _CLX . This will be explained using a conventional digital trunk shown in FIG. In the figure, a multiplexer (MPX) 50 and a demultiplexer (DMPX) 51 insert and separate individual signals, and are controlled by an exchange system clock signal _CLX . Elastic Store (ES) 5
Writing of the output of the multiplexer (MPX) 50 to 2 is performed using the switching system clock signal _CL
Reading to the transport device interface unit 54 is performed using the transmission line system clock signal _CLT . Writing from the transfer device interface unit 54 to the elastic store 53 is performed using the clock signal of the transmission line system.
Reading to the _{demultiplexer} 51 is performed using the exchange system clock signal _CLX .

[Problem to be solved by the invention]

As mentioned above, conventionally the switching system clock signal
CL _{X is} used to insert individual signals, but the switching system clock signal CL Disturbances may occur during switching, etc. If an individual signal is inserted using this disturbed clock signal _CL

[Means for solving problems]

FIG. 1 shows a principle block diagram of the individual signal insertion method according to the present invention.

In FIG. 1, a digital trunk line signal device 10 inserts an individual signal into a frame containing audio data and sends it to a digital transmission path _.
a first buffer memory (elastic store) 12 that synchronizes the phase of the individual signal with the clock signal _CLT of the digital transmission line 11;
3, and a multiplexer 14 for multiplexing the outputs of the first and second buffer memories (elastic stores) using the clock signal _CLT of the digital transmission line 11.

[Effect]

Since audio data and individual signals are multiplexed using the clock signal _CLT of the digital transmission line, the frame synchronization bit in the multiplexed frame is accurately synchronized with the clock signal _CLT of the transmission line. Therefore, no loss of synchronization occurs in the game.

〔Example〕

3A and B apply to embodiments of the present invention. The frame format of the digital transmission path and the multi-frame configuration of its time slot TS0 are shown.

In FIG. 3A, as is well known, one frame consisting of a signal time slot TS0 and audio time slots TS1 to TSn is 125 μs, and control signals and audio data are transmitted in multiple frames. Each time slot is 8
It has a bit configuration and has a signal time slot TS0.
The 0th bit to the 4th bit are individual signal bits,
The fifth bit is an alarm bit, the sixth bit is a multi-frame synchronization bit, and the seventh bit is a frame synchronization bit. Audio time slots TS1 to TSn are assigned channels during a call.
Audio data of CH1 to CHn is allocated.

In the multi-frame configuration of the signal time slot TS0, as shown in FIG. 3B, the individual signal bits of the channels CH1 to CHn are assigned to the 0th bit to the 4th bit of frames #0 to #N. That is, for example, the third bit of the #() frame indicates the channel CHi individual signal bit, and if this is "0", the audio channel CHi
indicates that there is no call or the unit is idle.
If it is "1", it indicates that a call is being made.

In an embodiment of the invention, the time slot
By inserting the individual signal bits of TS0 using the clock signal of the digital transmission line after synchronizing the phase of the audio data and the individual signal with the clock signal of the digital transmission line, frame synchronization bits and multi-frame synchronization bits can be synchronized. Aim to prevent misalignment.

FIG. 4 is a block diagram showing a digital trunk as a trunk line signaling device according to an embodiment of the present invention. In the same figure, 401 is a network (NW) interface section, 402 is a central control section (CC) interface section, 403 is an individual signal insertion register, 404 is an individual signal reception register, and 405 to 408 are elastastes. ITSUKU STORE, 4
09 is a multiplexer, 410 is a demultiplexer, 411 is a transfer device interface section, 41
Reference numeral 2 denotes a timing generator for a clock signal extracted from a digital transmission line, and 413 a timing generator for a clock signal within the exchange.

Network (NW) interface section 40
The audio data from 1 is written to the elastic store (ES ₀ ) 405 using the clock signal _CLX , read out using the clock signal _CLT , and input to the multiplexer (MPX) 409. Insert register 40
The individual signals stored in ES 3 are read out in synchronization with _{the clock} signal _CL It is read out from there by the signal _CLT and inputted to the multiplexer (MPX) 409.

In the multiplexer (MPX) 409,
The audio data and the individual signals are multiplexed in synchronization with the clock signal _CLT , and the data in the format shown in FIGS. Ru.

The data received via the transport device interface section 411 is sent to a demultiplexer (DMPX).
At 410, the audio data and the individual signals are separated by the clock signal _CLT . The separated audio data is written to the elastic store (ES ₂ ) using the clock signal _CLT , read from there using the clock signal _CLX , and sent to the NW interface section 4.
01 to the network. On the other hand, the separated individual signals are written into the elastic store (ES ₃ ) using the clock signal _CLT , read from there using the clock signal _CLX , and stored in the reception register 404. The individual signals in the reception register 404 are sent to the timing generator (CL ₀ ) 413 and the pair.
The signal is sent to the central control section (CC) 3 (FIG. 2) via the CC interface section 402 and used for various controls.

〔Effect of the invention〕

As described above, according to the present invention, individual signals are inserted in synchronization with the clock signal of the digital transmission line, so that frame synchronization bits and multi-frame synchronization bits can be easily detected at the other station due to out-of-synchronization, etc. Faults are prevented, which is extremely advantageous for private branch exchange systems.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram showing the individual signal insertion method according to the present invention, FIG. 2 is a block diagram schematically showing a digital switching system including a digital trunk to which the present invention is applied, and FIGS. Frame format of digital transmission line and its time slot applied to embodiments of the invention
FIG. 4 is a block diagram showing a digital trunk as a trunk signal device according to an embodiment of the present invention, and FIG. 5 is a block diagram showing an example of a conventional individual signal insertion method. It is. 10... Trunk line signal device, 11... Digital transmission path, 12... First buffer memory (elastic store), 13... Second buffer memory (elastic store), 14... Multiplexer.

Claims (1)

[Claims] 1. In a digital trunk line signal device 10 that inserts an individual signal into a frame containing audio data and sends it to a digital transmission path, the phase of the audio data is determined by the clock signal (CL _T ) of the digital transmission path 11. a first buffer memory 12 for synchronizing the phase of the individual signal with the clock signal (CL _T ) of the digital transmission line 11; and a second buffer memory 13 for synchronizing the phase of the individual signal with the clock signal (CL T ) of the digital transmission line 11; multiplexed using the clock signal of the